From nobody Mon Oct 6 15:16:36 2025 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CEDF28DB7E; Mon, 21 Jul 2025 10:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753092522; cv=none; b=XWRs/NhWEr8jEmSz8TPQzFwtssiFGHissSM1U1XguewbrLY2LD/OtFwxg/Zaw0GT/1HOvprDItFxTliwS3P3NAPts/dLRhRqTWd4SuCZCO0/IO68dpqWBnPKUYFcM3gffeKQR2KGEuzhJXS5vRDlgjasjnaAaqnpu/llf4/tCb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753092522; c=relaxed/simple; bh=janIChdf5G6IMOEIZktEYbOobBm0Gj/FpYAgXhJJl30=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NMr7OdVLZ75R/wUpRzJNbR2zk/LSxpwPLWKr2EvN2/548I6/92BvhsOaI/8fh1/qc6EkUoAIXt94MlDpTfC5N12bMsRvQeZtiBxI4mqTFeaF+12plnwj1GtLQdtNTFWjlV+r1jwu8knBfBPvjgKx/gUEtxYS5y7B5bOqaT3CLl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=pass smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=ItJCCtQ9; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="ItJCCtQ9" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 961CBC75FC; Mon, 21 Jul 2025 12:08:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1753092511; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=WPwvhrgvdLTtJt+7HBgUaeZ45ADec5RzNRm5Hexhxo0=; b=ItJCCtQ9pBvUdP8KWoh+Emu/C3Krlyaem00jtBM/BPmvJXYeafPcfuLkOwPQMppkT+hnok d1xiLa+Ygkl7jUx++1+P7RZv2484YkJ0nyUHXrByK/2pc/mvbZRMfnKQ70DVmiJ5Fc4Sb1 Nzsj3v7nr5mJU5F+iKkrSpdETmC0+rmKjbUBFTRTU/j4oaBoBfcqvzmJXU67brupkfP3F1 cq5Ptqz1QE522QBHEV41+j4ZbskRlu5Rn/c9cwiOwfuMfGEpkE1uCUj430dCsFYezPHzor NK/5GBdZ4hgGVdTtB2xNn5mkx4DegHzfJfkp+DtS9upnH/m6zLRgHLbtPZABPA== From: Frieder Schrempf To: linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Annette Kobou , Frieder Schrempf , Alexander Stein , Andrej Picej , Fabio Estevam , Frank Li , Liu Ying , Pengutronix Kernel Team , Teresa Remmet , Tim Harvey Subject: [PATCH v2 01/12] arm64: dts: imx8mm-kontron: Add overlay for LTE extension board Date: Mon, 21 Jul 2025 12:05:35 +0200 Message-ID: <20250721100701.115548-2-frieder@fris.de> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250721100701.115548-1-frieder@fris.de> References: <20250721100701.115548-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Annette Kobou This is an addon for the BL i.MX8MM that features an LTE modem, a TPM module, some LEDs and a pushbutton. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx8mm-kontron-bl-lte.dtso | 186 ++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 0b473a23d1200..05d58ce3f6550 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -341,8 +341,10 @@ imx95-19x19-evk-pcie1-ep-dtbs +=3D imx95-19x19-evk.dtb= imx-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-p= cie1-ep.dtb =20 imx8mm-kontron-dl-dtbs :=3D imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo +imx8mm-kontron-bl-lte-dtbs :=3D imx8mm-kontron-bl.dtb imx8mm-kontron-bl-l= te.dtbo =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-dl.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-bl-lte.dtb =20 imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso b/arc= h/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso new file mode 100644 index 0000000000000..324004b0eca3e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2025 Kontron Electronics GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + compatible =3D "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_keys>; + + key-user { + label =3D "user"; + linux,code =3D ; + gpios =3D <&gpio4 12 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led_lte>; + + lte-led1-b { + label =3D "lte-led1-blue"; + color =3D ; + gpios =3D <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + + lte-led1-g { + label =3D "lte-led1-green"; + color =3D ; + gpios =3D <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + lte-led1-r { + label =3D "lte-led1-red"; + color =3D ; + gpios =3D <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-b { + label =3D "lte-led2-blue"; + color =3D ; + gpios =3D <&gpio5 25 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-g { + label =3D "lte-led2-green"; + color =3D ; + gpios =3D <&gpio5 22 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-r { + label =3D "lte-led2-red"; + color =3D ; + gpios =3D <&gpio5 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ecspi3 { + status =3D "disabled"; +}; + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; + + tpm@2e { + compatible =3D "infineon,slb9673", "tcg,tpm-tis-i2c"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm>; + reg =3D <0x2e>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gpio3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio3>; + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "", "VDD_IO_REF", "TPM_PIRQ#", + "TPM_RESET# ", "", "", "", + "", "LTE_LED1_B", "LTE_LED1_G", "", + ""; + + vdd-io-ref-hog { + gpio-hog; + gpios =3D <10 GPIO_ACTIVE_HIGH>; + line-name =3D "VDD_IO_REF"; + output-high; + }; + + tpm-reset-hog { + gpio-hog; + gpios =3D <12 GPIO_ACTIVE_LOW>; + line-name =3D "TPM_RESET#"; + output-low; + }; +}; + +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + gpio-line-names =3D "", "", "LTE_RESET", "", + "", "", "", "", + "", "", "", "LTE_PWRKEY", + "", "", "", "", + "", "", "", "", + "LTE_PWR_EN"; +}; + +&gpio5 { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "LTE_LED2_G", "LTE_LED1_R", + "LTE_LED2_R", "LTE_LED2_B"; +}; + +&iomuxc { + pinctrl_gpio3: gpio3grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* VDD_IO_REF */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x19 /* LTE_RESET */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x19 /* LTE_PWRKEY */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x19 /* LTE_PWR_EN */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x19 /* Pushbutton */ + >; + }; + + pinctrl_gpio_led_lte: gpioledltegrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* LTE_LED1_B */ + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* LTE_LED1_G */ + MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x19 /* LTE_LED1_R */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* LTE_LED2_B */ + MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x19 /* LTE_LED2_G */ + MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x19 /* LTE_LED2_R */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* TPM_PIRQ# */ + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x39 /* TPM_RESET# */ + >; + }; +}; --=20 2.50.1