From nobody Mon Oct 6 12:02:53 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46362285075 for ; Mon, 21 Jul 2025 17:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753119560; cv=none; b=I52Q/fu49duga0IEvYmH55E21AHQbxMvRwitxYkPiHLParHZuBOUjpvp+BI74EW0U0aAoAyHhnHxgplfhsz28OnxJGMjjKgHlf4TI0dOYdHUBz3e3SGmuCcTu7yc5LoYZQaqZHIh2K+wUAhjKNavkfx3lqzT6pIQuahPeppFVjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753119560; c=relaxed/simple; bh=FL2EBBa+wSm77LeCRuxbxYL7cW7Y0BEpaYSJV7FVF5A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VV/RxtFOwVEWeGrASPVmUkA8JWXarW25q1bkY5KELXra6poph8tELoDlHK5RxAhRKyH7gBLIh8Rewu8MCC8hMtq7OejXR9Xc8ArgKkAoMdJMTYgk3IrHUSC0ocVVUqnJJGi8LlzlwUcjPlHPvk3hT1RWKxYrbXI1raicw7clBsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=CRtEapz+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="CRtEapz+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753119556; bh=FL2EBBa+wSm77LeCRuxbxYL7cW7Y0BEpaYSJV7FVF5A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CRtEapz+FWAhM5zcEGnvhUmfHhzRnTaKs8ZI48vJaeYGrWyo4Dg9shRY/fW6oGs1w Y+rhdoZG/7ZpqPOzRDNnHGU+6FS1ifZUq/MSTrFIQ1hqcHrHheje9cSSDLXxO2GwGi pkFE6Zlh3uI+xcLhz1qsg4SBEo37GcUIFDh4ZdE9/bvaAmQojVKejrb6XPqvbqxnA3 Ufkd06epzR0rq4/xxfDGFaELibMIby99JPKovs2b9RSRJsbJsYijGqLiIZAo6WYSlb slrauUWrPL6p52umvpAnvfI2qlNXlpmY05i9IaIEOjnQXceKSFQGW+T3JM1DvZfTpa x8unM6QfhX8vA== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 4460F17E0FC2; Mon, 21 Jul 2025 19:39:16 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 21 Jul 2025 20:39:04 +0300 Subject: [PATCH 1/5] drm/rockchip: vop2: Add high color depth support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-rk3588-10bpc-v1-1-e95a4abcf482@collabora.com> References: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> In-Reply-To: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Take the bits per color channel into consideration when computing DCLK rate. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 186f6452a7d359f079662bc580850929632ea8fe..a714bcbb02de16267e7febbaeb1= eb270c70aaef2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1731,6 +1731,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, clock *=3D 2; } =20 + if (vcstate->output_bpc > 8) + clock =3D DIV_ROUND_CLOSEST(clock * vcstate->output_bpc, 8); + vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); =20 /* --=20 2.50.0 From nobody Mon Oct 6 12:02:53 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B86EC2DECD2 for ; Mon, 21 Jul 2025 17:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753119560; cv=none; b=XI65eUk59hCLFvKcdzx2Ggeo3+sQPij3wfMuCZiPo0P1LYBQDtjKshT03Cdtg1E8XLbOtWLCpKqiGP7OrNNwybuP2ywwfdOOZ/cqa8SFA61YC+U3WotWnQn61wBpiJXYCCa3MlNWP2z8+y8TlVpHHBL1R9X17OqY6TMRhOVLgDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753119560; c=relaxed/simple; bh=kYEq0F90njnkcI6R84CDEdZRsEjUQbwOGs4hs3pzXxU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lSNeyXAFZ932qGvM112mVQXcrlKnE/IaFQ8j4z1oersy++JZWh/c6rBcwO3jyYljatj8kHIPBuS6YVFyaoiHO37yQMRYo4Nu3CWUUf8WUH0iJ+9T+wp+2x+dJzM/GkdHIIJQHA3Q544vh0T/oVAlqJrWgPxHa6IUOeFqPzv3FNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oIiqkPIJ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oIiqkPIJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753119557; bh=kYEq0F90njnkcI6R84CDEdZRsEjUQbwOGs4hs3pzXxU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oIiqkPIJ7qeciaSXJgV5xbEFBQ44SrFgo7o9cDO9lqmAcwgjIsJGtbkARYsq+t77V kaHFGQd8kR8UzIYhWJMIa8QVuellSejcnhsc25q4RJ7iJBFXMqyU0KNcuTbFufZKjB xJhiIxHQ61KalT5TSK1daeIWYhgvF0YnHS5uWIm08IQFDlSo5ZE0iS9CgAdMdD2vx3 4ObiNscn+lHZs6xMLHp42zBrilbTylOu4VXag3pPF67ALPqTVbRr9sv9H5HYi5bCaU FDD4C+pC+lP93Iw+LSOrXBOagbx/gqWBG/KNufB9B9TnYYdMepznKyryKJ0H40PpZt 0Bz0azmiTy9nA== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 08F8917E129E; Mon, 21 Jul 2025 19:39:17 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 21 Jul 2025 20:39:05 +0300 Subject: [PATCH 2/5] drm/bridge: dw-hdmi-qp: Handle platform supported formats and color depth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-rk3588-10bpc-v1-2-e95a4abcf482@collabora.com> References: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> In-Reply-To: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Extend struct dw_hdmi_qp_plat_data to include the supported display output formats and maximum bits per color channel. When provided by the platform driver, use them to setup the HDMI bridge accordingly. Additionally, improve debug logging in dw_hdmi_qp_bridge_atomic_enable() to also show the current HDMI output format and bpc. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 11 +++++++++-- include/drm/bridge/dw_hdmi_qp.h | 4 ++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 39332c57f2c54296f39e27612544f4fbf923863f..25edb35feb0a1c9861fdd4ca5fa= b5c08d44af356 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -848,8 +848,9 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm_= bridge *bridge, return; =20 if (connector->display_info.is_hdmi) { - dev_dbg(hdmi->dev, "%s mode=3DHDMI rate=3D%llu\n", - __func__, conn_state->hdmi.tmds_char_rate); + dev_dbg(hdmi->dev, "%s mode=3DHDMI %s rate=3D%llu bpc=3D%u\n", __func__, + drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_forma= t), + conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc); op_mode =3D 0; hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; } else { @@ -1085,6 +1086,12 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->bridge.vendor =3D "Synopsys"; hdmi->bridge.product =3D "DW HDMI QP TX"; =20 + if (plat_data->supported_formats) + hdmi->bridge.supported_formats =3D plat_data->supported_formats; + + if (plat_data->max_bpc) + hdmi->bridge.max_bpc =3D plat_data->max_bpc; + hdmi->bridge.ddc =3D dw_hdmi_qp_i2c_adapter(hdmi); if (IS_ERR(hdmi->bridge.ddc)) return ERR_CAST(hdmi->bridge.ddc); diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index e9be6d507ad9cdc55f5c7d6d3ef37eba41f1ce74..09c86a053136251c25237751e66= 564386dafdb3c 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -23,6 +23,10 @@ struct dw_hdmi_qp_plat_data { const struct dw_hdmi_qp_phy_ops *phy_ops; void *phy_data; int main_irq; + /* Supported output formats: bitmask of @hdmi_colorspace */ + unsigned int supported_formats; + /* Maximum bits per color channel: 8, 10 or 12 */ + unsigned int max_bpc; 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Mon, 21 Jul 2025 19:39:17 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 21 Jul 2025 20:39:06 +0300 Subject: [PATCH 3/5] drm/rockchip: dw_hdmi_qp: Switch to phy_configure() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-rk3588-10bpc-v1-3-e95a4abcf482@collabora.com> References: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> In-Reply-To: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Stop relying on phy_set_bus_width() based workaround to setup the TMDS character rate and, instead, use the recently introduced HDMI PHY configuration API. This is also a prerequisite to enable high color depth and FRL support. Additionally, move the logic to ->atomic_check() callback where the current mode rate is already provided by the connector state. As a matter of fact this is actually necessary to ensure the link rate is configured before VOP2 attempts to use the PHY PLL as a DCLK source in vop2_crtc_atomic_enable(). The rationale is to restrict any changes of the PHY rate via CCF and, instead, prefer the PHY configuration API for this purpose. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 37 +++++++++++++---------= ---- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 7d531b6f4c098c6c548788dad487ce4613a2f32b..b2dd29347338d58640387adb2b4= 55cc1558d4272 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -95,6 +96,7 @@ struct rockchip_hdmi_qp { struct delayed_work hpd_work; int port_id; const struct rockchip_hdmi_qp_ctrl_ops *ctrl_ops; + unsigned long long tmds_char_rate; }; =20 struct rockchip_hdmi_qp_ctrl_ops { @@ -113,24 +115,9 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); - struct drm_crtc *crtc =3D encoder->crtc; - unsigned long long rate; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); - - if (crtc && crtc->state) { - rate =3D drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode, - 8, HDMI_COLORSPACE_RGB); - /* - * FIXME: Temporary workaround to pass pixel clock rate - * to the PHY driver until phy_configure_opts_hdmi - * becomes available in the PHY API. See also the related - * comment in rk_hdptx_phy_power_on() from - * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c - */ - phy_set_bus_width(hdmi->phy, div_u64(rate, 100)); - } } =20 static int @@ -138,12 +125,26 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); + union phy_configure_opts phy_cfg =3D {}; + int ret; =20 - s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; - s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + return 0; =20 - return 0; + phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + + ret =3D phy_configure(hdmi->phy, &phy_cfg); + if (!ret) { + hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; + s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + } else { + dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); + } + + return ret; } =20 static const struct --=20 2.50.0 From nobody Mon Oct 6 12:02:53 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9609A2E1C55 for ; Mon, 21 Jul 2025 17:39:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753119562; cv=none; b=dtrD4b7tujDcmKiDaGGUXIdxW3wZRKqa1Vt1YyVQ0dDbrsE3L2sG6tGI2tnQtHA+wqfiogCD+WbSgJhFiDhhluiv7CA+7esMBZ5oZaR27W9GwRIejMFsLxvT9j+FVSvcbUvmfEiczO0nn/CUwWC+Sr4uHubscJC6o9F48NSzlNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753119562; c=relaxed/simple; bh=FDxPF4OT2bcKXd+eUAvhu2FvLoFP0u3RBFHt6nkW8Q0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=prF4LjgwvOir78G1SwpGTDZXdbEGrtDhNxt0gMLaB0QU5w5Q9lsdhSV8FkFSG7fdrJHvlrYIs32gBpst1/Tr8/FtUOGJRVQ5RkmEv8YIItIYS/zRHao9aODeBFEY26bLxHgz8P7GnfHk5uBHfyPS+9+gg2fCawgmHD+NWJA8oyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=BUtEsEU1; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="BUtEsEU1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753119558; bh=FDxPF4OT2bcKXd+eUAvhu2FvLoFP0u3RBFHt6nkW8Q0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BUtEsEU1O/71WkTafKm74yVOPcszS9eeyMS6tKeZYgfHzO1y8AnY8WoQFGtRi9Cp+ Uyf/DYYJmSx3eUC1E8MNYrsqiAXUXb0hddQ2T2c6ygy3hLewHC5M856xhJmJrWM4/Q eWpN/3Ojg/sYagdecKE9yBR3Pue7SKOvI1qKYcmzSBY4Q4kg2G/yJ7nixfGhyrp5wt ej5JNj7cHR3vST640/KUX/xGl3m3h/vxZzUJl1eNry8wBtPyRcGI1g+rXfTdP7lcp1 s+YUumTqonDcNjiXUxqqiCa2PPMwcDYe3Mamr1gpxJhu+AJw96oU3pfZD4rcP/t97s bmgYOFivgctDw== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 89AB817E14A9; Mon, 21 Jul 2025 19:39:18 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 21 Jul 2025 20:39:07 +0300 Subject: [PATCH 4/5] drm/rockchip: dw_hdmi_qp: Use bit macros for RK3576 regs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-rk3588-10bpc-v1-4-e95a4abcf482@collabora.com> References: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> In-Reply-To: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 For consistency and improved readability, redefine a few RK3576 specific register configurations by relying on GENMASK() and unshifted values for color depth and output format. Those are not used at the moment, but will be needed soon to support the related features. While at it, drop a few other defines which are unlikely to be ever required. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index b2dd29347338d58640387adb2b455cc1558d4272..578ff5eb87f1e27b9bb9a6a2993= 47b24b45381bb 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -38,21 +38,16 @@ #define RK3576_HDMI_HDCP14_MEM_EN BIT(15) =20 #define RK3576_VO0_GRF_SOC_CON8 0x0020 -#define RK3576_COLOR_FORMAT_MASK (0xf << 4) -#define RK3576_COLOR_DEPTH_MASK (0xf << 8) -#define RK3576_RGB (0 << 4) -#define RK3576_YUV422 (0x1 << 4) -#define RK3576_YUV444 (0x2 << 4) -#define RK3576_YUV420 (0x3 << 4) -#define RK3576_8BPC (0x0 << 8) -#define RK3576_10BPC (0x6 << 8) +#define RK3576_COLOR_DEPTH_MASK GENMASK(11, 8) +#define RK3576_8BPC 0x0 +#define RK3576_10BPC 0x6 +#define RK3576_COLOR_FORMAT_MASK GENMASK(7, 4) +#define RK3576_RGB 0x9 +#define RK3576_YUV422 0x1 +#define RK3576_YUV444 0x2 +#define RK3576_YUV420 0x3 #define RK3576_CECIN_MASK BIT(3) =20 -#define RK3576_VO0_GRF_SOC_CON12 0x0030 -#define RK3576_GRF_OSDA_DLYN (0xf << 12) -#define RK3576_GRF_OSDA_DIV (0x7f << 1) -#define RK3576_GRF_OSDA_DLY_EN BIT(0) - #define RK3576_VO0_GRF_SOC_CON14 0x0038 #define RK3576_I2S_SEL_MASK BIT(0) #define RK3576_SPDIF_SEL_MASK BIT(1) --=20 2.50.0 From nobody Mon Oct 6 12:02:53 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CBDA2E2647 for ; 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Mon, 21 Jul 2025 19:39:19 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 21 Jul 2025 20:39:08 +0300 Subject: [PATCH 5/5] drm/rockchip: dw_hdmi_qp: Add high color depth support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-rk3588-10bpc-v1-5-e95a4abcf482@collabora.com> References: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> In-Reply-To: <20250721-rk3588-10bpc-v1-0-e95a4abcf482@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Since both RK3576 and RK3588 SoCs are capable of handling 10 bpc color depth, introduce a pair of new helpers to program the necessary registers, as well as passing bpc at PHY configuration level. Note max_bpc is unconditionally set to 10 before initializing the QP bridge library, as there is no need to adjust it dynamically, i.e. per SoC variant, for now. While setting up .enc_init() callbacks of rockchip_hdmi_qp_ctrl_ops, also replace the unnecessary whitespace chars before .irq_callback() assignments. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 59 ++++++++++++++++++++++= ++-- 1 file changed, 56 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 578ff5eb87f1e27b9bb9a6a299347b24b45381bb..49d58f1321034b325a0741794a6= 2a279971d5f4c 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -7,6 +7,7 @@ * Author: Cristian Ciocaltea */ =20 +#include #include #include #include @@ -68,6 +69,12 @@ #define RK3588_HDMI1_LEVEL_INT BIT(24) #define RK3588_GRF_VO1_CON3 0x000c #define RK3588_GRF_VO1_CON6 0x0018 +#define RK3588_COLOR_DEPTH_MASK GENMASK(7, 4) +#define RK3588_8BPC 0x0 +#define RK3588_10BPC 0x6 +#define RK3588_COLOR_FORMAT_MASK GENMASK(3, 0) +#define RK3588_RGB 0x0 +#define RK3588_YUV420 0x3 #define RK3588_SCLIN_MASK BIT(9) #define RK3588_SDAIN_MASK BIT(10) #define RK3588_MODE_MASK BIT(11) @@ -96,6 +103,7 @@ struct rockchip_hdmi_qp { =20 struct rockchip_hdmi_qp_ctrl_ops { void (*io_init)(struct rockchip_hdmi_qp *hdmi); + void (*enc_init)(struct rockchip_hdmi_qp *hdmi, struct rockchip_crtc_stat= e *state); irqreturn_t (*irq_callback)(int irq, void *dev_id); irqreturn_t (*hardirq_callback)(int irq, void *dev_id); }; @@ -110,9 +118,16 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); + struct drm_crtc *crtc =3D encoder->crtc; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); + + if (!crtc || !crtc->state) + return; + + if (hdmi->ctrl_ops->enc_init) + hdmi->ctrl_ops->enc_init(hdmi, to_rockchip_crtc_state(crtc->state)); } =20 static int @@ -125,16 +140,19 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, union phy_configure_opts phy_cfg =3D {}; int ret; =20 - if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate && + s->output_bpc =3D=3D conn_state->hdmi.output_bpc) return 0; =20 phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + phy_cfg.hdmi.bpc =3D conn_state->hdmi.output_bpc; =20 ret =3D phy_configure(hdmi->phy, &phy_cfg); if (!ret) { hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + s->output_bpc =3D conn_state->hdmi.output_bpc; } else { dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); } @@ -373,15 +391,49 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip= _hdmi_qp *hdmi) regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } =20 +static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi, + struct rockchip_crtc_state *state) +{ + u32 val; + + if (state->output_bpc =3D=3D 10) + val =3D HIWORD_UPDATE(FIELD_PREP(RK3576_COLOR_DEPTH_MASK, RK3576_10BPC), + RK3576_COLOR_DEPTH_MASK); + else + val =3D HIWORD_UPDATE(FIELD_PREP(RK3576_COLOR_DEPTH_MASK, RK3576_8BPC), + RK3576_COLOR_DEPTH_MASK); + + regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON8, val); +} + +static void dw_hdmi_qp_rk3588_enc_init(struct rockchip_hdmi_qp *hdmi, + struct rockchip_crtc_state *state) +{ + u32 val; + + if (state->output_bpc =3D=3D 10) + val =3D HIWORD_UPDATE(FIELD_PREP(RK3588_COLOR_DEPTH_MASK, RK3588_10BPC), + RK3588_COLOR_DEPTH_MASK); + else + val =3D HIWORD_UPDATE(FIELD_PREP(RK3588_COLOR_DEPTH_MASK, RK3588_8BPC), + RK3588_COLOR_DEPTH_MASK); + + regmap_write(hdmi->vo_regmap, + hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3, + val); +} + static const struct rockchip_hdmi_qp_ctrl_ops rk3576_hdmi_ctrl_ops =3D { .io_init =3D dw_hdmi_qp_rk3576_io_init, - .irq_callback =3D dw_hdmi_qp_rk3576_irq, + .enc_init =3D dw_hdmi_qp_rk3576_enc_init, + .irq_callback =3D dw_hdmi_qp_rk3576_irq, .hardirq_callback =3D dw_hdmi_qp_rk3576_hardirq, }; =20 static const struct rockchip_hdmi_qp_ctrl_ops rk3588_hdmi_ctrl_ops =3D { .io_init =3D dw_hdmi_qp_rk3588_io_init, - .irq_callback =3D dw_hdmi_qp_rk3588_irq, + .enc_init =3D dw_hdmi_qp_rk3588_enc_init, + .irq_callback =3D dw_hdmi_qp_rk3588_irq, .hardirq_callback =3D dw_hdmi_qp_rk3588_hardirq, }; =20 @@ -476,6 +528,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev,= struct device *master, =20 plat_data.phy_ops =3D cfg->phy_ops; plat_data.phy_data =3D hdmi; + plat_data.max_bpc =3D 10; =20 encoder =3D &hdmi->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm, dev->of_node); --=20 2.50.0