From nobody Mon Oct 6 13:39:28 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 198D21F3BB5; Mon, 21 Jul 2025 06:04:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753077890; cv=none; b=NeKmOUF/MVokb6BdiBhXmnzr+POhl92T4lQLPWag/z2JOvoGOV6s7370gynX+DonTHrT0iuWg2TI5GnZs1mj0nIMtAuye1Pj8sjRYYO3cGdO2DRg96go1ZCOtkzMuEZnNQ1Dx5LYX+agYpLGQ1/SKPjMbARYWrT38sDdLvTjwyc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753077890; c=relaxed/simple; bh=3RIKLCbpXuG5IzWRYoD9BqTheBfbi8XdnTcRob2v7tg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nfVDfZT96HZnGRZ58OTbuIISaJZ6x09jzze/1TGFLtcw0BsRt8rySuZc8P3pdMYzZ0ghT8sIrzR4lzzHU8ZCJBL7W2vMi3KrnL+WKEopn9hxdgiFKicKVXQJDBw8Z8P6uq34zov1/0hbDM8Xk3rloLJCkq7j92vymw2AY9BPJ6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HQ8ibeKK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HQ8ibeKK" Received: by smtp.kernel.org (Postfix) with ESMTPS id AD802C4CEF5; Mon, 21 Jul 2025 06:04:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753077889; bh=3RIKLCbpXuG5IzWRYoD9BqTheBfbi8XdnTcRob2v7tg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HQ8ibeKKn4et6M8mJGRuHhq6Rg92YMAyOFrcOaChWL8ZYIO9VQKiynuBY4JUNXkvC wZfJQ+g73+BWoRp3RhJz6cMqvhgNu60JwLXPatwifPhbU4CXEv6YDnIc50eT3x4H9k XlVfYoQMc7jrxdsS3JMof70K3ZG2obnWVBMUknZepTGXS5Pd5PNbEzCU5r+lpuy+bP kVdlOKGYtnaoeAH+Fcz5HX7PEQ0WvF7Jf9J4KckZmNMsrB2qP8XXGNZwK077oeYNcr tP9UTIpC8533RGcNiYhmQelgC2QWXmqx+SUrKFdM8MWGQSMi3dxN+i4TzbBZb+veVM IyTvv4YkEyIQQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91AB2C83F27; Mon, 21 Jul 2025 06:04:49 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 21 Jul 2025 10:04:35 +0400 Subject: [PATCH v5 1/2] arm64: dts: ipq5018: Add CMN PLL node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com> References: <20250721-ipq5018-cmn-pll-v5-0-4cbf3479af65@outlook.com> In-Reply-To: <20250721-ipq5018-cmn-pll-v5-0-4cbf3479af65@outlook.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753077887; l=2619; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=Jc7mpYMgCxpITcEYnscgFXztbHy0Q20lBLLi8g9IFDY=; b=ZlhpHZYcU/pvY451fXhFyhUUQlQkmIA98V5BkMy/NBGcOpKwYuiesMbF60fN8bh1mFZ/AtuOO Nq0FP0/K73kAehBojSK3M402uuZSqXJOoXmo+NGqzQZdJPgAdwtfTRD X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++++++++= -- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 9ce73682e4ae7cde90f151dfcd41a5201ced2aa6..3ddcceaf760dccb39914a117d5d= cc8955fdb94fe 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ =20 #include -#include #include +#include +#include #include #include =20 @@ -29,6 +30,14 @@ gephy_tx_clk: gephy-tx-clk { #clock-cells =3D <0>; }; =20 + ref_96mhz_clk: ref-96mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <2>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -38,6 +47,12 @@ xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; + + xo_clk: xo-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <48000000>; + }; }; =20 cpus { @@ -229,6 +244,20 @@ mdio1: mdio@90000 { status =3D "disabled"; }; =20 + cmn_pll: clock-controller@9b000 { + compatible =3D "qcom,ipq5018-cmn-pll"; + reg =3D <0x0009b000 0x800>; + clocks =3D <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names =3D "ref", + "ahb", + "sys"; + #clock-cells =3D <1>; + assigned-clocks =3D <&cmn_pll IPQ5018_CMN_PLL_CLK>; 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Mon, 21 Jul 2025 06:04:49 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 21 Jul 2025 10:04:36 +0400 Subject: [PATCH v5 2/2] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com> References: <20250721-ipq5018-cmn-pll-v5-0-4cbf3479af65@outlook.com> In-Reply-To: <20250721-ipq5018-cmn-pll-v5-0-4cbf3479af65@outlook.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753077887; l=2156; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=HWWUllR1trQyCJksWvP6XbezGjzhmGW/ycqYEMYXU0o=; b=utsEdfaeW7XHg+/IZpxEEnjkjK+t4jZoXJqHhi9Ol8NQinAfkXtaSRPf8RipZ+r6yZdb2GSZt bOIEvsohy5WBiun+EUBgi9NQvFNjkQcKL/VQvSvv8nkZNdfr1edgIpA X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/bo= ot/dts/qcom/ipq5018-rdp432-c2.dts index 43def95e9275258041e7522ba4098a3767be3df1..df3cbb7c79c4e6c58cba7695691= 827fb8b84e451 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -120,5 +120,6 @@ &usbphy0 { }; =20 &xo_board_clk { - clock-frequency =3D <24000000>; + clock-div =3D <4>; + clock-mult =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/a= rch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a1854378= 86b04b0d99e8e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -124,5 +124,6 @@ uart_pins: uart-pins-state { }; =20 &xo_board_clk { - clock-frequency =3D <24000000>; + clock-div =3D <4>; + clock-mult =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 3ddcceaf760dccb39914a117d5dcc8955fdb94fe..8ae7d76e29c90cb27fae4904aec= 6442edada885e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -44,7 +44,8 @@ sleep_clk: sleep-clk { }; =20 xo_board_clk: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&ref_96mhz_clk>; #clock-cells =3D <0>; }; =20 --=20 2.50.1