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These are required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC from Anlogic, which uses a processor core designed by Nuclei. Signed-off-by: Junhui Liu Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 5d2a7a8d3ac6c666c8b557c2ef385918e5e97bf9..6ace3c66ce58fc15ef7cc70e88f= d1904cb8395b9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -127,6 +127,8 @@ patternProperties: description: Anbernic "^andestech,.*": description: Andes Technology Corporation + "^anlogic,.*": + description: Shanghai Anlogic Infotech Co., Ltd. "^anvo,.*": description: Anvo-Systems Dresden GmbH "^aoly,.*": @@ -968,6 +970,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milianke,.*": + description: Changzhou Milianke Electronic Technology Co., Ltd "^milkv,.*": description: MilkV Technology Co., Ltd "^miniand,.*": @@ -1081,6 +1085,8 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^numonyx,.*": description: Numonyx (deprecated, use micron) deprecated: true --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A54F42DA755; Mon, 21 Jul 2025 15:50:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753113061; cv=pass; b=g+Ips96C3ru0PEO8NcbqM0D17ee5pWKgB5lhKtlTICfvvBWlYklWiWA1O+nHhpER4XPp/hSc6qd6wCNKwI43J1GolLhA6YusDVluZ1uIJ3ChPkRvHcG86Ky5zozi83luo6NC81ystcF9xT273pxLKznQ6TyzZ4ZPWZcGSUD+8sM= ARC-Message-Signature: i=2; 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a=ed25519-sha256; t=1753112991; l=946; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=cdC+gHkr28j2ptGfilNq1eA/ICUbwZpjzhH/BVYbOhg=; b=fAPwZIz/SLTjhDnmuDiXkGxPW6eDmJ/wZ25iYTmNlzRpbbjVsh8a0tgl+ExiijV4KRJtZS4zd MMHGM/CTd8sB4rxyUu3shUbCPjalI8VBGnNuZCKLd0e/apS6EOOInL2 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC. It features a 64-bit architecture and dual-issue, 9-stage pipeline, with lots of optional extensions including V, K, Zc, and more. Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 2c72f148a74b019e46ad5917a0b75d45777c385e..f198d8b1fa328f538b4a2983ca7= 95340337fbd2b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - amd,mbv32 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BFD12D5C9B; Mon, 21 Jul 2025 15:51:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; 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a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External Add Anlogic DR1V90 FPSoC, which is used by the Milianke MLKPAI-FS01 board. Signed-off-by: Junhui Liu Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/riscv/anlogic.yaml | 27 ++++++++++++++++++= ++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documen= tation/devicetree/bindings/riscv/anlogic.yaml new file mode 100644 index 0000000000000000000000000000000000000000..91b1526c99aa3ca9cc7b0e79788= 61408bd017049 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/anlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic SoC-based boards + +maintainers: + - Junhui Liu + +description: + Anlogic SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milianke,mlkpai-fs01 + - const: anlogic,dr1v90 + +additionalProperties: true + +... --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FF292E03E5; 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Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index d85a1a088b35dabc0aa202475b926302705c4cf1..16b8c0bdce82a55765046cfdc8d= 1f85a8dfb3912 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -29,6 +29,7 @@ properties: oneOf: - items: - enum: + - anlogic,dr1v90-clint # Anlogic DR1V90 - canaan,k210-clint # Canaan Kendryte K210 - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10BBE2E0409; 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Signed-off-by: Junhui Liu --- .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index ffc4768bad065276378d23d53d6e81efad0a6b66..cc6de8bb89937859e4405aac5d9= 31b8586ac2ddd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -57,6 +57,7 @@ properties: - const: andestech,nceplic100 - items: - enum: + - anlogic,dr1v90-plic - canaan,k210-plic - sifive,fu540-c000-plic - spacemit,k1-plic --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 020E22E0919; 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a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External The Anlogic DR1V90 SoC integrates a UART controller compatible with snps,dw-apb-uart, operating at a 50 MHz clock. Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 8f1b7f704c5bc7cb9552b7d4825d96199cbc6c4f..ed00eefe17aa11200e0a10637d4= cc10b68948699 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7BA32E2676; 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a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Signed-off-by: Junhui Liu --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debca1469f4a912b3414711eb709baab..de163cdddcda1c08e7c9e98716e= af043d4c4555a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,10 @@ menu "SoC selection" =20 +config ARCH_ANLOGIC + bool "Anlogic SoCs" + help + This enables support for Anlogic SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP =20 --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 190C42E03E6; Mon, 21 Jul 2025 15:52:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1753113107; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=z0Qp3/izL0TY+gD3T8jeqDLAQGqMdDazcJY4P4vPPw4=; b=InnBnQOpzVDUeOPoqFEPZra92raBfL0WxUin+VJO7PE6D0VVwJesEnFbtnoUDX4b qpngp0U5h3qhkF7tOyP7Ojeuf0My7xbKwTUj+cm2gMP/6kXWhStfbd1L/Sks6mstgwR g/4KLOdEgg+gtwf6yW0W24vZ9BVFHAnAOrvKgbAw= Received: by mx.zohomail.com with SMTPS id 1753113105602598.6931403939552; Mon, 21 Jul 2025 08:51:45 -0700 (PDT) From: Junhui Liu Date: Mon, 21 Jul 2025 23:46:14 +0800 Subject: [PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-dr1v90-basic-dt-v1-8-5740c5199c47@pigmoral.tech> References: <20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech> In-Reply-To: <20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753112991; l=4459; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=+EFABcFWlLIRqin+/kMYM/pMww5J+sGA43GWCpn0qnw=; b=JPYOvB0MuwSMHITDJwm54eaor40UxEHbk+iMY+ckuwpB7HhQ0hPaBpwHFTO8WWCJMDNi9uyZA sHHn3R50myBB1v9eypzmwSiPqV8G74iPyDjOuvNEK7PlEqzaswbnNzv X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS part and 94,464 LUTs for the PL part. The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible UART controllers. Currently, a "no4lvl" bootarg is required to force the kernel to use 3-level paging for successful boot. The DR1V90 hangs if SATP is set to 4/5-level paging modes during early boot, as detected in set_satp_mode(). Some basic information of the processor can be obtained by running a simple application from nuclei-sdk [1]: -----Nuclei RISC-V CPU Configuration Information----- MARCHID: 0xc900 MIMPID: 0x20300 ISA: RV64 A B C D F I M P S U MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-S= afety-Mechanism DLEN=3DVLEN/2 ILM: 256 KB has-ecc DLM: 256 KB has-ecc ICACHE: 32 KB(set=3D256,way=3D2,lsize=3D64,ecc=3D1) DCACHE: 32 KB(set=3D256,way=3D2,lsize=3D64,ecc=3D1) TLB: MainTLB(set=3D32,way=3D2,entry=3D1,ecc=3D1) ITLB(entry=3D= 8) DTLB(entry=3D8) IREGION: 0x68000000 128 MB Unit Size Address INFO 64KB 0x68000000 DEBUG 64KB 0x68010000 ECLIC 64KB 0x68020000 TIMER 64KB 0x68030000 PLIC 64MB 0x6c000000 INFO-Detail: mpasize : 0 PPI: 0xf8000000 128 MB -----End of Nuclei CPU INFO----- Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application= /baremetal/cpuinfo/main.c [1] Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 86 +++++++++++++++++++++++++++++= ++++ 1 file changed, 86 insertions(+) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/= anlogic/dr1v90.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e1e3f6b72e56abce5a35e6d7571= c91a64b0fecff --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +/dts-v1/; +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Anlogic DR1V90"; + compatible =3D "anlogic,dr1v90"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <800000000>; + + cpu@0 { + compatible =3D "nuclei,ux900", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zba", "zbb", "z= bc", + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm"; + i-cache-block-size =3D <64>; + i-cache-size =3D <32768>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <32768>; + d-cache-sets =3D <256>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint: timer@68030000 { + compatible =3D "anlogic,dr1v90-clint", "sifive,clint0"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250721-dr1v90-basic-dt-v1-9-5740c5199c47@pigmoral.tech> References: <20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech> In-Reply-To: <20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753112991; l=2221; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=dt4UgCfziITaZN8gOwGd/lnBPhcw0i3TYLGZmxXzCjw=; b=PFeQKGi8OpDfUWCZ23aqkiAxhGwQj3LwwaKmJyPclrDk76VqFNt/v0LbtY3wloDGCSxJ1yDu+ VLk2K9cH0FjBMUjmFh1aro/22kG5mUBwVPgAnzvV/sutG2+t3ucStHC X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External Add support for the Milianke MLKPAI FS01 board based on the Anlogic DR1V90 SoC. The board features 512MB of onboard memory, with the region after 0x1fe00000 reserved for OpenSBI. Currently, the board can boot to a console via UART1, which is connected to the onboard serial chip and routed to the Type-C interface. Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/anlogic/Makefile | 2 ++ arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++= ++++ 3 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 64a898da9aee33f5c10cd332ad59b945615816bf..d423b825160c7cc0248b2581268= 67531b9687e23 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner +subdir-y +=3D anlogic subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anl= ogic/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..87f3b2f418cfa32012df5ae82d1= 7262a9610f90c --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANLOGIC) +=3D dr1v90-mlkpai-fs01.dtb diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/risc= v/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts new file mode 100644 index 0000000000000000000000000000000000000000..6a9dca4b6e39261bdef63df5f15= 8c89a323f1732 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +#include "dr1v90.dtsi" + +/ { + model =3D "Milianke MLKPAI-FS01"; + compatible =3D "milianke,mlkpai-fs01", "anlogic,dr1v90"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x1fe00000>; + }; +}; + +&uart1 { + status =3D "okay"; +}; --=20 2.50.1 From nobody Mon Oct 6 11:55:34 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42F9F2E0917; Mon, 21 Jul 2025 15:52:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753113148; cv=pass; b=bDpNCE3VorVaI81/OcXSV+ib/wkLCK1zdNukEDTd/ZB3ne5w7omHk7qtiXh65v7lyAYTq0VT6s6mXlyf8v/me5Na4bbkm/u5nx4QhdJvBIKdcEl8DGW4kp/d/PKM7qjS3QzxIQrZAaCEa0bmiLje/QMDB+49d2mZghb79MO+MmQ= ARC-Message-Signature: i=2; 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a=ed25519-sha256; t=1753112991; l=717; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=iy4AnDRSlJUF5GnacD/24Ahpd5pwxuoUMab2YIgFR6I=; b=F7m4YRktHeWw0lYcRYa179RBWzXWWpelyXb6jm4svGOwIaksd4Rh1DgjJkDY8+Xh0CY0lJl0a dikF5QwDvx/CUizfQLfBP+0uuEs11Uf/bG5kZ8/hP28BqnqK4FoZf+Y X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External Enable Anlogic SoC config in defconfig to allow the default upstream kernel booting on Milianke MLKPAI-FS01 board. Signed-off-by: Junhui Liu --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fe8bd8afb4183ce871020fb2992a21a13bccbc87..9b096dde47a3a4328cd4c9abae6= 730780ec8fba2 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -22,6 +22,7 @@ CONFIG_USER_NS=3Dy CONFIG_CHECKPOINT_RESTORE=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_PROFILING=3Dy +CONFIG_ARCH_ANLOGIC=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy --=20 2.50.1