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Sun, 20 Jul 2025 01:33:05 -0700 (PDT) Received: from [127.0.0.1] ([2001:250:5800:1002::1d55]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3f46b97sm4079721a91.41.2025.07.20.01.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Jul 2025 01:33:04 -0700 (PDT) From: Zixian Zeng Date: Sun, 20 Jul 2025 16:31:44 +0800 Subject: [PATCH v4 2/4] spi: spi-sg2044-nor: Add configurable chip_info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250720-sfg-spifmc-v4-2-033188ad801e@gmail.com> References: <20250720-sfg-spifmc-v4-0-033188ad801e@gmail.com> In-Reply-To: <20250720-sfg-spifmc-v4-0-033188ad801e@gmail.com> To: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen Wang , Inochi Amaoto , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Longbin Li Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Zixian Zeng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753000358; l=3096; i=sycamoremoon376@gmail.com; s=20250113; h=from:subject:message-id; bh=g46DzEpcJPn1i0I3gZxZ5oIULesc7GWeVCVQQpgoe9c=; b=YukjZRjuG7zBKFA+bLUHLliBzwC6HfzWrgebpe6NZrnhXBeKuzke63c7trXlc8ATk42WV+NB4 W3cceLQ0bkGCGS/lgwlQfEoVojsHeaYJy9zSK89/okcCCNQrWR90uBB X-Developer-Key: i=sycamoremoon376@gmail.com; a=ed25519; pk=OYfH6Z2Nx3aU1r0UZdvhskmddV6KC6V1nyFjsQQt4J8= SG2044 and SG2042 have similar SPI-NOR flash controller design, but have incompatibility which causes existing driver not working on SG2042: 1. SPI-NOR flash controller on SG2042 have no OPT register. 2. FIFO trigger level on SG2042 should be strictly less than 8. So introduce a new configurable chip_info structure to hold the different configuration. Link: https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/SPI-= flash.rst Signed-off-by: Zixian Zeng --- drivers/spi/spi-sg2044-nor.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-sg2044-nor.c b/drivers/spi/spi-sg2044-nor.c index a59aa3fc55d277653d01df9c83b3f0aa08edab46..0ef569eb28b7609df1f23d89a6b= 3e7afc2569c80 100644 --- a/drivers/spi/spi-sg2044-nor.c +++ b/drivers/spi/spi-sg2044-nor.c @@ -84,12 +84,18 @@ =20 #define SPIFMC_MAX_READ_SIZE 0x10000 =20 +struct sg204x_spifmc_chip_info { + bool has_opt_reg; + u32 rd_fifo_int_trigger_level; +}; + struct sg2044_spifmc { struct spi_controller *ctrl; void __iomem *io_base; struct device *dev; struct mutex lock; struct clk *clk; + const struct sg204x_spifmc_chip_info *chip_info; }; =20 static int sg2044_spifmc_wait_int(struct sg2044_spifmc *spifmc, u8 int_typ= e) @@ -139,7 +145,7 @@ static ssize_t sg2044_spifmc_read_64k(struct sg2044_spi= fmc *spifmc, =20 reg =3D sg2044_spifmc_init_reg(spifmc); reg |=3D (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYT= ES_SHIFT; - reg |=3D SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE; + reg |=3D spifmc->chip_info->rd_fifo_int_trigger_level; reg |=3D SPIFMC_TRAN_CSR_WITH_CMD; reg |=3D SPIFMC_TRAN_CSR_TRAN_MODE_RX; =20 @@ -335,7 +341,8 @@ static ssize_t sg2044_spifmc_trans_reg(struct sg2044_sp= ifmc *spifmc, reg |=3D SPIFMC_TRAN_CSR_TRAN_MODE_RX; reg |=3D SPIFMC_TRAN_CSR_TRAN_MODE_TX; =20 - writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT); + if (spifmc->chip_info->has_opt_reg) + writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT); } else { /* * If write values to the Status Register, @@ -457,6 +464,11 @@ static int sg2044_spifmc_probe(struct platform_device = *pdev) ret =3D devm_mutex_init(dev, &spifmc->lock); if (ret) return ret; + spifmc->chip_info =3D device_get_match_data(&pdev->dev); + if (!spifmc->chip_info) { + dev_err(&pdev->dev, "Failed to get specific chip info\n"); + return -EINVAL; + } =20 sg2044_spifmc_init(spifmc); sg2044_spifmc_init_reg(spifmc); @@ -468,8 +480,13 @@ static int sg2044_spifmc_probe(struct platform_device = *pdev) return 0; } =20 +static const struct sg204x_spifmc_chip_info sg2044_chip_info =3D { + .has_opt_reg =3D true, + .rd_fifo_int_trigger_level =3D SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE, +}; + static const struct of_device_id sg2044_spifmc_match[] =3D { - { .compatible =3D "sophgo,sg2044-spifmc-nor" }, + { .compatible =3D "sophgo,sg2044-spifmc-nor", .data =3D &sg2044_chip_info= }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sg2044_spifmc_match); --=20 2.49.0