From nobody Mon Oct 6 17:09:57 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 998A4223DCC; Sun, 20 Jul 2025 10:58:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753009102; cv=none; b=R+kIPS6MnVzlrTOOw1ys0lhO0I50Da81kWhaMqNVLX21AiyUTTlaaYE/UXSm4DylsDFBn34Hpvi3OSGlhSOzy6neteyx1o6/uDB8bU72FjjqMmJ6Hq1OxgunB9AUSmqS9kxybyXpgZXh3adOwhr9AhFziFQsxKhpWgXeymcYWdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753009102; c=relaxed/simple; bh=K4vOGNxLAPCB7vznXiRuV3prmClEMFlvFYDOzQbg+Gk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ix60p89ywlk7etrnCPUpMxKBDEd044JqPHkNXLTSnGNEuMiwruHKAipyqw5c5g8U+CcYyUec2NWQOHC968VEB/1zU79XAIfEMLYhUUgl/rqUuzLS+ND8SsA/b4LbudnDkrtqB6XL5ErFe2LLYl1oPk68ph9p29dfdjc4kf8LNZs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=USk3q7lI; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="USk3q7lI" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56K5eKIo004187; Sun, 20 Jul 2025 10:58:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= cYKwbxeG4hrCkBWA5SBtkwUoQX2g5h/22kGMK82hjNA=; b=USk3q7lIU9/PHB5s aWTpd22dqYwoGsyioCByxFs+j1VqgruXWIvvDsIXt6odUueFRB7rr+21UB9Ant+Q Q0LJdPEl5Q9yahxEpUf87djlGh/Xh2br+lfOWabvu///8kulLKG4RBhKjyYwqKUk F2H+RVc2UOF8GGlwC6+vLf9MUcvSCLDnGr3d4c70BDF4S+hPL5zsaQP2Hfs/dGuU n+LSks8R7BNp+QzlHAtm4gD1I2QW5uzFn3TI8g1yiVuKkF9yg1S9aQvWbutZc4sI WPtXquLtcKNlXa6pFhJaDUy8NYYjA82Cg2DNc538bK5zQvVFqv20qI9KlSkmiYaD maMtcw== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 480451a2p1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 20 Jul 2025 10:58:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56KAw6Wn000466 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 20 Jul 2025 10:58:06 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 20 Jul 2025 03:58:01 -0700 From: Luo Jie Date: Sun, 20 Jul 2025 18:57:16 +0800 Subject: [PATCH net-next v6 09/14] net: ethernet: qualcomm: Initialize PPE port control settings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250720-qcom_ipq_ppe-v6-9-4ae91c203a5f@quicinc.com> References: <20250720-qcom_ipq_ppe-v6-0-4ae91c203a5f@quicinc.com> In-Reply-To: <20250720-qcom_ipq_ppe-v6-0-4ae91c203a5f@quicinc.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lei Wei , Suruchi Agarwal , Pavithra R , "Simon Horman" , Jonathan Corbet , Kees Cook , "Gustavo A. R. Silva" , "Philipp Zabel" CC: , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753009036; l=8504; i=quic_luoj@quicinc.com; s=20250209; h=from:subject:message-id; bh=K4vOGNxLAPCB7vznXiRuV3prmClEMFlvFYDOzQbg+Gk=; b=6FKnKqJre4j0q5/8P4Ss2jkV4jC2tAsakTekm1hkMCmNFTlT3H3Ij2YAvfP3xzcstIcDiAYLP avPKbBPPubQBcKpDzou84kuMJ38sqS7dzzRbfm5LFDXT8fkVIf2+xao X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=pzwy8bU5tJZ5UKGTv28n+QOuktaWuriznGmriA9Qkfc= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=EIMG00ZC c=1 sm=1 tr=0 ts=687ccbbf cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=J0k_80nE0nYP0oceNegA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 0SGGrXAz-ytr2mUuAmu-dnUO4PXJ1wDF X-Proofpoint-GUID: 0SGGrXAz-ytr2mUuAmu-dnUO4PXJ1wDF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIwMDEwNSBTYWx0ZWRfX2CK8Tau5yDB5 y2uBZ4E3vbhSLoNj3TATKUhgUO2P2ih1tyLxT4ivTXDNygXeUZgRaN25xSKjBQmcDJpOTEddmmY KtpOy4T//KG8CGDIkKWyXRNkaIQwM5lQKE5mez/ces6uSV8p6GMoIxs0zL7jZFFj5D5nfaD0iTI uqNCiCftVqKW1TBR/BwbUwCw7uklMLFVr3oXt9a93MWCJHCzv8xcWpdMwiab7jdNNZBgEuyT5KZ 21iQct68wOekPoM17EuUUnIoBIAi5M8ntSwOmcWYgu3Q/mdIR1YfItGRSQW1xrS9mw88n9VoauB 4seWNo6OJWthQvNZxp3kfe5Hj9nWngDzYn7j6kv9SdCtvvUFEZD3+RdUUSGPie3y1ntwdD0FmS2 mwTbZ6ucgojKjXiP54ZUR+yb3Wg+fuRMR+IswVOPgBeB9dBc/Nycvo7eTdlFng1JuBv7jA8e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-19_03,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 mlxscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507200105 Configure the default action as drop when the packet size is more than the configured MTU of physical port. Also enable port specific counters in PPE. Signed-off-by: Luo Jie --- drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 86 ++++++++++++++++++++++= +++- drivers/net/ethernet/qualcomm/ppe/ppe_config.h | 15 +++++ drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 47 ++++++++++++++ 3 files changed, 147 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/e= thernet/qualcomm/ppe/ppe_config.c index 39a01f25f5ef..8b2b9986b895 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c @@ -1178,6 +1178,44 @@ int ppe_sc_config_set(struct ppe_device *ppe_dev, in= t sc, struct ppe_sc_cfg cfg) return regmap_write(ppe_dev->regmap, reg, val); } =20 +/** + * ppe_counter_enable_set - Set PPE port counter enabled + * @ppe_dev: PPE device + * @port: PPE port ID + * + * Enable PPE counters on the given port for the unicast packet, multicast + * packet and VLAN packet received and transmitted by PPE. + * + * Return: 0 on success, negative error code on failure. + */ +int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port) +{ + u32 reg, mru_mtu_val[3]; + int ret; + + reg =3D PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * port; + ret =3D regmap_bulk_read(ppe_dev->regmap, reg, + mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); + if (ret) + return ret; + + PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(mru_mtu_val, true); + PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(mru_mtu_val, true); + ret =3D regmap_bulk_write(ppe_dev->regmap, reg, + mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); + if (ret) + return ret; + + reg =3D PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * port; + ret =3D regmap_set_bits(ppe_dev->regmap, reg, PPE_MC_MTU_CTRL_TBL_TX_CNT_= EN); + if (ret) + return ret; + + reg =3D PPE_PORT_EG_VLAN_TBL_ADDR + PPE_PORT_EG_VLAN_TBL_INC * port; + + return regmap_set_bits(ppe_dev->regmap, reg, PPE_PORT_EG_VLAN_TBL_TX_COUN= TING_EN); +} + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port= _id, const struct ppe_bm_port_config port_cfg) { @@ -1606,6 +1644,48 @@ static int ppe_servcode_init(struct ppe_device *ppe_= dev) return ppe_sc_config_set(ppe_dev, PPE_EDMA_SC_BYPASS_ID, sc_cfg); } =20 +/* Initialize PPE port configurations. */ +static int ppe_port_config_init(struct ppe_device *ppe_dev) +{ + u32 reg, val, mru_mtu_val[3]; + int i, ret; + + /* MTU and MRU settings are not required for CPU port 0. */ + for (i =3D 1; i < ppe_dev->num_ports; i++) { + /* Enable Ethernet port counter */ + ret =3D ppe_counter_enable_set(ppe_dev, i); + if (ret) + return ret; + + reg =3D PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * i; + ret =3D regmap_bulk_read(ppe_dev->regmap, reg, + mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); + if (ret) + return ret; + + /* Drop the packet when the packet size is more than + * the MTU or MRU of the physical interface. + */ + PPE_MRU_MTU_CTRL_SET_MRU_CMD(mru_mtu_val, PPE_ACTION_DROP); + PPE_MRU_MTU_CTRL_SET_MTU_CMD(mru_mtu_val, PPE_ACTION_DROP); + ret =3D regmap_bulk_write(ppe_dev->regmap, reg, + mru_mtu_val, ARRAY_SIZE(mru_mtu_val)); + if (ret) + return ret; + + reg =3D PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * i; + val =3D FIELD_PREP(PPE_MC_MTU_CTRL_TBL_MTU_CMD, PPE_ACTION_DROP); + ret =3D regmap_update_bits(ppe_dev->regmap, reg, + PPE_MC_MTU_CTRL_TBL_MTU_CMD, + val); + if (ret) + return ret; + } + + /* Enable CPU port counters. */ + return ppe_counter_enable_set(ppe_dev, 0); +} + int ppe_hw_config(struct ppe_device *ppe_dev) { int ret; @@ -1626,5 +1706,9 @@ int ppe_hw_config(struct ppe_device *ppe_dev) if (ret) return ret; =20 - return ppe_servcode_init(ppe_dev); + ret =3D ppe_servcode_init(ppe_dev); + if (ret) + return ret; + + return ppe_port_config_init(ppe_dev); } diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h b/drivers/net/e= thernet/qualcomm/ppe/ppe_config.h index 2b3f7e39cc7e..84fa447742e3 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h @@ -233,6 +233,20 @@ struct ppe_sc_cfg { int eip_offset_sel; }; =20 +/** + * enum ppe_action_type - PPE action of the received packet. + * @PPE_ACTION_FORWARD: Packet forwarded per L2/L3 process. + * @PPE_ACTION_DROP: Packet dropped by PPE. + * @PPE_ACTION_COPY_TO_CPU: Packet copied to CPU port per multicast queue. + * @PPE_ACTION_REDIRECT_TO_CPU: Packet redirected to CPU port per unicast = queue. + */ +enum ppe_action_type { + PPE_ACTION_FORWARD =3D 0, + PPE_ACTION_DROP =3D 1, + PPE_ACTION_COPY_TO_CPU =3D 2, + PPE_ACTION_REDIRECT_TO_CPU =3D 3, +}; + int ppe_hw_config(struct ppe_device *ppe_dev); int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, int node_id, bool flow_level, int port, @@ -254,4 +268,5 @@ int ppe_port_resource_get(struct ppe_device *ppe_dev, i= nt port, int *res_start, int *res_end); int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, struct ppe_sc_cfg cfg); +int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port); #endif diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/eth= ernet/qualcomm/ppe/ppe_regs.h index 4cb76313db87..c26bee83252f 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h @@ -40,6 +40,18 @@ #define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value) \ FIELD_MODIFY(PPE_SERVICE_W1_RX_CNT_EN, (tbl_cfg) + 0x1, value) =20 +/* PPE port egress VLAN configurations. */ +#define PPE_PORT_EG_VLAN_TBL_ADDR 0x20020 +#define PPE_PORT_EG_VLAN_TBL_ENTRIES 8 +#define PPE_PORT_EG_VLAN_TBL_INC 4 +#define PPE_PORT_EG_VLAN_TBL_VLAN_TYPE BIT(0) +#define PPE_PORT_EG_VLAN_TBL_CTAG_MODE GENMASK(2, 1) +#define PPE_PORT_EG_VLAN_TBL_STAG_MODE GENMASK(4, 3) +#define PPE_PORT_EG_VLAN_TBL_VSI_TAG_MODE_EN BIT(5) +#define PPE_PORT_EG_VLAN_TBL_PCP_PROP_CMD BIT(6) +#define PPE_PORT_EG_VLAN_TBL_DEI_PROP_CMD BIT(7) +#define PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN BIT(8) + /* PPE queue counters enable/disable control. */ #define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044 #define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2) @@ -65,6 +77,41 @@ #define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \ FIELD_MODIFY(PPE_EG_SERVICE_W1_TX_CNT_EN, (tbl_cfg) + 0x1, value) =20 +/* PPE port control configurations for the traffic to the multicast queues= . */ +#define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00 +#define PPE_MC_MTU_CTRL_TBL_ENTRIES 8 +#define PPE_MC_MTU_CTRL_TBL_INC 4 +#define PPE_MC_MTU_CTRL_TBL_MTU GENMASK(13, 0) +#define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14) +#define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16) + +/* PPE port control configurations for the traffic to the unicast queues. = */ +#define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000 +#define PPE_MRU_MTU_CTRL_TBL_ENTRIES 256 +#define PPE_MRU_MTU_CTRL_TBL_INC 0x10 +#define PPE_MRU_MTU_CTRL_W0_MRU GENMASK(13, 0) +#define PPE_MRU_MTU_CTRL_W0_MRU_CMD GENMASK(15, 14) +#define PPE_MRU_MTU_CTRL_W0_MTU GENMASK(29, 16) +#define PPE_MRU_MTU_CTRL_W0_MTU_CMD GENMASK(31, 30) +#define PPE_MRU_MTU_CTRL_W1_RX_CNT_EN BIT(0) +#define PPE_MRU_MTU_CTRL_W1_TX_CNT_EN BIT(1) +#define PPE_MRU_MTU_CTRL_W1_SRC_PROFILE GENMASK(3, 2) +#define PPE_MRU_MTU_CTRL_W1_INNER_PREC_LOW BIT(31) +#define PPE_MRU_MTU_CTRL_W2_INNER_PREC_HIGH GENMASK(1, 0) + +#define PPE_MRU_MTU_CTRL_SET_MRU(tbl_cfg, value) \ + FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MRU, tbl_cfg, value) +#define PPE_MRU_MTU_CTRL_SET_MRU_CMD(tbl_cfg, value) \ + FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MRU_CMD, tbl_cfg, value) +#define PPE_MRU_MTU_CTRL_SET_MTU(tbl_cfg, value) \ + FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MTU, tbl_cfg, value) +#define PPE_MRU_MTU_CTRL_SET_MTU_CMD(tbl_cfg, value) \ + FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MTU_CMD, tbl_cfg, value) +#define PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_MRU_MTU_CTRL_W1_RX_CNT_EN, (tbl_cfg) + 0x1, value) +#define PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_MRU_MTU_CTRL_W1_TX_CNT_EN, (tbl_cfg) + 0x1, value) + /* PPE service code configuration for destination port and counter. */ #define PPE_IN_L2_SERVICE_TBL_ADDR 0x66000 #define PPE_IN_L2_SERVICE_TBL_ENTRIES 256 --=20 2.34.1