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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lei Wei , Suruchi Agarwal , Pavithra R , "Simon Horman" , Jonathan Corbet , Kees Cook , "Gustavo A. R. Silva" , "Philipp Zabel" CC: , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753009036; l=23683; i=quic_luoj@quicinc.com; s=20250209; h=from:subject:message-id; bh=z/p2kh/oDBWqC8FrgmXr12XNqLuHhF77kn3fLgTiQik=; b=6LtBHc/030u7bHIl7obUjKUEgr+l9uEqpRMASalzzSY4uTMeJUvMA9wTc7+71kD0UkBbL4GJs LNaWTvguk3CBDuY4j5r9joee4r7slqQgDzzbDDihFoMoQHPcpGL6v/z X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=pzwy8bU5tJZ5UKGTv28n+QOuktaWuriznGmriA9Qkfc= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=EIMG00ZC c=1 sm=1 tr=0 ts=687ccb98 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=v1KnxslhLN2fqV9aa6wA:9 a=QEXdDO2ut3YA:10 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: cOQw7onQKLtvNAI-70Dn2A_DnnscTp4c X-Proofpoint-GUID: cOQw7onQKLtvNAI-70Dn2A_DnnscTp4c X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIwMDEwNCBTYWx0ZWRfXw/jMWQm6N2G/ qXw6tYFAQExUVzbGmv/l6yG7O2iptFBkRWBDQPWx0ZidyFzRVJ+svzQwWoFL2+b6AB9VUtDvD+C afzxrPcQzyGCv8fCy3Y0gvsjbnITfQzT0Y0J9CyXkJ6MD0/necmrydqkPe6YnqgoXAlLXNqhB+u UZLRiCopV0RemXjFPTkciPyh1XZMtNlXo5IO7RnxfrKPBrQeY8bIUgJmQZKt2Jk/2hwoXjZ10lz 9tgelUuIE0xxnkCSuI+pTfpEvwoPQwJ9zG5Z3uRoUi201MjhLJyW0Dny1IQlMEuPhyyopaiFGHw S0uPWEXec8Wp3mk1ya4Lc9ZVCrkFFZ3aLSjzKVMK4DiXg1U771gdiV6wFaIXTbv4NPPmXvbZkoY TVY4LCyl388wWY9CCqzTodvidKy0YpAu7FmPj0QrpdZd1On8ikU/BaeMCBHCNz7pkYuVLYzA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-19_03,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 mlxscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507200104 The PPE (packet process engine) hardware block is available in Qualcomm IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which are used to connect with external PHY devices by PCS. It includes an L2 switch function for bridging packets among the 6 ethernet ports and the CPU port. The CPU port enables packet transfer between the ethernet ports and the ARM cores in the SoC, using the ethernet DMA. The PPE also includes packet processing offload capabilities for various networking functions such as route and bridge flows, VLANs, different tunnel protocols and VPN. The PPE switch is modeled according to the ethernet switch schema, with additional properties defined for the switch node for interrupts, clocks, resets, interconnects and Ethernet DMA. The switch port node is extended with additional properties for clocks and resets. Signed-off-by: Luo Jie --- .../devicetree/bindings/net/qcom,ipq9574-ppe.yaml | 529 +++++++++++++++++= ++++ 1 file changed, 529 insertions(+) diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/= Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml new file mode 100644 index 000000000000..d48169a8ba7c --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -0,0 +1,529 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ packet process engine (PPE) + +maintainers: + - Luo Jie + - Lei Wei + - Suruchi Agarwal + - Pavithra R + +description: | + The Ethernet functionality in the PPE (Packet Process Engine) is compris= ed + of three components, the switch core, port wrapper and Ethernet DMA. + + The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and + two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet + port to host CPU communication using Ethernet DMA. The other is used + communicating to the EIP engine which is used for IPsec offload. On the + IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with exter= nal + Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue + Management) and SCH (Scheduler) modules for supporting the packet proces= sing. + + The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (= PCS) + supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. = There + are 3 UNIPHY (PCS) instances supported on the IPQ9574. + + Ethernet DMA is used to transmit and receive packets between the six Eth= ernet + ports and ARM host CPU. + + The follow diagram shows the PPE hardware block along with its connectiv= ity + to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, + NSS clock controller) and ethernet PCS/PHY blocks. For depicting the PHY + connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used a= s an + example. + + +---------+ + | 48 MHZ | + +----+----+ + |(clock) + v + +----+----+ + +------| CMN PLL | + | +----+----+ + | |(clock) + | v + | +----+----+ +----+----+ (clock) +----+----+ + | +---| NSSCC | | GCC |--------->| MDIO | + | | +----+----+ +----+----+ +----+----+ + | | |(clock & reset) |(clock) + | | v v + | | +----+---------------------+--+----------+----------+---------+ + | | | +-----+ |EDMA FIFO | | EIP FIFO| + | | | | SCH | +----------+ +---------+ + | | | +-----+ | | | + | | | +------+ +------+ +-------------------+ | + | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | + | | | +------+ +------+ +-------------------+ | + | | | | | + | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | + | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | + | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | + | | | | | | | | | | + | | +-----+---------+---------+---------+---------+---------+-----+ + | | | | | | | | + | | +---+---------+---------+---------+---+ +---+---+ +---+---+ + +--+---->| PCS0 | | PCS1 | | PCS2 | + |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ + | | | | | | | + | +---+---------+---------+---------+---+ +---+---+ +---+---+ + +------->| QCA8075 PHY | | PHY4 | | PHY5 | + (clock) +-------------------------------------+ +-------+ +-------+ + +properties: + compatible: + enum: + - qcom,ipq9574-ppe + + reg: + maxItems: 1 + + clocks: + items: + - description: PPE core clock from NSS clock controller + - description: PPE APB (Advanced Peripheral Bus) clock from NSS cloc= k controller + - description: PPE ingress process engine clock from NSS clock contr= oller + - description: PPE BM, QM and scheduler clock from NSS clock control= ler + + clock-names: + items: + - const: ppe + - const: apb + - const: ipe + - const: btq + + resets: + maxItems: 1 + description: PPE reset, which is necessary before configuring PPE hard= ware + + interrupts: + maxItems: 1 + description: PPE switch miscellaneous interrupt + + interconnects: + items: + - description: Clock path leading to PPE switch core function + - description: Clock path leading to PPE register access + - description: Clock path leading to QoS generation + - description: Clock path leading to timeout reference + - description: Clock path leading to NSS NOC from memory NOC + - description: Clock path leading to memory NOC from NSS NOC + - description: Clock path leading to enhanced memory NOC from NSS NOC + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: qos_gen + - const: timeout_ref + - const: nssnoc_memnoc + - const: memnoc_nssnoc + - const: memnoc_nssnoc_1 + + ethernet-dma: + type: object + additionalProperties: false + description: + EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM + host CPU. There are 32 TX descriptor rings, 32 TX completion rings, + 24 RX descriptor rings and 8 RX fill rings supported. + + properties: + clocks: + items: + - description: EDMA system clock from NSS Clock Controller + - description: EDMA APB (Advanced Peripheral Bus) clock from + NSS Clock Controller + + clock-names: + items: + - const: sys + - const: apb + + resets: + maxItems: 1 + description: EDMA reset from NSS clock controller + + interrupts: + minItems: 65 + maxItems: 65 + + interrupt-names: + minItems: 65 + maxItems: 65 + description: + Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ri= ng interrupts. + Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring inte= rrupts. + Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ri= ng interrupts. + Interrupt "misc" is the Ethernet DMA miscellaneous error interru= pt. + + required: + - clocks + - clock-names + - resets + - interrupts + - interrupt-names + +patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^ethernet-port@[1-6]+$": + type: object + unevaluatedProperties: false + $ref: ethernet-switch-port.yaml# + + properties: + reg: + minimum: 1 + maximum: 6 + description: PPE Ethernet port ID + + clocks: + items: + - description: Port MAC clock from NSS clock controller + - description: Port RX clock from NSS clock controller + - description: Port TX clock from NSS clock controller + + clock-names: + items: + - const: mac + - const: rx + - const: tx + + resets: + items: + - description: Port MAC reset from NSS clock controller + - description: Port RX reset from NSS clock controller + - description: Port TX reset from NSS clock controller + + reset-names: + items: + - const: mac + - const: rx + - const: tx + + required: + - reg + - clocks + - clock-names + - resets + - reset-names + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interconnects + - interconnect-names + - ethernet-dma + +allOf: + - $ref: ethernet-switch.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + ethernet-switch@3a000000 { + compatible =3D "qcom,ipq9574-ppe"; + reg =3D <0x3a000000 0xbef800>; + clocks =3D <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>; + clock-names =3D "ppe", + "apb", + "ipe", + "btq"; + resets =3D <&nsscc PPE_FULL_RESET>; + interrupts =3D ; + interconnects =3D <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PP= E>, + <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_= PPE_CFG>, + <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_Q= OSGEN_REF>, + <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_= TIMEOUT_REF>, + <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSS= NOC>, + <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNO= C>, + <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_ME= M_NOC_1>; + interconnect-names =3D "ppe", + "ppe_cfg", + "qos_gen", + "timeout_ref", + "nssnoc_memnoc", + "memnoc_nssnoc", + "memnoc_nssnoc_1"; + + ethernet-dma { + clocks =3D <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; + clock-names =3D "sys", + "apb"; + resets =3D <&nsscc EDMA_HW_RESET>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "txcmpl_0", + "txcmpl_1", + "txcmpl_2", + "txcmpl_3", + "txcmpl_4", + "txcmpl_5", + "txcmpl_6", + "txcmpl_7", + "txcmpl_8", + "txcmpl_9", + "txcmpl_10", + "txcmpl_11", + "txcmpl_12", + "txcmpl_13", + "txcmpl_14", + "txcmpl_15", + "txcmpl_16", + "txcmpl_17", + "txcmpl_18", + "txcmpl_19", + "txcmpl_20", + "txcmpl_21", + "txcmpl_22", + "txcmpl_23", + "txcmpl_24", + "txcmpl_25", + "txcmpl_26", + "txcmpl_27", + "txcmpl_28", + "txcmpl_29", + "txcmpl_30", + "txcmpl_31", + "rxfill_0", + "rxfill_1", + "rxfill_2", + "rxfill_3", + "rxfill_4", + "rxfill_5", + "rxfill_6", + "rxfill_7", + "rxdesc_0", + "rxdesc_1", + "rxdesc_2", + "rxdesc_3", + "rxdesc_4", + "rxdesc_5", + "rxdesc_6", + "rxdesc_7", + "rxdesc_8", + "rxdesc_9", + "rxdesc_10", + "rxdesc_11", + "rxdesc_12", + "rxdesc_13", + "rxdesc_14", + "rxdesc_15", + "rxdesc_16", + "rxdesc_17", + "rxdesc_18", + "rxdesc_19", + "rxdesc_20", + "rxdesc_21", + "rxdesc_22", + "rxdesc_23", + "misc"; + }; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-port@1 { + reg =3D <1>; + phy-mode =3D "qsgmii"; + managed =3D "in-band-status"; + phy-handle =3D <&phy0>; + pcs-handle =3D <&pcs0_ch0>; + clocks =3D <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>; + clock-names =3D "mac", + "rx", + "tx"; + resets =3D <&nsscc PORT1_MAC_ARES>, + <&nsscc PORT1_RX_ARES>, + <&nsscc PORT1_TX_ARES>; + reset-names =3D "mac", + "rx", + "tx"; + }; + + ethernet-port@2 { + reg =3D <2>; + phy-mode =3D "qsgmii"; + managed =3D "in-band-status"; + phy-handle =3D <&phy1>; + pcs-handle =3D <&pcs0_ch1>; + clocks =3D <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>; + clock-names =3D "mac", + "rx", + "tx"; + resets =3D <&nsscc PORT2_MAC_ARES>, + <&nsscc PORT2_RX_ARES>, + <&nsscc PORT2_TX_ARES>; + reset-names =3D "mac", + "rx", + "tx"; + }; + + ethernet-port@3 { + reg =3D <3>; + phy-mode =3D "qsgmii"; + managed =3D "in-band-status"; + phy-handle =3D <&phy2>; + pcs-handle =3D <&pcs0_ch2>; + clocks =3D <&nsscc NSS_CC_PORT3_MAC_CLK>, + <&nsscc NSS_CC_PORT3_RX_CLK>, + <&nsscc NSS_CC_PORT3_TX_CLK>; + clock-names =3D "mac", + "rx", + "tx"; + resets =3D <&nsscc PORT3_MAC_ARES>, + <&nsscc PORT3_RX_ARES>, + <&nsscc PORT3_TX_ARES>; + reset-names =3D "mac", + "rx", + "tx"; + }; + + ethernet-port@4 { + reg =3D <4>; + phy-mode =3D "qsgmii"; + managed =3D "in-band-status"; + phy-handle =3D <&phy3>; + pcs-handle =3D <&pcs0_ch3>; + clocks =3D <&nsscc NSS_CC_PORT4_MAC_CLK>, + <&nsscc NSS_CC_PORT4_RX_CLK>, + <&nsscc NSS_CC_PORT4_TX_CLK>; + clock-names =3D "mac", + "rx", + "tx"; + resets =3D <&nsscc PORT4_MAC_ARES>, + <&nsscc PORT4_RX_ARES>, + <&nsscc PORT4_TX_ARES>; + reset-names =3D "mac", + "rx", + "tx"; + }; + + ethernet-port@5 { + reg =3D <5>; + phy-mode =3D "usxgmii"; + managed =3D "in-band-status"; + phy-handle =3D <&phy4>; + pcs-handle =3D <&pcs1_ch0>; + clocks =3D <&nsscc NSS_CC_PORT5_MAC_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK>, + <&nsscc NSS_CC_PORT5_TX_CLK>; + clock-names =3D "mac", + "rx", + "tx"; + resets =3D <&nsscc PORT5_MAC_ARES>, + <&nsscc PORT5_RX_ARES>, + <&nsscc PORT5_TX_ARES>; + reset-names =3D "mac", + "rx", + "tx"; + }; + + ethernet-port@6 { + reg =3D <6>; + phy-mode =3D "usxgmii"; + managed =3D "in-band-status"; + phy-handle =3D <&phy5>; + pcs-handle =3D <&pcs2_ch0>; + clocks =3D <&nsscc NSS_CC_PORT6_MAC_CLK>, + <&nsscc NSS_CC_PORT6_RX_CLK>, + <&nsscc NSS_CC_PORT6_TX_CLK>; + clock-names =3D "mac", + "rx", + "tx"; + resets =3D <&nsscc PORT6_MAC_ARES>, + <&nsscc PORT6_RX_ARES>, + <&nsscc PORT6_TX_ARES>; + reset-names =3D "mac", + "rx", + "tx"; + }; + }; + }; --=20 2.34.1