From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 86A53149C41; Sat, 19 Jul 2025 04:37:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899875; cv=none; b=OA5dv3xP3PmS85hPG4blibL4842ziHoKmGpfmm7lWTYkJ/E0Kz/Ohc9QHQgc0Mb7Qwbt18tGbZ4u7JKOrcvVB6GB1C1JmZpRaG9KDkPth31uApnj3nlXQ2KQ3Ppjq1KjJF+Qj2G4sbmkRJEhek/gwSJy9GOoBUQBzLWNDEd4fdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899875; c=relaxed/simple; bh=/pQppYO1yCT8qPFWYW6OyV6VDHNQ/uI+qcbhsRfbKYM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hewV39wO4d8yEsS/bqw5x23bMhuT0guAyBgYn/CVYhBMmBupaWk1t8W51QvJuw8dWICtaV2BS4N/jT5g3wgTb6eQmMK3rH8BAOtp/m0m8/AONODZHA2SJwrNZigsURiPuA8onzzGRg3rYL6gyxabQ405ylI1z2UVCD67SpSKrF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC60A15A1; Fri, 18 Jul 2025 21:37:45 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A29E93F66E; Fri, 18 Jul 2025 21:37:51 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 1/8] arm64/gcs: task_gcs_el0_enable() should use passed task Date: Fri, 18 Jul 2025 23:37:33 -0500 Message-ID: <20250719043740.4548-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Mark Rutland noticed that the task parameter is ignored and 'current' is being used instead. Since this is usually what its passed, it hasn't yet been causing problems but likely will as the code gets more testing. But, once this is fixed, it creates a new bug in copy_thread_gcs() since the gcs_el_mode isn't yet set for the task before its being checked. Move gcs_alloc_thread_stack() after the new task's gcs_el0_mode initialization to avoid this. Fixes: fc84bc5378a8 ("arm64/gcs: Context switch GCS state for EL0") Signed-off-by: Jeremy Linton Reviewed-by: Mark Brown --- arch/arm64/include/asm/gcs.h | 2 +- arch/arm64/kernel/process.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index f50660603ecf..5bc432234d3a 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -58,7 +58,7 @@ static inline u64 gcsss2(void) =20 static inline bool task_gcs_el0_enabled(struct task_struct *task) { - return current->thread.gcs_el0_mode & PR_SHADOW_STACK_ENABLE; + return task->thread.gcs_el0_mode & PR_SHADOW_STACK_ENABLE; } =20 void gcs_set_el0_mode(struct task_struct *task); diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 08b7042a2e2d..3e1baff5e88d 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -307,13 +307,13 @@ static int copy_thread_gcs(struct task_struct *p, p->thread.gcs_base =3D 0; p->thread.gcs_size =3D 0; =20 + p->thread.gcs_el0_mode =3D current->thread.gcs_el0_mode; + p->thread.gcs_el0_locked =3D current->thread.gcs_el0_locked; + gcs =3D gcs_alloc_thread_stack(p, args); if (IS_ERR_VALUE(gcs)) return PTR_ERR((void *)gcs); =20 - p->thread.gcs_el0_mode =3D current->thread.gcs_el0_mode; - p->thread.gcs_el0_locked =3D current->thread.gcs_el0_locked; - return 0; } =20 --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 347CF21ABD5; Sat, 19 Jul 2025 04:37:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899876; cv=none; b=iaCjF/5B/10fmKDZ/D5PRWU0w72+OA44FwTch9CMrm9JbU4LxexgXNbpzQUBXDf1fwpubqykT1VrDYFIPl4KsdlN2ckLiWfFPoXLmGL2flFVsLA29T6XrAH8Ojb9VDDe5xVEoy6yCGAIkRoEvBEveQEwDRk0kN1B562NrZSTSrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899876; c=relaxed/simple; bh=9P2954cNJ8XHv3MEpXhgG8WzfYYUFsuLqaxFnmm0PrM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QWJxJLrvTYjqoUGZB7d/0YHrpJbqjLyR9MU3I8nZfmUYXfI00OCWREFxjlx+dmKjF+N3Jfmn26Mc1e66p1J5ajxwjEhBhvmIv/m/jrYUa1SJL0bqteBbNdUKP79kFRBlD/H1hxUnpCSPDSZOPl2792umCjBGbKWvkErySYLIDf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CEB51CC4; Fri, 18 Jul 2025 21:37:47 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 661563F66E; Fri, 18 Jul 2025 21:37:53 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 2/8] arm64: probes: Break ret out from bl/blr Date: Fri, 18 Jul 2025 23:37:34 -0500 Message-ID: <20250719043740.4548-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare for GCS by breaking RET out into its own function, where it makes more sense to encapsulate the new behavior independent from the branch instructions. Signed-off-by: Jeremy Linton Reviewed-by: Catalin Marinas --- arch/arm64/kernel/probes/decode-insn.c | 7 ++++--- arch/arm64/kernel/probes/simulate-insn.c | 10 +++++++++- arch/arm64/kernel/probes/simulate-insn.h | 3 ++- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/pro= bes/decode-insn.c index 6438bf62e753..4137cc5ef031 100644 --- a/arch/arm64/kernel/probes/decode-insn.c +++ b/arch/arm64/kernel/probes/decode-insn.c @@ -108,9 +108,10 @@ arm_probe_decode_insn(u32 insn, struct arch_probe_insn= *api) aarch64_insn_is_bl(insn)) { api->handler =3D simulate_b_bl; } else if (aarch64_insn_is_br(insn) || - aarch64_insn_is_blr(insn) || - aarch64_insn_is_ret(insn)) { - api->handler =3D simulate_br_blr_ret; + aarch64_insn_is_blr(insn)) { + api->handler =3D simulate_br_blr; + } else if (aarch64_insn_is_ret(insn)) { + api->handler =3D simulate_ret; } else { /* * Instruction cannot be stepped out-of-line and we don't diff --git a/arch/arm64/kernel/probes/simulate-insn.c b/arch/arm64/kernel/p= robes/simulate-insn.c index 4c6d2d712fbd..09a0b36122d0 100644 --- a/arch/arm64/kernel/probes/simulate-insn.c +++ b/arch/arm64/kernel/probes/simulate-insn.c @@ -126,7 +126,7 @@ simulate_b_cond(u32 opcode, long addr, struct pt_regs *= regs) } =20 void __kprobes -simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs) +simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs) { int xn =3D (opcode >> 5) & 0x1f; =20 @@ -138,6 +138,14 @@ simulate_br_blr_ret(u32 opcode, long addr, struct pt_r= egs *regs) set_x_reg(regs, 30, addr + 4); } =20 +void __kprobes +simulate_ret(u32 opcode, long addr, struct pt_regs *regs) +{ + int xn =3D (opcode >> 5) & 0x1f; + + instruction_pointer_set(regs, get_x_reg(regs, xn)); +} + void __kprobes simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs) { diff --git a/arch/arm64/kernel/probes/simulate-insn.h b/arch/arm64/kernel/p= robes/simulate-insn.h index efb2803ec943..9e772a292d56 100644 --- a/arch/arm64/kernel/probes/simulate-insn.h +++ b/arch/arm64/kernel/probes/simulate-insn.h @@ -11,7 +11,8 @@ void simulate_adr_adrp(u32 opcode, long addr, struct pt_regs *regs); void simulate_b_bl(u32 opcode, long addr, struct pt_regs *regs); void simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs); -void simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs); +void simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs); +void simulate_ret(u32 opcode, long addr, struct pt_regs *regs); void simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs); void simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs); void simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs); --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D899F21D5BE; Sat, 19 Jul 2025 04:37:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899878; cv=none; b=kLDH+DuI6kBSKzNIXpPG5U0D1bNS0oEhAobsw1aJik0qFa7HJ3e3xyV/FRqeLlGNnF7gFrKAwwE8nBADuAhPztB3153HZA4GeTmcTW0U+dw52hc3o4fIgBOMGCXRPi1+5yDFG9YkWepbzTYjplor2EnPEiF7MbQW6ujXCw/3r5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899878; c=relaxed/simple; bh=URCnOS97CjnYCCCAFA4WMVqU8SoBUYBJkyKO4o/slyg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ubx8BjXOP+pTtrKR/iKCK38YBs51e2fsLGrCh8S2FOXlLo9S/Z+3U1RD/A4nC5nfFVfx72Jq2RvS00I9e+3UvSsgHpYGTtW3caktISqMf+wROm9K+oMPswFglELGUecTOYymr1LnbsuMNU+cLdoyXxmYmiuYKftFsedDi1CUkKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7600522EE; Fri, 18 Jul 2025 21:37:49 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 632693F66E; Fri, 18 Jul 2025 21:37:55 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 3/8] arm64: uaccess: Move existing GCS accessors definitions to gcs.h Date: Fri, 18 Jul 2025 23:37:35 -0500 Message-ID: <20250719043740.4548-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We are going to add some additional GCS access helpers to gcs.h in order to avoid some forward reference problems with uaccess. In preparation for that, lets move the existing gcssttr() and put_user_gcs() routines into gcs.h where it makes sense to keep all the accessors together. Further, the code which uses them already includes gcs.h and there is an existing CONFIG_ARM64_GCS check we can reuse. Signed-off-by: Jeremy Linton Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/gcs.h | 35 ++++++++++++++++++++++++++++ arch/arm64/include/asm/uaccess.h | 40 -------------------------------- 2 files changed, 35 insertions(+), 40 deletions(-) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index 5bc432234d3a..e3b360c9dba4 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -81,6 +81,41 @@ static inline int gcs_check_locked(struct task_struct *t= ask, return 0; } =20 +static inline int gcssttr(unsigned long __user *addr, unsigned long val) +{ + register unsigned long __user *_addr __asm__ ("x0") =3D addr; + register unsigned long _val __asm__ ("x1") =3D val; + int err =3D 0; + + /* GCSSTTR x1, x0 */ + asm volatile( + "1: .inst 0xd91f1c01\n" + "2: \n" + _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) + : "+r" (err) + : "rZ" (_val), "r" (_addr) + : "memory"); + + return err; +} + +static inline void put_user_gcs(unsigned long val, unsigned long __user *a= ddr, + int *err) +{ + int ret; + + if (!access_ok((char __user *)addr, sizeof(u64))) { + *err =3D -EFAULT; + return; + } + + uaccess_ttbr0_enable(); + ret =3D gcssttr(addr, val); + if (ret !=3D 0) + *err =3D ret; + uaccess_ttbr0_disable(); +} + #else =20 static inline bool task_gcs_el0_enabled(struct task_struct *task) diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uacc= ess.h index 5b91803201ef..1aa4ecb73429 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -502,44 +502,4 @@ static inline size_t probe_subpage_writeable(const cha= r __user *uaddr, =20 #endif /* CONFIG_ARCH_HAS_SUBPAGE_FAULTS */ =20 -#ifdef CONFIG_ARM64_GCS - -static inline int gcssttr(unsigned long __user *addr, unsigned long val) -{ - register unsigned long __user *_addr __asm__ ("x0") =3D addr; - register unsigned long _val __asm__ ("x1") =3D val; - int err =3D 0; - - /* GCSSTTR x1, x0 */ - asm volatile( - "1: .inst 0xd91f1c01\n" - "2: \n" - _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) - : "+r" (err) - : "rZ" (_val), "r" (_addr) - : "memory"); - - return err; -} - -static inline void put_user_gcs(unsigned long val, unsigned long __user *a= ddr, - int *err) -{ - int ret; - - if (!access_ok((char __user *)addr, sizeof(u64))) { - *err =3D -EFAULT; - return; - } - - uaccess_ttbr0_enable(); - ret =3D gcssttr(addr, val); - if (ret !=3D 0) - *err =3D ret; - uaccess_ttbr0_disable(); -} - - -#endif /* CONFIG_ARM64_GCS */ - #endif /* __ASM_UACCESS_H */ --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E93F722128B; Sat, 19 Jul 2025 04:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899880; cv=none; b=CUKJGduyM9pLNXugoiEn7gWcNCbC9JYcT0ffSH+chbvuzCguMf8OA28WqXBjBaMY375RnZxMpe+kSj35lpndOi146/fgGzbJKK9b0s7dkAP/6If4PeJOGRWDSe3MYIdSWPdBBSDBKZyCS2NjeTZQ4YNBX7vHzdVVZTLCuB4dVF8= ARC-Message-Signature: i=1; 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Fri, 18 Jul 2025 21:37:57 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 4/8] arm64: uaccess: Add additional userspace GCS accessors Date: Fri, 18 Jul 2025 23:37:36 -0500 Message-ID: <20250719043740.4548-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Uprobes need more advanced read, push, and pop userspace GCS functionality. Implement those features using the existing gcsstr() and copy_from_user(). Its important to note that GCS pages can be read by normal instructions, but the hardware validates that pages used by GCS specific operations, have a GCS privilege set. We aren't validating this in load_user_gcs because it requires stabilizing the VMA over the read which may fault. Signed-off-by: Jeremy Linton Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/gcs.h | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index e3b360c9dba4..f2fc8173fee3 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -116,6 +116,45 @@ static inline void put_user_gcs(unsigned long val, uns= igned long __user *addr, uaccess_ttbr0_disable(); } =20 +/* + * Unlike put_user_gcs() above, the use of copy_from_user() may provide + * an opening for non GCS pages to be used to source data. Therefore this + * should only be used in contexts where that is acceptable. + */ +static inline u64 load_user_gcs(unsigned long __user *addr, int *err) +{ + unsigned long ret; + u64 load =3D 0; + + gcsb_dsync(); + ret =3D copy_from_user(&load, addr, sizeof(load)); + if (ret !=3D 0) + *err =3D ret; + return load; +} + +static inline void push_user_gcs(unsigned long val, int *err) +{ + u64 gcspr =3D read_sysreg_s(SYS_GCSPR_EL0); + + gcspr -=3D sizeof(u64); + put_user_gcs(val, (unsigned long __user *)gcspr, err); + if (!*err) + write_sysreg_s(gcspr, SYS_GCSPR_EL0); +} + +static inline u64 pop_user_gcs(int *err) +{ + u64 gcspr =3D read_sysreg_s(SYS_GCSPR_EL0); + u64 read_val; + + read_val =3D load_user_gcs((unsigned long __user *)gcspr, err); + if (!*err) + write_sysreg_s(gcspr + sizeof(u64), SYS_GCSPR_EL0); + + return read_val; +} + #else =20 static inline bool task_gcs_el0_enabled(struct task_struct *task) @@ -126,6 +165,10 @@ static inline bool task_gcs_el0_enabled(struct task_st= ruct *task) static inline void gcs_set_el0_mode(struct task_struct *task) { } static inline void gcs_free(struct task_struct *task) { } static inline void gcs_preserve_current_state(void) { } +static inline void put_user_gcs(unsigned long val, unsigned long __user *a= ddr, + int *err) { } +static inline void push_user_gcs(unsigned long val, int *err) { } + static inline unsigned long gcs_alloc_thread_stack(struct task_struct *tsk, const struct kernel_clone_args *args) { @@ -136,6 +179,15 @@ static inline int gcs_check_locked(struct task_struct = *task, { return 0; } +static inline u64 load_user_gcs(unsigned long __user *addr, int *err) +{ + *err =3D -EFAULT; + return 0; +} +static inline u64 pop_user_gcs(int *err) +{ + return 0; +} =20 #endif =20 --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AA04C2236F2; Sat, 19 Jul 2025 04:38:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899882; cv=none; b=cRLyDlVoYtzBl8YLaLoCv7zCwsgBCTPnWuD/2DFdskqiXwGewpdiBX9sxp90m+1YHxqQIR9Q5PezS/52zSN+KgSHCBMSykw6N6r6hofbfBgISAWGOhLsf8Xo02dDPiCPIBhb6tl9dOIir6P7aWeAJJ169GBI/xv566O1xOf3zYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899882; c=relaxed/simple; bh=BXNQjR8ZVx9QHf4N0+b39YD6ruoQMQRnBRAwJ4rpC9I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M8onZdm58zv7wcVkwIXk1Txoyyo2OjEpUtlYTrT20dMVE7ObH1XhuuOIPmNhsGRVvEuqvkqGzdIee/op1zAomeRcRdpYZNunR2+GBMxP8S0ZCXMrwoqaNzzeEc4VYlx/6e75Yrqqljfhz1QQLWN1qYoVIL652m7tcaej6lTX7+o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D8292444; Fri, 18 Jul 2025 21:37:53 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EAD763F66E; Fri, 18 Jul 2025 21:37:58 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 5/8] arm64: probes: Add GCS support to bl/blr/ret Date: Fri, 18 Jul 2025 23:37:37 -0500 Message-ID: <20250719043740.4548-6-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The arm64 probe simulation doesn't currently have logic in place to deal with GCS and this results in core dumps if probes are inserted at control flow locations. Fix-up bl, blr and ret to manipulate the shadow stack as needed. While we manipulate and validate the shadow stack correctly, the hardware provides additional security by only allowing GCS operations against pages which are marked to support GCS. For writing there is gcssttr() which enforces this, but there isn't an equivalent for reading. This means that uprobe users should be aware that probing on control flow instructions which require reading the shadow stack (ex: ret) offers lower security guarantees than what is achieved without the uprobe active. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/probes/simulate-insn.c | 35 ++++++++++++++++++++---- 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kernel/probes/simulate-insn.c b/arch/arm64/kernel/p= robes/simulate-insn.c index 09a0b36122d0..c75dce7bbe13 100644 --- a/arch/arm64/kernel/probes/simulate-insn.c +++ b/arch/arm64/kernel/probes/simulate-insn.c @@ -13,6 +13,7 @@ #include =20 #include "simulate-insn.h" +#include "asm/gcs.h" =20 #define bbl_displacement(insn) \ sign_extend32(((insn) & 0x3ffffff) << 2, 27) @@ -49,6 +50,20 @@ static inline u32 get_w_reg(struct pt_regs *regs, int re= g) return lower_32_bits(pt_regs_read_reg(regs, reg)); } =20 +static inline void update_lr(struct pt_regs *regs, long addr) +{ + int err =3D 0; + + if (user_mode(regs) && task_gcs_el0_enabled(current)) { + push_user_gcs(addr + 4, &err); + if (err) { + force_sig(SIGSEGV); + return; + } + } + procedure_link_pointer_set(regs, addr + 4); +} + static bool __kprobes check_cbz(u32 opcode, struct pt_regs *regs) { int xn =3D opcode & 0x1f; @@ -107,9 +122,8 @@ simulate_b_bl(u32 opcode, long addr, struct pt_regs *re= gs) { int disp =3D bbl_displacement(opcode); =20 - /* Link register is x30 */ if (opcode & (1 << 31)) - set_x_reg(regs, 30, addr + 4); + update_lr(regs, addr); =20 instruction_pointer_set(regs, addr + disp); } @@ -133,17 +147,26 @@ simulate_br_blr(u32 opcode, long addr, struct pt_regs= *regs) /* update pc first in case we're doing a "blr lr" */ instruction_pointer_set(regs, get_x_reg(regs, xn)); =20 - /* Link register is x30 */ if (((opcode >> 21) & 0x3) =3D=3D 1) - set_x_reg(regs, 30, addr + 4); + update_lr(regs, addr); } =20 void __kprobes simulate_ret(u32 opcode, long addr, struct pt_regs *regs) { - int xn =3D (opcode >> 5) & 0x1f; + u64 ret_addr; + int err =3D 0; + unsigned long lr =3D procedure_link_pointer(regs); =20 - instruction_pointer_set(regs, get_x_reg(regs, xn)); + if (user_mode(regs) && task_gcs_el0_enabled(current)) { + ret_addr =3D pop_user_gcs(&err); + if (err || ret_addr !=3D lr) { + force_sig(SIGSEGV); + return; + } + } + + instruction_pointer_set(regs, lr); } =20 void __kprobes --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0B456225416; Sat, 19 Jul 2025 04:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899883; cv=none; b=ItRPXdziN7brf5WN7N393bFG9UtQvkJPi3IOgiHEgwI+b2+BRkRrQFrADnxfRICEDln4hQpslwTYolM2/dmqMvGiznZEdrDVBv1vs2QuVSyvpNFOGipahvLOZbjoLq8wtj8/Zi4d3ajBcSXtCF6vvpmq3F8xhLIqH3WRrK/ulaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899883; c=relaxed/simple; bh=VTYNHl3TYRpGap5CUq4f/rggtDb+4sh9tqphO6FsH1Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d1gpF5yOenPLLrNbsL7DluqMkQBwonaWPJfGOo0UWRZdqjtQFrd0KEAPRqIREMc8qL+k51Y6WDkkAaydujaWYdRqdyEfF9X3Atri2zRqV7KbHFQOg1rXjNJ/AF8ZcWG0eDEKyRLpwF/rwIivYTqaqOi25vVAbW1WxgnsdEUFpoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CBB9D244B; Fri, 18 Jul 2025 21:37:54 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AA7463F66E; Fri, 18 Jul 2025 21:38:00 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton , Steve Capper Subject: [PATCH v4 6/8] arm64: uprobes: Add GCS support to uretprobes Date: Fri, 18 Jul 2025 23:37:38 -0500 Message-ID: <20250719043740.4548-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ret probes work by changing the value in the link register at the probe location to return to the probe rather than the calling routine. Thus the GCS needs to be updated with this address as well. Since its possible to insert probes at locations where the current value of the LR doesn't match the GCS state this needs to be detected and handled in order to maintain the existing no-fault behavior. Co-developed-by: Steve Capper Signed-off-by: Steve Capper (updated to use new gcs accessors, and handle LR/GCS mismatches) Signed-off-by: Jeremy Linton Reviewed-by: Catalin Marinas --- arch/arm64/kernel/probes/uprobes.c | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/kernel/probes/uprobes.c b/arch/arm64/kernel/probes/= uprobes.c index cb3d05af36e3..b7b0c25eff50 100644 --- a/arch/arm64/kernel/probes/uprobes.c +++ b/arch/arm64/kernel/probes/uprobes.c @@ -6,6 +6,7 @@ #include #include #include +#include =20 #include "decode-insn.h" =20 @@ -159,11 +160,41 @@ arch_uretprobe_hijack_return_addr(unsigned long tramp= oline_vaddr, struct pt_regs *regs) { unsigned long orig_ret_vaddr; + unsigned long gcs_ret_vaddr; + int err =3D 0; + u64 gcspr; =20 orig_ret_vaddr =3D procedure_link_pointer(regs); + + if (task_gcs_el0_enabled(current)) { + gcspr =3D read_sysreg_s(SYS_GCSPR_EL0); + gcs_ret_vaddr =3D load_user_gcs((unsigned long __user *)gcspr, &err); + if (err) { + force_sig(SIGSEGV); + goto out; + } + /* + * If the LR and GCS entry don't match, then some kind of PAC/control + * flow happened. Likely because the user is attempting to retprobe + * on something that isn't a function boundary or inside a leaf + * function. Explicitly abort this retprobe because it will generate + * a GCS exception. + */ + if (gcs_ret_vaddr !=3D orig_ret_vaddr) { + orig_ret_vaddr =3D -1; + goto out; + } + put_user_gcs(trampoline_vaddr, (unsigned long __user *) gcspr, &err); + if (err) { + force_sig(SIGSEGV); + goto out; + } + } + /* Replace the return addr with trampoline addr */ procedure_link_pointer_set(regs, trampoline_vaddr); =20 +out: return orig_ret_vaddr; } =20 --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3BA3322CBE9; Sat, 19 Jul 2025 04:38:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899885; cv=none; b=MRwOK22Wsk0ZG5jRLV1sxCi6Tnrdvg82J/Hj1JVX6iLvYr2+wHegQ153t9ZUwKyYYChB9TT+0Gg12kN397zBPQmucX7x5EEPd1xiS0drnnnAOxui0zTJxaI+QhZ3cmNZPc8y9OIKWR54XFrvSBvAde2ShFcAj9qKJaHinuS0aqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899885; c=relaxed/simple; bh=c4P5cqyGsprUwS02iRfL9eWWuWV2qeAJREBDUiqWBtE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qoCsV083CDcOLs0EdtojvjD7RNwdnz2Z1u3lLzuW74Si7gRof6g0dTmMt13pUYyR10hAFjWJ21s4ZFEM/qpZIFNaVqNKDpoNstPCJTO+fgsGYCwVmNZvd+LCMymJMAhC/uSNCqbMU8c6EcRxa+4Dg0blfIGuRDlerZh9365srCs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88B632E91; Fri, 18 Jul 2025 21:37:56 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 699423F66E; Fri, 18 Jul 2025 21:38:02 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 7/8] arm64: Kconfig: Remove GCS restrictions on UPROBES Date: Fri, 18 Jul 2025 23:37:39 -0500 Message-ID: <20250719043740.4548-8-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the uprobe paths have been made GCS compatible drop the Kconfig restriction. Signed-off-by: Jeremy Linton Acked-by: Catalin Marinas --- arch/arm64/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 393d71124f5d..6e609caf1d18 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2224,7 +2224,6 @@ config ARM64_GCS default y select ARCH_HAS_USER_SHADOW_STACK select ARCH_USES_HIGH_VMA_FLAGS - depends on !UPROBES help Guarded Control Stack (GCS) provides support for a separate stack with restricted access which contains only return --=20 2.50.1 From nobody Mon Oct 6 15:13:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CCDE2225419; Sat, 19 Jul 2025 04:38:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899887; cv=none; b=SQlBTPE24OhghfiFApCMDsOekW/aC4WPiB3hPapaiccDfoV28h3UohuA+t8hC0aydEhLSXgTpuwVi9/SyYQfDPgvg5qoliMlJSIiGU6d4/j7O3WhCx7Fg03z4HxTR/c2bmhOrmJ8lRtsbmFUM/qo7MGsQZhxcwGcpfV8Ndp6twg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752899887; c=relaxed/simple; bh=s+4CXnyWKnGe+lq9lzRVTLvQSangoa8NJGuxh9g3sTs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C/H5ApGXwrhRbMHeuuDCG4qEH1NwHZjWDrXeFJP/ZK7azpsG6aiCh1TiNY0FhQrbvgpdE7HyXlDuPxS5j5FUgGm8+h5jouXv3hCOHsnn8q9H9ckxHL6YJA/Bc1FvH9Wonr9ED7TTHCD6JwNTFrXYMu290rVqeIVzLgrMIk19ZlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 425742E96; Fri, 18 Jul 2025 21:37:58 -0700 (PDT) Received: from u200865.usa.arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 298483F66E; Fri, 18 Jul 2025 21:38:04 -0700 (PDT) From: Jeremy Linton To: linux-trace-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org, mhiramat@kernel.org, oleg@redhat.com, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, thiago.bauermann@linaro.org, broonie@kernel.org, yury.khrustalev@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v4 8/8] uprobes: uprobe_warn should use passed task Date: Fri, 18 Jul 2025 23:37:40 -0500 Message-ID: <20250719043740.4548-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250719043740.4548-1-jeremy.linton@arm.com> References: <20250719043740.4548-1-jeremy.linton@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" uprobe_warn() is passed a task structure, yet its using current. For the most part this shouldn't matter, but since a task structure is provided, lets use it. Signed-off-by: Jeremy Linton Acked-by: Masami Hiramatsu (Google) Acked-by: Oleg Nesterov --- kernel/events/uprobes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index 4c965ba77f9f..2dc4fed837a2 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -121,7 +121,7 @@ struct xol_area { =20 static void uprobe_warn(struct task_struct *t, const char *msg) { - pr_warn("uprobe: %s:%d failed to %s\n", current->comm, current->pid, msg); + pr_warn("uprobe: %s:%d failed to %s\n", t->comm, t->pid, msg); } =20 /* --=20 2.50.1