From nobody Mon Oct 6 17:06:27 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23EEF230274 for ; Sat, 19 Jul 2025 03:06:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752894361; cv=none; b=pnoKvbV4Iwg5E8G6RXsTlk7rGZeh2jhouBe07mmPsJUIl6ZfvKGMhekkRlHnnTXUWQTyDEHFsro5meXNEtfyYL2e2faR81O1XUQtx8y1K1i1V6/dQVTK7L+nkxHfZVqc2qdeTaGkSieGLdZnV7sNIggo32m9GkhNgZQ7t1G8jGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752894361; c=relaxed/simple; bh=gnUVsnOcV/XtpgO/L2imjrh4swAc/StdCtllv4r2d8E=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Content-Type; b=Dqxkfy2/FP4MAjkdi8XY4qIL+lupAC6qlM0a2VeH+B1TLyCMkG1VkhrQ8WGQjkCoKrolF5b7Isxd0ygfvA24W6bx9UyiM9kBtBPO933xhYKRq3e0PnKXojAL3g/GoaOPWCrgnnYeQgPjEea89KP3sr+vxZBZ6iAdC7WnppibX9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=NSqgKl1m; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="NSqgKl1m" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-74b4d2f67d5so2387788b3a.3 for ; Fri, 18 Jul 2025 20:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1752894359; x=1753499159; darn=vger.kernel.org; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=nmgRc//yvu8C/2TPTG7gdgWNTTZ5mY9hqNAERparZN8=; b=NSqgKl1mGVNlT2kIuAiTy9OhB3bZq7Sqct8Vnqoq4uiablBFgW99WdrO0deCOcLuLq KML1HC6TGohOSoFfi7hxPmEP+2O4nPMmlxzmQTa0fjLDlSwTtHMmNsWokViK9QQsEjI8 wAXICrEKo1DxL4qbyhTpSgnkcZokeZTzb1wMyX24DANkycRDV9ag9LVVJjXDMTRmhVQl QNnmNHefHFfAv7umNFGkrUcIifUMaGirQ0wh0K8uo9jaGDhweNXmj8GrqpAmBRBWRq2Q D6URjIzFws2fPUROIcSJuxgL9nNeb8LS87yIN3EXXLyJlJpanZYWEwnqpy6/XbILaKgE YuDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752894359; x=1753499159; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=nmgRc//yvu8C/2TPTG7gdgWNTTZ5mY9hqNAERparZN8=; b=CycSwIsyqydidfGcjfZm3xD/Oim0HanPfDzH77ALDlDJZgsxRrhBOK+HGJ6mKHmKho JUGvsBTWjdwEtZupM43gBL0H/2CVHRrG1a61UrgcB/YJOFD6KczytVRQBfNVClpTOJYa IRcNPUli2i66s9f6qKvOdRJAPxGA0DGJSfpfzghf5qdqRyDkyM7k2+5tfX/kKcngJTRc pIprq+3YBDTxl+U+KJ5Ys6XtfvgeHEe8PhJJoyUoTYSNdVazAECUwYWnHvXbDLHmG5WD gUvW3UtmhfIfcdOt9PLiWF8IDwgQ9zz3u2rs1oUfrjRzQslIh6ksAqqmRNm3yCvRtQ27 zaFA== X-Forwarded-Encrypted: i=1; AJvYcCVrJ92JImxP6arINpbqEObjiy0chFMgSjwm9DD03K/2Qmfbv8HYuubJPyI707Xb5CdVcppupcOH4pXrVlQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzAiIB/s2dOzXpwmbN9RFVOkoy3EGO7ZLLFV0+inCUgy8m5cV2X UVmzgZ+hcsTVeGFMzwd19ibyEoo4KOcQruR403HHWTBHPT/l9hmN1fai/MVSFapL4Yu9p+gVf1/ VH5ODpW7d1Q== X-Google-Smtp-Source: AGHT+IG4YDUB4lx+V+i8TajjW6vMqT0pjd6tqiud9nGrVufXkeQRNx06qqxAraYwENxoI7aztNJ+KmaqZCxN X-Received: from pfbdh2.prod.google.com ([2002:a05:6a00:4782:b0:746:fd4c:1fcf]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:3e23:b0:748:e150:ac5c with SMTP id d2e1a72fcca58-759ae1e7120mr7877546b3a.23.1752894359467; Fri, 18 Jul 2025 20:05:59 -0700 (PDT) Date: Fri, 18 Jul 2025 20:05:16 -0700 In-Reply-To: <20250719030517.1990983-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250719030517.1990983-1-irogers@google.com> X-Mailer: git-send-email 2.50.0.727.gbf7dc18ff4-goog Message-ID: <20250719030517.1990983-15-irogers@google.com> Subject: [PATCH v3 14/15] perf parse-events: Fix missing slots for Intel topdown metric events From: Ian Rogers To: Thomas Falcon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Ravi Bangoria , James Clark , Dapeng Mi , Weilin Wang , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Topdown metric events require grouping with a slots event. In perf metrics this is currently achieved by metrics adding an unnecessary "0 * tma_info_thread_slots". New TMA metrics trigger optimizations of the metric expression that removes the event and breaks the metric due to the missing but required event. Add a pass immediately before sorting and fixing parsed events, that insert a slots event if one is missing. Update test expectations to match this. Signed-off-by: Ian Rogers --- tools/perf/arch/x86/util/evlist.c | 24 ++++++++++++++++++++++++ tools/perf/arch/x86/util/topdown.c | 28 ++++++++++++++++++++++++++++ tools/perf/arch/x86/util/topdown.h | 2 ++ tools/perf/tests/parse-events.c | 24 ++++++++++++------------ tools/perf/util/evlist.h | 1 + tools/perf/util/parse-events.c | 10 ++++++++++ 6 files changed, 77 insertions(+), 12 deletions(-) diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/e= vlist.c index 1969758cc8c1..75e9d00a1494 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -81,3 +81,27 @@ int arch_evlist__cmp(const struct evsel *lhs, const stru= ct evsel *rhs) /* Default ordering by insertion index. */ return lhs->core.idx - rhs->core.idx; } + +int arch_evlist__add_required_events(struct list_head *list) +{ + struct evsel *pos, *metric_event =3D NULL; + int idx =3D 0; + + if (!topdown_sys_has_perf_metrics()) + return 0; + + list_for_each_entry(pos, list, core.node) { + if (arch_is_topdown_slots(pos)) { + /* Slots event already present, nothing to do. */ + return 0; + } + if (metric_event =3D=3D NULL && arch_is_topdown_metrics(pos)) + metric_event =3D pos; + idx++; + } + if (metric_event =3D=3D NULL) { + /* No topdown metric events, nothing to do. */ + return 0; + } + return topdown_insert_slots_event(list, idx + 1, metric_event); +} diff --git a/tools/perf/arch/x86/util/topdown.c b/tools/perf/arch/x86/util/= topdown.c index 66b231fbf52e..0d01b662627a 100644 --- a/tools/perf/arch/x86/util/topdown.c +++ b/tools/perf/arch/x86/util/topdown.c @@ -77,3 +77,31 @@ bool arch_topdown_sample_read(struct evsel *leader) =20 return false; } + +/* + * Make a copy of the topdown metric event metric_event with the given ind= ex but + * change its configuration to be a topdown slots event. Copying from + * metric_event ensures modifiers are the same. + */ +int topdown_insert_slots_event(struct list_head *list, int idx, struct evs= el *metric_event) +{ + struct evsel *evsel =3D evsel__new_idx(&metric_event->core.attr, idx); + + if (!evsel) + return -ENOMEM; + + evsel->core.attr.config =3D TOPDOWN_SLOTS; + evsel->core.cpus =3D perf_cpu_map__get(metric_event->core.cpus); + evsel->core.pmu_cpus =3D perf_cpu_map__get(metric_event->core.pmu_cpus); + evsel->core.is_pmu_core =3D true; + evsel->pmu =3D metric_event->pmu; + evsel->name =3D strdup("slots"); + evsel->precise_max =3D metric_event->precise_max; + evsel->sample_read =3D metric_event->sample_read; + evsel->weak_group =3D metric_event->weak_group; + evsel->bpf_counter =3D metric_event->bpf_counter; + evsel->retire_lat =3D metric_event->retire_lat; + evsel__set_leader(evsel, evsel__leader(metric_event)); + list_add_tail(&evsel->core.node, list); + return 0; +} diff --git a/tools/perf/arch/x86/util/topdown.h b/tools/perf/arch/x86/util/= topdown.h index 2349536cf882..69035565e649 100644 --- a/tools/perf/arch/x86/util/topdown.h +++ b/tools/perf/arch/x86/util/topdown.h @@ -5,9 +5,11 @@ #include =20 struct evsel; +struct list_head; =20 bool topdown_sys_has_perf_metrics(void); bool arch_is_topdown_slots(const struct evsel *evsel); bool arch_is_topdown_metrics(const struct evsel *evsel); +int topdown_insert_slots_event(struct list_head *list, int idx, struct evs= el *metric_event); =20 #endif diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 5ec2e5607987..bb8004397650 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -719,20 +719,20 @@ static int test__checkevent_pmu_partial_time_callgrap= h(struct evlist *evlist) =20 static int test__checkevent_pmu_events(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type = || - strcmp(evsel->pmu->name, "cpu")); - TEST_ASSERT_VAL("wrong exclude_user", - !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", - evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); - TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); - TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); + TEST_ASSERT_VAL("wrong number of entries", 1 <=3D evlist->core.nr_entries= ); =20 + evlist__for_each_entry(evlist, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= || + strcmp(evsel->pmu->name, "cpu")); + TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); + TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); + } return TEST_OK; } =20 diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index fac1a01ba13f..1472d2179be1 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -111,6 +111,7 @@ void evlist__add(struct evlist *evlist, struct evsel *e= ntry); void evlist__remove(struct evlist *evlist, struct evsel *evsel); =20 int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs); +int arch_evlist__add_required_events(struct list_head *list); =20 int evlist__add_dummy(struct evlist *evlist); struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wid= e); diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index fe2073c6b549..01fa8c80998b 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2190,6 +2190,11 @@ static int evlist__cmp(void *_fg_idx, const struct l= ist_head *l, const struct li return arch_evlist__cmp(lhs, rhs); } =20 +int __weak arch_evlist__add_required_events(struct list_head *list __alway= s_unused) +{ + return 0; +} + static int parse_events__sort_events_and_fix_groups(struct list_head *list) { int idx =3D 0, force_grouped_idx =3D -1; @@ -2201,6 +2206,11 @@ static int parse_events__sort_events_and_fix_groups(= struct list_head *list) struct evsel *force_grouped_leader =3D NULL; bool last_event_was_forced_leader =3D false; =20 + /* On x86 topdown metrics events require a slots event. */ + ret =3D arch_evlist__add_required_events(list); + if (ret) + return ret; + /* * Compute index to insert ungrouped events at. Place them where the * first ungrouped event appears. --=20 2.50.0.727.gbf7dc18ff4-goog