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Fri, 18 Jul 2025 16:48:25 -0700 From: Nicolin Chen To: , CC: , , , , , Subject: [PATCH 1/2] iommu/arm-smmu-v3: Do not bother impl_ops if IOMMU_VIOMMU_TYPE_ARM_SMMUV3 Date: Fri, 18 Jul 2025 16:48:21 -0700 Message-ID: <20250718234822.1734190-2-nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250718234822.1734190-1-nicolinc@nvidia.com> References: <20250718234822.1734190-1-nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|IA0PR12MB8976:EE_ X-MS-Office365-Filtering-Correlation-Id: 7444ad89-fd1e-43bc-500e-08ddc6559b42 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?g+dYLeQFoTpig64x91IP+4u0QSWmtDGScu1iu2NHqn63FeSNfDTZzM5Dw69N?= =?us-ascii?Q?F2Rryape86u0akWDi9Al77M49eWQBSNRsSkGh7MvapoLJQK5f1589N5oVcIB?= =?us-ascii?Q?CyOeXZ6XDOrjgTsCSNQRFQESVx75m9Q3IH0j5A4SlL1WVY7qj4c4ojrEIXbV?= =?us-ascii?Q?4P8Tx6cAv+3fQKSPwoQWx//9xNrBjyPNonhmGK/BLA3BUC0cCLUxu9FPP6Jy?= =?us-ascii?Q?n5DCoI61mbeRlqx3R21jGeCoanqrP2K7gF8Kod/QpgsheOagnTMUGUrLxJHM?= =?us-ascii?Q?u6Vzr3hryXyLswTY2poWxR5+CUmAMZ5mO4H9KpaKsPLvazAWbMjS9Gq0CARx?= =?us-ascii?Q?q2V1rxZVBF/e8LWlPZEZrrtKG+72dU4PNtIjcHSzhFvN1p9Kvq6fsGW7Rk+Q?= =?us-ascii?Q?P1EOmt+CYtSKBJuYoBJWgwxPqAhxX9OnezZ1iMqxpcWyl6uGebjJBvRkKQqJ?= =?us-ascii?Q?AdgrJKx3+rn0m8TPKxakGMaHX/8oFryaSFnTqj7xgNZcQiv4Itm8FJXQE8uc?= =?us-ascii?Q?CzW9rQi0fvxEFu9aJPWklHO0j7jlH2nzWrwPW8xe6fXC59udkQcbVwEi7MAd?= =?us-ascii?Q?3diKBBhEekQTEdLo8NjgJgyUhaRyI75RHL+4LB8x0U3UNq2NuJ+cMa7zXQLX?= =?us-ascii?Q?yGRVbGFTCcYZCXFWr+HIoLZ5ZsYbplU9R4D6QWqDA7yR0tIu6OauTFGAZntq?= =?us-ascii?Q?GjmGe6NWqQJsTmxlUVliSJkBd5pciSBichqVzmoWHEfnficnpybR1VM/5tRb?= =?us-ascii?Q?DYuea5Mrtmc5gLsgyP64Su+jIXkioaDuy5Q/fm98+nF4/ZT2BnHcOk6+94UB?= =?us-ascii?Q?S4iVmqljkELw+idb9oeSZCT7zo3BBAmEpNU92Nh+S7Cg1u+a0GbjJvwK2gKN?= =?us-ascii?Q?/OzIj/KUVZtm2toXPQGtOmm9kDIugG3bIKmYwCCos6X8YYdOQHOQv0hj06ZU?= =?us-ascii?Q?vdFibGlUv8Lve8m8SdWuveV3byz1jYAti95PzU50vvRenfUKJLTQnPRRWSGg?= =?us-ascii?Q?SRzHC8tno/eyNExCbeZGCwsmgdbz1nY1hukoeIClINFFh2q0U9/oQ3a9vdpK?= =?us-ascii?Q?sDliiE/e9fMIrVdNO9UTpiwUQE+31/c5dOevN7GyzOWkkYGDXzGCo0YisDgj?= =?us-ascii?Q?KGSv3lkt2KpsL9XDK0ALoQvIk8qjmHYG+KME0ajZ2yvBT+WBrrPSf7f2bDDj?= =?us-ascii?Q?5kLwEtvsmL7mgMLihy6L1CNG6X8DYweA5HhggmhdjTtHHYBF7jC3oFKJPxGs?= =?us-ascii?Q?0eY/NPYBzeo955TV7nfDZKIAsb4Fgpq+Xjs6K73CPDmf982LJRNEqLI3qdEO?= =?us-ascii?Q?GEWM3PQsyAVv/G1SYrSIQ+RaXrNpxUEshCLT3yDMhyJzlxNGI8ZPVlSC8feh?= =?us-ascii?Q?cU/u+A6HzMRtUNBqGzcFRy7XXYY7IjYTpCxmEGzSjJXI0qvMwVMqf0vDG771?= =?us-ascii?Q?8hmpNWdkK05dRdDeE36VXtIOPWrn7cUYpyPCH+3uAl05kSf2N6nqjb9Uz9R4?= =?us-ascii?Q?JMaxRgOAirpK0fMMmQbyJgexQDpqb0i24CcH?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 23:48:33.4190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7444ad89-fd1e-43bc-500e-08ddc6559b42 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8976 Content-Type: text/plain; charset="utf-8" When viommu type is IOMMU_VIOMMU_TYPE_ARM_SMMUV3, always return or init the standard struct arm_vsmmu, instead of going through impl_ops that must have its own viommu type than the standard IOMMU_VIOMMU_TYPE_ARM_SMMUV3. Given that arm_vsmmu_init() is called after arm_smmu_get_viommu_size(), any unsupported viommu->type must be a corruption. And missing a pairing impl's vsmmu_init should be a driver bug too. Warn these two cases. Suggested-by: Will Deacon Signed-off-by: Nicolin Chen --- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 30 ++++++++++++------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index d9bea8f1f636..0b2acb80f41b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -420,14 +420,13 @@ size_t arm_smmu_get_viommu_size(struct device *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return 0; =20 - if (smmu->impl_ops && smmu->impl_ops->vsmmu_size && - viommu_type =3D=3D smmu->impl_ops->vsmmu_type) - return smmu->impl_ops->vsmmu_size; + if (viommu_type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); =20 - if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + if (!smmu->impl_ops || !smmu->impl_ops->vsmmu_size || + viommu_type !=3D smmu->impl_ops->vsmmu_type) return 0; - - return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); + return smmu->impl_ops->vsmmu_size; } =20 int arm_vsmmu_init(struct iommufd_viommu *viommu, @@ -447,12 +446,21 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, /* FIXME Move VMID allocation from the S2 domain allocation to here */ vsmmu->vmid =3D s2_parent->s2_cfg.vmid; =20 - if (smmu->impl_ops && smmu->impl_ops->vsmmu_init && - viommu->type =3D=3D smmu->impl_ops->vsmmu_type) - return smmu->impl_ops->vsmmu_init(vsmmu, user_data); + if (viommu->type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) { + viommu->ops =3D &arm_vsmmu_ops; + return 0; + } =20 - viommu->ops =3D &arm_vsmmu_ops; - return 0; + /* + * If a non standard type was supported in arm_smmu_get_viommu_size() by + * an implementation, a pairing vsmmu_init op must exist. + */ + if (WARN_ON_ONCE(!smmu->impl_ops || !smmu->impl_ops->vsmmu_init)) + return -EOPNOTSUPP; + /* Unsupported type was rejected in arm_smmu_get_viommu_size() */ + if (WARN_ON(viommu->type !=3D smmu->impl_ops->vsmmu_type)) + return -EOPNOTSUPP; + return smmu->impl_ops->vsmmu_init(vsmmu, user_data); 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Fri, 18 Jul 2025 16:48:25 -0700 From: Nicolin Chen To: , CC: , , , , , Subject: [PATCH 2/2] iommu/arm-smmu-v3: Replace vsmmu_size/type with get_viommu_size Date: Fri, 18 Jul 2025 16:48:22 -0700 Message-ID: <20250718234822.1734190-3-nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250718234822.1734190-1-nicolinc@nvidia.com> References: <20250718234822.1734190-1-nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F67:EE_|MW3PR12MB4364:EE_ X-MS-Office365-Filtering-Correlation-Id: 8272b248-1d2c-42db-6364-08ddc6559ca1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DORCNXWjkBvoksLp4lgHeX688CPM29yzorzIX0YllpM4x8DoTOboTN3BLlh1?= =?us-ascii?Q?0hn6kn+aIRN7zuVxFFfbbKXer2gobfeyGXp8AOeZjUyyAE3Z7pSpOXghxj1V?= =?us-ascii?Q?gQTE0ntfBxwbFBUskrjaBVfhn1BbncsyIN58V2VID5D0sDNV9vMKj7x+0gy3?= =?us-ascii?Q?Tqev2ytySGzad6EuiFH/okjuG6/Yy/nBqAuOPwKTRRbo0PUJZGejSmMh7srr?= =?us-ascii?Q?sbC4o4YH9lCuKcjJc8F6H6Weu8vWoRl03umRIlEWmslR70aHsh4Y8uWJ/Un7?= =?us-ascii?Q?qJJoFLfOWgEXWAS2QnTy+XrC6tKJ0miUby/rt6s2vPMMrOK1nIpPv6H/Y5rc?= =?us-ascii?Q?fqVKb4xx5xWQYltwMGIISFPks+BQWrUN/TZlcwYUco0CHDLD0Vts/3rKaPDc?= =?us-ascii?Q?PzyKCTvLbjQe6+331ma/0AqbQWJJBNNEO3wmEC2hCZIuhwMORgfFYFJX+Pnk?= =?us-ascii?Q?Rt+NJhLRuRHiJh4A4fVOvg2+7hntYKfcdoskyDbHxoztDhW42GHzR0Wn1t5+?= =?us-ascii?Q?7RtTfq+hI+BBix9lbZneKTITWiFumc+YD4QrU9PrsD+mk6TlC798a3LX5Fmj?= =?us-ascii?Q?L/jHyybx36wRe2zoK3s+U9ltkEZQvjBFKVQmD2UmkjfWdMlr+MRn4she3723?= =?us-ascii?Q?9Zc+gqpdeWKTUKBXmAT/tFjWfziZbKDbLN3H41iyglXLE0uVyOP4tHRgpa8g?= =?us-ascii?Q?c/h+ArO+ESLUudP+i5ZqLcrxv8NFd+qotn/AgR79tjNgLUTjRl+A2oUdUtzn?= =?us-ascii?Q?gaE7+4x6z9DKozW/F5AfoUGf+SEXHon207lLQa/WFl5anFqjbyV5hRtQLNJ+?= =?us-ascii?Q?dDcXFFervAhqN3wM/+5ghpAShT7HTljJ9rbchnA8Y2yetMk0XJcv6SzLbpJM?= =?us-ascii?Q?K+M2s620RODcE9e++PYSAHJ3G0AeAv26mGuZq6x0Hz2pzXiJb4uk8TAUlmg+?= =?us-ascii?Q?d36qUUyLGP2pVQZCICdcR29ZTECtX3Bun7R1DTv+TEeGmF3fVJgqP3GrlQv3?= =?us-ascii?Q?QMeEnte/Y/P6hp0+exLMp+ktRxqWiRVtTh23n2DNvG3CCMfyYHJF+6Ean6an?= =?us-ascii?Q?zp10HPETO4zyBEu12JyQyd/dgNaglt6klp+f5TsixrM3Byh9HSEuzmawy4U4?= =?us-ascii?Q?FlJSLgTBkRtR7KChqa8fpbGl5D9pyMY+AToaT9uaSMSbcbCRjow/m2WIAMvY?= =?us-ascii?Q?GIxtPtt/8FHXhpVXZtbfcrUj4r/68XYpfV2K1WCPVUQnZBZ/KdqiJrQXMUx0?= =?us-ascii?Q?ySYwGEtXs6yGyHBHbstdycY8M9+u7JSSHQ1kGtzE50QcmuFc7Qyozu81CT/s?= =?us-ascii?Q?jSJ+7sgDwxYDKnuzfMYvF3N2bDK00Fgm5IKvHj8DGuE1UZI7Jop0yBc4wsoO?= =?us-ascii?Q?2YZFiC/75aO4F83f1rdH+NwGsEm8pvwsUQyccFRHZEVnQbNem1wYATO1nggc?= =?us-ascii?Q?DQQ4CcFOFLA1BXDKA8Gw4nAZ3biCTibv/yPJZdak2jECL+lpX1RjAAQY96ID?= =?us-ascii?Q?4nUwWqP2uk9p5gZY6mI0asUHgFF2EEO8EeMI?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 23:48:35.7488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8272b248-1d2c-42db-6364-08ddc6559ca1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4364 Content-Type: text/plain; charset="utf-8" It's more flexible to have a get_viommu_size op. Replace static vsmmu_size and vsmmu_type with that. Suggested-by: Will Deacon Signed-off-by: Nicolin Chen Acked-by: Will Deacon --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 8 ++------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +-- drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 14 ++++++++++++-- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 0b2acb80f41b..d4b7affaa480 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -423,10 +423,9 @@ size_t arm_smmu_get_viommu_size(struct device *dev, if (viommu_type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); =20 - if (!smmu->impl_ops || !smmu->impl_ops->vsmmu_size || - viommu_type !=3D smmu->impl_ops->vsmmu_type) + if (!smmu->impl_ops || !smmu->impl_ops->get_viommu_size) return 0; - return smmu->impl_ops->vsmmu_size; + return smmu->impl_ops->get_viommu_size(viommu_type); } =20 int arm_vsmmu_init(struct iommufd_viommu *viommu, @@ -457,9 +456,6 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, */ if (WARN_ON_ONCE(!smmu->impl_ops || !smmu->impl_ops->vsmmu_init)) return -EOPNOTSUPP; - /* Unsupported type was rejected in arm_smmu_get_viommu_size() */ - if (WARN_ON(viommu->type !=3D smmu->impl_ops->vsmmu_type)) - return -EOPNOTSUPP; return smmu->impl_ops->vsmmu_init(vsmmu, user_data); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 3fa02c51df9f..e332f5ba2f8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -728,8 +728,7 @@ struct arm_smmu_impl_ops { */ void *(*hw_info)(struct arm_smmu_device *smmu, u32 *length, enum iommu_hw_info_type *type); - const size_t vsmmu_size; - const enum iommu_viommu_type vsmmu_type; + size_t (*get_viommu_size)(enum iommu_viommu_type viommu_type); int (*vsmmu_init)(struct arm_vsmmu *vsmmu, const struct iommu_user_data *user_data); }; diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu= /arm/arm-smmu-v3/tegra241-cmdqv.c index 4c86eacd36b1..46005ed52bc2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -832,6 +832,13 @@ static void *tegra241_cmdqv_hw_info(struct arm_smmu_de= vice *smmu, u32 *length, return info; } =20 +static size_t tegra241_cmdqv_get_vintf_size(enum iommu_viommu_type viommu_= type) +{ + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV) + return 0; + return VIOMMU_STRUCT_SIZE(struct tegra241_vintf, vsmmu.core); +} + static struct arm_smmu_impl_ops tegra241_cmdqv_impl_ops =3D { /* For in-kernel use */ .get_secondary_cmdq =3D tegra241_cmdqv_get_cmdq, @@ -839,8 +846,7 @@ static struct arm_smmu_impl_ops tegra241_cmdqv_impl_ops= =3D { .device_remove =3D tegra241_cmdqv_remove, /* For user-space use */ .hw_info =3D tegra241_cmdqv_hw_info, - .vsmmu_size =3D VIOMMU_STRUCT_SIZE(struct tegra241_vintf, vsmmu.core), - .vsmmu_type =3D IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + .get_viommu_size =3D tegra241_cmdqv_get_vintf_size, .vsmmu_init =3D tegra241_cmdqv_init_vintf_user, }; =20 @@ -1273,6 +1279,10 @@ tegra241_cmdqv_init_vintf_user(struct arm_vsmmu *vsm= mu, phys_addr_t page0_base; int ret; =20 + /* Unsupported type was rejected in tegra241_cmdqv_get_vintf_size() */ + if (WARN_ON(vsmmu->core.type !=3D IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV)) + return -EOPNOTSUPP; + if (!user_data) return -EINVAL; =20 --=20 2.43.0