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Fri, 18 Jul 2025 04:51:41 -0700 From: Yonatan Maman To: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= , Andrew Morton , Jason Gunthorpe , Leon Romanovsky CC: Lyude Paul , Danilo Krummrich , "David Airlie" , Simona Vetter , Alistair Popple , Ben Skeggs , Michael Guralnik , Or Har-Toov , Daisuke Matsuda , Shay Drory , , , , , , "Yonatan Maman" , Gal Shalom Subject: [PATCH v2 1/5] mm/hmm: HMM API to enable P2P DMA for device private pages Date: Fri, 18 Jul 2025 14:51:08 +0300 Message-ID: <20250718115112.3881129-2-ymaman@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718115112.3881129-1-ymaman@nvidia.com> References: <20250718115112.3881129-1-ymaman@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000204:EE_|DS0PR12MB6487:EE_ X-MS-Office365-Filtering-Correlation-Id: 30e3c9f0-552e-4446-0144-08ddc5f1847a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:52:05.6428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30e3c9f0-552e-4446-0144-08ddc5f1847a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000204.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6487 Content-Type: text/plain; charset="utf-8" From: Yonatan Maman hmm_range_fault() by default triggered a page fault on device private when HMM_PFN_REQ_FAULT flag was set. pages, migrating them to RAM. In some cases, such as with RDMA devices, the migration overhead between the device (e.g., GPU) and the CPU, and vice-versa, significantly degrades performance. Thus, enabling Peer-to-Peer (P2P) DMA access for device private page might be crucial for minimizing data transfer overhead. Introduced an API to support P2P DMA for device private pages,includes: - Leveraging the struct pagemap_ops for P2P Page Callbacks. This callback involves mapping the page for P2P DMA and returning the corresponding PCI_P2P page. - Utilizing hmm_range_fault for initializing P2P DMA. The API also adds the HMM_PFN_REQ_TRY_P2P flag option for the hmm_range_fault caller to initialize P2P. If set, hmm_range_fault attempts initializing the P2P connection first, if the owner device supports P2P, using p2p_page. In case of failure or lack of support, hmm_range_fault will continue with the regular flow of migrating the page to RAM. This change does not affect previous use-cases of hmm_range_fault, because both the caller and the page owner must explicitly request and support it to initialize P2P connection. Signed-off-by: Yonatan Maman Signed-off-by: Gal Shalom --- include/linux/hmm.h | 2 ++ include/linux/memremap.h | 8 ++++++ mm/hmm.c | 57 +++++++++++++++++++++++++++++++--------- 3 files changed, 55 insertions(+), 12 deletions(-) diff --git a/include/linux/hmm.h b/include/linux/hmm.h index db75ffc949a7..988c98c0edcc 100644 --- a/include/linux/hmm.h +++ b/include/linux/hmm.h @@ -27,6 +27,7 @@ struct mmu_interval_notifier; * HMM_PFN_P2PDMA_BUS - Bus mapped P2P transfer * HMM_PFN_DMA_MAPPED - Flag preserved on input-to-output transformation * to mark that page is already DMA mapped + * HMM_PFN_ALLOW_P2P - Allow returning PCI P2PDMA page * * On input: * 0 - Return the current state of the page, do not fault = it. @@ -47,6 +48,7 @@ enum hmm_pfn_flags { HMM_PFN_DMA_MAPPED =3D 1UL << (BITS_PER_LONG - 4), HMM_PFN_P2PDMA =3D 1UL << (BITS_PER_LONG - 5), HMM_PFN_P2PDMA_BUS =3D 1UL << (BITS_PER_LONG - 6), + HMM_PFN_ALLOW_P2P =3D 1UL << (BITS_PER_LONG - 7), =20 HMM_PFN_ORDER_SHIFT =3D (BITS_PER_LONG - 11), =20 diff --git a/include/linux/memremap.h b/include/linux/memremap.h index 4aa151914eab..79becc37df00 100644 --- a/include/linux/memremap.h +++ b/include/linux/memremap.h @@ -89,6 +89,14 @@ struct dev_pagemap_ops { */ vm_fault_t (*migrate_to_ram)(struct vm_fault *vmf); =20 + /* + * Used for private (un-addressable) device memory only. Return a + * corresponding PFN for a page that can be mapped to device + * (e.g using dma_map_page) + */ + int (*get_dma_pfn_for_device)(struct page *private_page, + unsigned long *dma_pfn); + /* * Handle the memory failure happens on a range of pfns. Notify the * processes who are using these pfns, and try to recover the data on diff --git a/mm/hmm.c b/mm/hmm.c index feac86196a65..089e522b346b 100644 --- a/mm/hmm.c +++ b/mm/hmm.c @@ -232,6 +232,49 @@ static inline unsigned long pte_to_hmm_pfn_flags(struc= t hmm_range *range, return pte_write(pte) ? (HMM_PFN_VALID | HMM_PFN_WRITE) : HMM_PFN_VALID; } =20 +static bool hmm_handle_device_private(struct hmm_range *range, + unsigned long pfn_req_flags, + swp_entry_t entry, + unsigned long *hmm_pfn) +{ + struct page *page =3D pfn_swap_entry_to_page(entry); + struct dev_pagemap *pgmap =3D page_pgmap(page); + int ret; + + pfn_req_flags &=3D range->pfn_flags_mask; + pfn_req_flags |=3D range->default_flags; + + /* + * Don't fault in device private pages owned by the caller, + * just report the PFN. + */ + if (pgmap->owner =3D=3D range->dev_private_owner) { + *hmm_pfn =3D swp_offset_pfn(entry); + goto found; + } + + /* + * P2P for supported pages, and according to caller request + * translate the private page to the match P2P page if it fails + * continue with the regular flow + */ + if (pfn_req_flags & HMM_PFN_ALLOW_P2P && + pgmap->ops->get_dma_pfn_for_device) { + ret =3D pgmap->ops->get_dma_pfn_for_device(page, hmm_pfn); + if (!ret) + goto found; + + } + + return false; + +found: + *hmm_pfn |=3D HMM_PFN_VALID; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:52:12.9731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87185bc8-c921-4ccf-f5b6-08ddc5f188e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6067 Content-Type: text/plain; charset="utf-8" From: Yonatan Maman Enabling Peer-to-Peer DMA (P2P DMA) access in GPU-centric applications is crucial for minimizing data transfer overhead (e.g., for RDMA use- case). This change aims to enable that capability for Nouveau over HMM device private pages. P2P DMA for private device pages allows the GPU to directly exchange data with other devices (e.g., NICs) without needing to traverse system RAM. To fully support Peer-to-Peer for device private pages, the following changes are made: - Introduce struct nouveau_dmem_hmm_p2p within struct nouveau_dmem to manage BAR1 PCI P2P memory. p2p_start_addr holds the virtual address allocated with pci_alloc_p2pmem(), and p2p_size represents the allocated size of the PCI P2P memory. - nouveau_dmem_init - Ensure BAR1 accessibility and assign struct pages (PCI_P2P_PAGE) for all BAR1 pages. Introduce nouveau_alloc_bar1_pci_p2p_mem in nouveau_dmem to expose BAR1 for use as P2P memory via pci_p2pdma_add_resource and implement static allocation and assignment of struct pages using pci_alloc_p2pmem. This function will be called from nouveau_dmem_init, and failure triggers a warning message instead of driver failure. - nouveau_dmem_fini - Ensure BAR1 PCI P2P memory is properly destroyed during driver cleanup. Introduce nouveau_destroy_bar1_pci_p2p_mem to handle freeing of PCI P2P memory associated with Nouveau BAR1. Modify nouveau_dmem_fini to call nouveau_destroy_bar1_pci_p2p_mem. - Implement Nouveau `p2p_page` callback function - Implement BAR1 mapping for the chunk using `io_mem_reserve` if no mapping exists. Retrieve the pre-allocated P2P virtual address and size from `hmm_p2p`. Calculate the page offset within BAR1 and return the corresponding P2P page. Signed-off-by: Yonatan Maman Reviewed-by: Gal Shalom --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 110 +++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouve= au/nouveau_dmem.c index ca4932a150e3..acac1449d8cb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -40,6 +40,9 @@ #include #include #include +#include +#include + =20 /* * FIXME: this is ugly right now we are using TTM to allocate vram and we = pin @@ -77,9 +80,15 @@ struct nouveau_dmem_migrate { struct nouveau_channel *chan; }; =20 +struct nouveau_dmem_hmm_p2p { + size_t p2p_size; + void *p2p_start_addr; +}; + struct nouveau_dmem { struct nouveau_drm *drm; struct nouveau_dmem_migrate migrate; + struct nouveau_dmem_hmm_p2p hmm_p2p; struct list_head chunks; struct mutex mutex; struct page *free_pages; @@ -159,6 +168,60 @@ static int nouveau_dmem_copy_one(struct nouveau_drm *d= rm, struct page *spage, return 0; } =20 +static int nouveau_dmem_bar1_mapping(struct nouveau_bo *nvbo, + unsigned long long *bus_addr) +{ + int ret; + struct ttm_resource *mem =3D nvbo->bo.resource; + + if (mem->bus.offset) { + *bus_addr =3D mem->bus.offset; + return 0; + } + + if (PFN_UP(nvbo->bo.base.size) > PFN_UP(nvbo->bo.resource->size)) + return -EINVAL; + + ret =3D ttm_bo_reserve(&nvbo->bo, false, false, NULL); + if (ret) + return ret; + + ret =3D nvbo->bo.bdev->funcs->io_mem_reserve(nvbo->bo.bdev, mem); + *bus_addr =3D mem->bus.offset; + + ttm_bo_unreserve(&nvbo->bo); + return ret; +} + +static int nouveau_dmem_get_dma_pfn(struct page *private_page, + unsigned long *dma_pfn) +{ + int ret; + unsigned long long offset_in_chunk; + unsigned long long chunk_bus_addr; + unsigned long long bar1_base_addr; + struct nouveau_drm *drm =3D page_to_drm(private_page); + struct nouveau_bo *nvbo =3D nouveau_page_to_chunk(private_page)->bo; + struct nvkm_device *nv_device =3D nvxx_device(drm); + size_t p2p_size =3D drm->dmem->hmm_p2p.p2p_size; + + bar1_base_addr =3D nv_device->func->resource_addr(nv_device, 1); + offset_in_chunk =3D + (page_to_pfn(private_page) << PAGE_SHIFT) - + nouveau_page_to_chunk(private_page)->pagemap.range.start; + + ret =3D nouveau_dmem_bar1_mapping(nvbo, &chunk_bus_addr); + if (ret) + return ret; + + *dma_pfn =3D chunk_bus_addr + offset_in_chunk; + if (!p2p_size || *dma_pfn > bar1_base_addr + p2p_size || + *dma_pfn < bar1_base_addr) + return -ENOMEM; + + return 0; +} + static vm_fault_t nouveau_dmem_migrate_to_ram(struct vm_fault *vmf) { struct nouveau_drm *drm =3D page_to_drm(vmf->page); @@ -222,6 +285,7 @@ static vm_fault_t nouveau_dmem_migrate_to_ram(struct vm= _fault *vmf) static const struct dev_pagemap_ops nouveau_dmem_pagemap_ops =3D { .page_free =3D nouveau_dmem_page_free, .migrate_to_ram =3D nouveau_dmem_migrate_to_ram, + .get_dma_pfn_for_device =3D nouveau_dmem_get_dma_pfn, }; =20 static int @@ -407,14 +471,31 @@ nouveau_dmem_evict_chunk(struct nouveau_dmem_chunk *c= hunk) kvfree(dma_addrs); } =20 +static void nouveau_destroy_bar1_pci_p2p_mem(struct nouveau_drm *drm, + struct pci_dev *pdev, + void *p2p_start_addr, + size_t p2p_size) +{ + if (p2p_size) + pci_free_p2pmem(pdev, p2p_start_addr, p2p_size); + + NV_INFO(drm, "PCI P2P memory freed(%p)\n", p2p_start_addr); +} + void nouveau_dmem_fini(struct nouveau_drm *drm) { struct nouveau_dmem_chunk *chunk, *tmp; + struct nvkm_device *nv_device =3D nvxx_device(drm); =20 if (drm->dmem =3D=3D NULL) return; =20 + nouveau_destroy_bar1_pci_p2p_mem(drm, + nv_device->func->pci(nv_device)->pdev, + drm->dmem->hmm_p2p.p2p_start_addr, + drm->dmem->hmm_p2p.p2p_size); + mutex_lock(&drm->dmem->mutex); =20 list_for_each_entry_safe(chunk, tmp, &drm->dmem->chunks, list) { @@ -579,10 +660,28 @@ nouveau_dmem_migrate_init(struct nouveau_drm *drm) return -ENODEV; } =20 +static int nouveau_alloc_bar1_pci_p2p_mem(struct nouveau_drm *drm, + struct pci_dev *pdev, size_t size, + void **pp2p_start_addr) +{ + int ret; + + ret =3D pci_p2pdma_add_resource(pdev, 1, size, 0); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:52:14.7180 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62247cfc-b5b6-4b2e-712c-08ddc5f189e2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF0000020A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5914 Content-Type: text/plain; charset="utf-8" From: Yonatan Maman Add Peer-to-Peer (P2P) DMA request for hmm_range_fault calling, utilizing capabilities introduced in mm/hmm. By setting range.default_flags to HMM_PFN_REQ_FAULT | HMM_PFN_REQ_TRY_P2P, HMM attempts to initiate P2P DMA connections for device private pages (instead of page fault handling). This enhancement utilizes P2P DMA to reduce performance overhead during data migration between devices (e.g., GPU) and system memory, providing performance benefits for GPU-centric applications that utilize RDMA and device private pages. Signed-off-by: Yonatan Maman Signed-off-by: Gal Shalom --- drivers/infiniband/core/umem_odp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/infiniband/core/umem_odp.c b/drivers/infiniband/core/u= mem_odp.c index b1c44ec1a3f3..7ba80ed4977c 100644 --- a/drivers/infiniband/core/umem_odp.c +++ b/drivers/infiniband/core/umem_odp.c @@ -362,6 +362,10 @@ int ib_umem_odp_map_dma_and_lock(struct ib_umem_odp *u= mem_odp, u64 user_virt, range.default_flags |=3D HMM_PFN_REQ_WRITE; } =20 + if (access_mask & HMM_PFN_ALLOW_P2P) + range.default_flags |=3D HMM_PFN_ALLOW_P2P; + + range.pfn_flags_mask =3D HMM_PFN_ALLOW_P2P; range.hmm_pfns =3D &(umem_odp->map.pfn_list[pfn_start_idx]); timeout =3D jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); =20 --=20 2.34.1 From nobody Mon Oct 6 17:09:56 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2056.outbound.protection.outlook.com [40.107.243.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE7572D97A9; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:52:27.9834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb9c1271-119a-4c9b-3cc4-08ddc5f191db X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6414 Content-Type: text/plain; charset="utf-8" From: Yonatan Maman Add support for P2P for MLX5 NIC devices with automatic fallback to standard DMA when P2P mapping fails. The change introduces P2P DMA requests by default using the HMM_PFN_ALLOW_P2P flag. If P2P mapping fails with -EFAULT error, the operation is retried without the P2P flag, ensuring a fallback to standard DMA flow (using host memory). Signed-off-by: Yonatan Maman Signed-off-by: Gal Shalom --- drivers/infiniband/hw/mlx5/odp.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/infiniband/hw/mlx5/odp.c b/drivers/infiniband/hw/mlx5/= odp.c index f6abd64f07f7..6a0171117f48 100644 --- a/drivers/infiniband/hw/mlx5/odp.c +++ b/drivers/infiniband/hw/mlx5/odp.c @@ -715,6 +715,10 @@ static int pagefault_real_mr(struct mlx5_ib_mr *mr, st= ruct ib_umem_odp *odp, if (odp->umem.writable && !downgrade) access_mask |=3D HMM_PFN_WRITE; =20 + /* + * try fault with HMM_PFN_ALLOW_P2P flag + */ + access_mask |=3D HMM_PFN_ALLOW_P2P; np =3D ib_umem_odp_map_dma_and_lock(odp, user_va, bcnt, access_mask, faul= t); if (np < 0) return np; @@ -724,6 +728,18 @@ static int pagefault_real_mr(struct mlx5_ib_mr *mr, st= ruct ib_umem_odp *odp, * ib_umem_odp_map_dma_and_lock already checks this. */ ret =3D mlx5r_umr_update_xlt(mr, start_idx, np, page_shift, xlt_flags); + if (ret =3D=3D -EFAULT) { + /* + * Indicate P2P Mapping Error, retry with no HMM_PFN_ALLOW_P2P + */ + mutex_unlock(&odp->umem_mutex); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:52:35.2142 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e54f7cd4-055e-45db-d1cd-08ddc5f1962c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7460 Content-Type: text/plain; charset="utf-8" From: Yonatan Maman ATS (Address Translation Services) mainly utilized to optimize PCI Peer-to-Peer transfers and prevent bus failures. This change employed ATS usage for ODP memory, to optimize DMA P2P for ODP memory. (e.g DMA P2P for private device pages - ODP memory). Signed-off-by: Yonatan Maman Signed-off-by: Gal Shalom --- drivers/infiniband/hw/mlx5/mlx5_ib.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/m= lx5/mlx5_ib.h index fde859d207ae..a7b7a565b7e8 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -1734,9 +1734,9 @@ static inline bool rt_supported(int ts_cap) static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, struct ib_umem *umem, int access_flags) { - if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) - return false; - return access_flags & IB_ACCESS_RELAXED_ORDERING; + if (MLX5_CAP_GEN(dev->mdev, ats) && (umem->is_dmabuf || umem->is_odp)) + return access_flags & IB_ACCESS_RELAXED_ORDERING; + return false; } =20 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, --=20 2.34.1