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charset="utf-8" Each PCIe controller on SA8775P includes a 'link_down' reset line in hardware. This patch documents the reset in the device tree binding. The 'link_down' reset is used to forcefully bring down the PCIe link layer, which is useful in scenarios such as link recovery after errors, power management transitions, and hotplug events. Including this reset line improves robustness and provides finer control over PCIe controller behavior. As the 'link_down' reset was omitted in the initial submission, it is now being documented. While this reset is not required for most of the block's basic functionality, and device trees lacking it will continue to function correctly in most cases, it is necessary to ensure maximum robustness when shutting down or recovering the PCIe core. Therefore, its inclusion is justified despite the minor ABI change. Signed-off-by: Ziyue Zhang Reviewed-by: Johan Hovold Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index 4b91b5608013..19afe2a03409 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -66,11 +66,14 @@ properties: - const: global =20 resets: - maxItems: 1 + items: + - description: PCIe controller reset + - description: PCIe link down reset =20 reset-names: items: - const: pci + - const: link_down =20 required: - interconnects @@ -166,8 +169,10 @@ examples: =20 power-domains =3D <&gcc PCIE_0_GDSC>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; =20 perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; --=20 2.34.1