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charset="utf-8" The gcc_aux_clk is required by the PCIe controller but not by the PCIe PHY. In PCIe PHY, the source of aux_clk used in low-power mode should be gcc_phy_aux_clk. Hence, remove gcc_aux_clk and replace it with gcc_phy_aux_clk. Removed the phy_aux clock from the PCIe PHY binding as it is no longer used by any instance. Fixes: fd2d4e4c1986 ("dt-bindings: phy: qcom,qmp: Add sa8775p QMP PCIe PHY") Signed-off-by: Ziyue Zhang Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 2c6c9296e4c0..17fd6547d3b4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -176,6 +176,8 @@ allOf: contains: enum: - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy @@ -197,8 +199,6 @@ allOf: contains: enum: - qcom,qcs8300-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x4-pcie-phy then: properties: clocks: --=20 2.34.1 From nobody Mon Oct 6 17:06:22 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62E8E1F95C; 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charset="utf-8" Each PCIe controller on SA8775P includes a 'link_down' reset line in hardware. This patch documents the reset in the device tree binding. The 'link_down' reset is used to forcefully bring down the PCIe link layer, which is useful in scenarios such as link recovery after errors, power management transitions, and hotplug events. Including this reset line improves robustness and provides finer control over PCIe controller behavior. As the 'link_down' reset was omitted in the initial submission, it is now being documented. While this reset is not required for most of the block's basic functionality, and device trees lacking it will continue to function correctly in most cases, it is necessary to ensure maximum robustness when shutting down or recovering the PCIe core. Therefore, its inclusion is justified despite the minor ABI change. Signed-off-by: Ziyue Zhang Reviewed-by: Johan Hovold Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index 4b91b5608013..19afe2a03409 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -66,11 +66,14 @@ properties: - const: global =20 resets: - maxItems: 1 + items: + - description: PCIe controller reset + - description: PCIe link down reset =20 reset-names: items: - const: pci + - const: link_down =20 required: - interconnects @@ -166,8 +169,10 @@ examples: =20 power-domains =3D <&gcc PCIE_0_GDSC>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; 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charset="utf-8" gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and replace it with gcc_phy_aux_clk. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 9997a29901f5..39a4f59d8925 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7707,16 +7707,18 @@ pcie0_phy: phy@1c04000 { compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg =3D <0x0 0x1c04000 0x0 0x2000>; =20 - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; - - clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; =20 assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 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Fri, 18 Jul 2025 08:17:24 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 56I8HMhI009039; Fri, 18 Jul 2025 08:17:22 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 47ugsn1e3m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Jul 2025 08:17:22 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 56I8HLKX009025; Fri, 18 Jul 2025 08:17:21 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (cse-cd01-lnx.qualcomm.com [10.64.75.209]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 56I8HLVN009019 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Jul 2025 08:17:21 +0000 Received: by cse-cd01-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id CE6BD20F21; Fri, 18 Jul 2025 16:17:19 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Konrad Dybcio Subject: [PATCH v5 4/4] arm64: dts: qcom: sa8775p: add link_down reset for pcie Date: Fri, 18 Jul 2025 16:17:18 +0800 Message-Id: <20250718081718.390790-5-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718081718.390790-1-ziyue.zhang@oss.qualcomm.com> References: <20250718081718.390790-1-ziyue.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE4MDA2NCBTYWx0ZWRfX556J9A2iHR0E PRWGf60HqHjQi6X20AIKPRGWKTFcy9v04n15ckbsFZ0M1ufmJIY6VULWaOvMFY3fSFve7ztoLDc KIEVMF+midS3QT2l7A59Wm/Ax+HyLXxDxR/CyOPWm3mC5vGwUmCwFuMBToceAQvQhTiv0zd8r4V bOgQ+G4uy2CQ9/Q+3ZCyKDumLnQ4CVrJkTEB9kIlGKKkBr8IF1JQ6ublKztu8eFW+ZXaVRtgSgz lzHF4Gle1IxbD4g5jNDAWOmuTdUo9FAlBZ98/cMURjF7T6iaRTGVASb2tKEgB+5U9Z+x+qMmfIb MdtomrDl8fDB87L2nMZqvE6zYA/6BEz/UI5yGMN95vQp4iWpPzbaV8ThIbKjgH1cI2JP+Ye+VXF k4qGqlWuUkisn862tzcnb/Qbn3ginHLXjz3NyEgea8xg1JXCkGu1qXHBM5VidSEbx2k7S8lf X-Proofpoint-GUID: LHGcv2tjgp2uiEj88sgslubYgOoDwszm X-Authority-Analysis: v=2.4 cv=SZT3duRu c=1 sm=1 tr=0 ts=687a0314 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=UMluCPnEzjiUAf4N7sYA:9 X-Proofpoint-ORIG-GUID: LHGcv2tjgp2uiEj88sgslubYgOoDwszm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-18_01,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507180064 Content-Type: text/plain; charset="utf-8" SA8775p supports 'link_down' reset on hardware, so add it for both pcie0 and pcie1, which can provide a better user experience. Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang Reviewed-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 39a4f59d8925..76bced68a2d2 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7635,8 +7635,11 @@ pcie0: pcie@1c00000 { iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + power-domains =3D <&gcc PCIE_0_GDSC>; =20 phys =3D <&pcie0_phy>; @@ -7803,8 +7806,11 @@ pcie1: pcie@1c10000 { iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, <0x100 &pcie_smmu 0x0081 0x1>; =20 - resets =3D <&gcc GCC_PCIE_1_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + power-domains =3D <&gcc PCIE_1_GDSC>; =20 phys =3D <&pcie1_phy>; --=20 2.34.1