From nobody Mon Oct 6 19:09:15 2025 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 256A7213E66 for ; Fri, 18 Jul 2025 07:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752822095; cv=none; b=c6XxqS/VFN1RXlTHaSRtuYirTt0iPDSDcxz+qyENZLSYrzASizbssY3QZ7CcR9Ewx2TCgbsmDAL5SkiRDE9DYoSm0oEcZhYMjalq16GbBDaMk6XeB8azFuD1mDNjmpEZpDR2fPves0QkxChpoCU80URScashCRHvBs7DNDa30+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752822095; c=relaxed/simple; bh=w8HyUGSw2smGLYHx1uivJrJ+uFxsulh+KFQgrb1Ibfg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o3XgWOTXFsPHAGoHysjdCSeq54QDc2TfKb4EaNI0avKwFVTmCn5fheRL88xfN4Qo5nzqekQGaSVGrGZ2ZfeqeQBYpCd4GoRR9/GlxrNBUD9uLk8LqkgOVUd7PIQ+wnGbT6CNQc3XXP3B1eyHnhGBGw7vmOVIGISLW6G955UZQ2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4bk0zm2t7GztSkf; Fri, 18 Jul 2025 15:00:20 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id 55CCA180B66; Fri, 18 Jul 2025 15:01:25 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 18 Jul 2025 15:01:25 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 18 Jul 2025 15:01:24 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 drm-dp 06/11] drm/hisilicon/hibmc: add dp mode valid check Date: Fri, 18 Jul 2025 14:51:20 +0800 Message-ID: <20250718065125.2892404-7-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250718065125.2892404-1-shiyongbang@huawei.com> References: <20250718065125.2892404-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li If DP is connected, add mode check and BW check in mode_valid_ctx() to ensure DP's cfg is usable. For example: Some DP's mode(1920x1080 60HZ 138.5 MHz) gives to drm, however, the GPU is configured for 148MHz in display_ctrl_adjust() by looking up the table of struct hibmc_pll_table{}. This difference will cause the DP to not display because the clock the DP gets via drm frame is 138MHz. Fixes: f9698f802e50 ("drm/hisilicon/hibmc: Restructuring the header dp_reg.= h") Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 10 ++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 6 +++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 51 +++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index b4d612047f36..7fbd51ffd778 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -276,6 +276,16 @@ void hibmc_dp_reset_link(struct hibmc_dp *dp) dp->dp_dev->link.status.channel_equalized =3D false; } =20 +u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.link_rate; +} + +u8 hibmc_dp_get_lanes(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.lanes; +} + static const struct hibmc_dp_color_raw g_rgb_raw[] =3D { {CBAR_COLOR_BAR, 0x000, 0x000, 0x000}, {CBAR_WHITE, 0xfff, 0xfff, 0xfff}, diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 9b45e88e47e4..0059a2648a38 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -12,6 +12,10 @@ #include #include =20 +/* 27 * 10000000 * 80% =3D 216000000 */ +#define DP_MODE_VALI_CAL 216000000 +#define BPP_24 24 + struct hibmc_dp_dev; =20 enum hibmc_dp_cbar_pattern { @@ -62,5 +66,7 @@ void hibmc_dp_reset_link(struct hibmc_dp *dp); void hibmc_dp_hpd_cfg(struct hibmc_dp *dp); void hibmc_dp_enable_int(struct hibmc_dp *dp); void hibmc_dp_disable_int(struct hibmc_dp *dp); +u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp); +u8 hibmc_dp_get_lanes(struct hibmc_dp *dp); =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index 354e18bb2998..99b30a6c7e06 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -15,6 +15,28 @@ =20 #define DP_MASKED_SINK_HPD_PLUG_INT BIT(2) =20 +struct hibmc_dp_disp_clk { + u16 hdisplay; + u16 vdisplay; + u32 clock; +}; + +static const struct hibmc_dp_disp_clk hibmc_dp_clk_table[] =3D { + {640, 480, 25175}, /* 25175 khz */ + {800, 600, 40000}, /* 40000 khz */ + {1024, 768, 65000}, /* 65000 khz */ + {1152, 864, 80000}, /* 80000 khz */ + {1280, 768, 79500}, /* 79500 khz */ + {1280, 720, 74250}, /* 74250 khz */ + {1280, 960, 108000}, /* 108000 khz */ + {1280, 1024, 108000}, /* 108000 khz */ + {1440, 900, 106500}, /* 106500 khz */ + {1600, 900, 108000}, /* 108000 khz */ + {1600, 1200, 162000}, /* 162000 khz */ + {1920, 1080, 148500}, /* 148500 khz */ + {1920, 1200, 193250}, /* 193250 khz */ +}; + static int hibmc_dp_connector_get_modes(struct drm_connector *connector) { const struct drm_edid *drm_edid; @@ -42,9 +64,38 @@ static int hibmc_dp_detect(struct drm_connector *connect= or, return connector_status_disconnected; } =20 +static int hibmc_dp_mode_valid(struct drm_connector *connector, + const struct drm_display_mode *mode, + struct drm_modeset_acquire_ctx *ctx, + enum drm_mode_status *status) +{ + struct hibmc_dp *dp =3D to_hibmc_dp(connector); + u64 cur_val, max_val; + + /* check DP link BW */ + cur_val =3D (u64)mode->htotal * mode->vtotal * drm_mode_vrefresh(mode) * = BPP_24; + max_val =3D (u64)hibmc_dp_get_link_rate(dp) * DP_MODE_VALI_CAL * hibmc_dp= _get_lanes(dp); + + *status =3D cur_val > max_val ? MODE_CLOCK_HIGH : MODE_OK; + + /* check the clock */ + for (size_t i =3D 0; i < ARRAY_SIZE(hibmc_dp_clk_table); i++) { + if (hibmc_dp_clk_table[i].hdisplay =3D=3D mode->hdisplay && + hibmc_dp_clk_table[i].vdisplay =3D=3D mode->vdisplay) { + if (hibmc_dp_clk_table[i].clock !=3D mode->clock) { + *status =3D MODE_CLOCK_RANGE; + return 0; + } + } + } + + return 0; +} + static const struct drm_connector_helper_funcs hibmc_dp_conn_helper_funcs = =3D { .get_modes =3D hibmc_dp_connector_get_modes, .detect_ctx =3D hibmc_dp_detect, + .mode_valid_ctx =3D hibmc_dp_mode_valid, }; =20 static int hibmc_dp_late_register(struct drm_connector *connector) --=20 2.33.0