From nobody Mon Oct 6 19:09:13 2025 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B693B20299E for ; Fri, 18 Jul 2025 07:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752822090; cv=none; b=siuTZqRol6a7jrbzKlSilwcGpMMITjSOEKjxFPNlbka9Zh2S1QhcdX+QlFIolQX3VNKOGupUwCFWYXNZrP3OKJkctAcjVkXUym9zFcxulVu65/lBPghYUhIPIrlnXlwriTXdu8M9tBUg0Oy7PDxJo+PkXuifVWTyZHjNlJ/6e0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752822090; c=relaxed/simple; bh=+1aaXO/Xhp/1BxTDqzpFeLioebk825bpt6A++VONwfg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jgqSc4ttvV/3UCq+eCU2wAcVx0yK70SESxTx6140vUVznJRUrETfRm6qGeI1roZxrRF9WdEhkGhuCdYXPiMJn6FRijvN+1drXLK/FLvasBw0SCCpxTL589MEFiaq57oY735QU1DjAiwJEi3q+3Q3RL8i4S/7Z8jWRzipRkiMGM0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4bk0wG4KlRzdbxd; Fri, 18 Jul 2025 14:57:18 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id AD2C0180468; Fri, 18 Jul 2025 15:01:26 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 18 Jul 2025 15:01:26 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 18 Jul 2025 15:01:25 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 drm-dp 09/11] drm/hisilicon/hibmc: fix no showing problem with loading hibmc manually Date: Fri, 18 Jul 2025 14:51:23 +0800 Message-ID: <20250718065125.2892404-10-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250718065125.2892404-1-shiyongbang@huawei.com> References: <20250718065125.2892404-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li When using command rmmod and insmod, there is no showing in second time insmoding. Because DP controller won't send HPD signals, if connection doesn't change or controller isn't reset. So add reset before unreset in hibmc_dp_hw_init(). Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this hot plug detect of i= rq feature") Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- ChangeLog: v2 -> v3: - fix the issue commit ID, suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index 7fbd51ffd778..36daf7542d40 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -181,6 +181,8 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); /* rst */ + writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + usleep_range(30, 50); writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); /* clock enable */ writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); --=20 2.33.0