From nobody Mon Oct 6 20:59:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19DE61EDA03; Fri, 18 Jul 2025 01:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802820; cv=none; b=UugzM6zK4NVpOHXzXDvA04UXcraV3/Mt8K5KNSZWaxNGoCfyVYxRATi7aQqhoVtx8WnxFIy+/VSnAZ1MxcOMPTmpI0n17WnMtIma+oHrrnEeXu22kYSTrqagJom6OjPuF96zQcroJZii6+N2ENzCM4/eNhZHMET0R5y5wQbpYiQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802820; c=relaxed/simple; bh=0hNsv9KESme0CC07v7qNNGShOQXUwWV1Ff+LbnZiLcI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ku+YRdyd6/VRwfbQBZTzlrYalP6uuYYA9BJHyZo5cjH14582sAATQhYVbftsttcKsVOLm/sEOwmFz8Cb02WXdHrlWFmwqL90YNYNyHSJxUa0iUgheu3lOG1K1v5wEhzZcXnfcOr1s+5ONDN++5pyxrVGLcGXtzMG0zuRKFQ8Jgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HPA4GaZ9; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HPA4GaZ9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802820; x=1784338820; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0hNsv9KESme0CC07v7qNNGShOQXUwWV1Ff+LbnZiLcI=; b=HPA4GaZ9bcleXb/R66S5GTCzhyMb9E5d7FhU8XJLd0dcxmmzHmHfzGbp vLk3R0YMhMaTnkUQY2NZ7mLWuuG8m9kLQEsWhz2/DLdu5Ff3ORGlYdF5/ UXE22qwpP7MAdCBXzgGC2vGoWNQB4TVXJ048Px9zkuwyPGH+CSd5w4laL 9MUFC+ewIdhbEtMXcd9M//x4XP9fJEh6lGkuq54thQr27vnQutJcnI/W2 XvvUT3lljFepVFe1yzTr5JJYwpOp42Ol8GuVFHgavqQtX+E7+/Uu18H8W K/4GCsK7ug7O+aLIyPZSnQGDOlBOJXyD+O8Q/Cc8mHUKTGNIZSxb7M+5o A==; X-CSE-ConnectionGUID: FUGX8D11SY2EXSzZUcbJDA== X-CSE-MsgGUID: lezntrBPQE+ZYAVEqxaeew== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951531" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951531" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:19 -0700 X-CSE-ConnectionGUID: GuyVw/LERkaYaxvH1lFrmQ== X-CSE-MsgGUID: c4oOsBp/Tm6eklQ9uvmY+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918429" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:40:15 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , Dapeng Mi , Kan Liang Subject: [kvm-unit-tests patch v2 7/7] x86: pmu_pebs: Support to validate timed PEBS record on GNR/SRF Date: Fri, 18 Jul 2025 09:39:15 +0800 Message-Id: <20250718013915.227452-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Intel GNR/SRF platform, timed PEBS is introduced. Timed PEBS adds a new "retired latency" field in basic info group to show the timing info. IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to indicate whether timed PEBS is supported. After introducing timed PEBS, the PEBS record format field shrinks to bits[31:0] and the bits[47:32] is used to record retired latency. Thus shrink the record format to bits[31:0] accordingly and avoid the retired latency field is recognized a part of record format to compare and cause failure on GNR/SRF. Please find detailed information about timed PEBS in section 8.4.1 "Timed Processor Event Based Sampling" of "Intel Architecture Instruction Set Extensions and Future Features". Reviewed-by: Kan Liang Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- lib/x86/pmu.h | 6 ++++++ x86/pmu_pebs.c | 8 +++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h index c7dc68c1..86a7a05f 100644 --- a/lib/x86/pmu.h +++ b/lib/x86/pmu.h @@ -20,6 +20,7 @@ #define PMU_CAP_LBR_FMT 0x3f #define PMU_CAP_FW_WRITES (1ULL << 13) #define PMU_CAP_PEBS_BASELINE (1ULL << 14) +#define PMU_CAP_PEBS_TIMING_INFO (1ULL << 17) #define PERF_CAP_PEBS_FORMAT 0xf00 =20 #define EVNSEL_EVENT_SHIFT 0 @@ -188,4 +189,9 @@ static inline bool pmu_has_pebs_baseline(void) return pmu.perf_cap & PMU_CAP_PEBS_BASELINE; } =20 +static inline bool pmu_has_pebs_timing_info(void) +{ + return pmu.perf_cap & PMU_CAP_PEBS_TIMING_INFO; +} + #endif /* _X86_PMU_H_ */ diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 2848cc1e..bc37e8e3 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -277,6 +277,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive unsigned int count =3D 0; bool expected, pebs_idx_match, pebs_size_match, data_cfg_match; void *cur_record; + u64 format_mask; =20 expected =3D (ds->pebs_index =3D=3D ds->pebs_buffer_base) && !pebs_rec->f= ormat_size; if (!(rdmsr(MSR_CORE_PERF_GLOBAL_STATUS) & GLOBAL_STATUS_BUFFER_OVF)) { @@ -289,6 +290,8 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive return; } =20 + /* Record format shrinks to bits[31:0] after timed PEBS is introduced. */ + format_mask =3D pmu_has_pebs_timing_info() ? GENMASK_ULL(31, 0) : GENMASK= _ULL(47, 0); expected =3D ds->pebs_index >=3D ds->pebs_interrupt_threshold; cur_record =3D (void *)pebs_buffer; do { @@ -296,8 +299,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size =3D pebs_rec->format_size >> RECORD_SIZE_OFFSET; pebs_idx_match =3D pebs_rec->applicable_counters & bitmask; pebs_size_match =3D pebs_record_size =3D=3D get_pebs_record_size(pebs_da= ta_cfg, use_adaptive); - data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D - (use_adaptive ? pebs_data_cfg : 0); + data_cfg_match =3D (pebs_rec->format_size & format_mask) =3D=3D (use_ada= ptive ? pebs_data_cfg : 0); expected =3D pebs_idx_match && pebs_size_match && data_cfg_match; report(expected, "PEBS record (written seq %d) is verified (including size, counte= rs and cfg).", count); @@ -327,7 +329,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size, get_pebs_record_size(pebs_data_cfg, use_adapti= ve)); if (!data_cfg_match) printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with the effectiv= e MSR_PEBS_DATA_CFG (0x%lx).\n", - pebs_rec->format_size & 0xffffffffffff, use_adaptive ? pebs_data= _cfg : 0); + pebs_rec->format_size & format_mask, use_adaptive ? pebs_data_cf= g : 0); } } =20 --=20 2.34.1