From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DA71194A60; Fri, 18 Jul 2025 01:39:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802800; cv=none; b=B1DmcvJyDY514bs7V9QrPmiPZGsvXrh0RZU4S19uwSrqLjzfmZyhSmXb1A2o2MY7UP9y/XooDjE3lbNOlXGZpJQwrLaLyZJPNMNOhdcGrn419Tlq4+J1WG+jOFMtbO/DYV3Qp8lCvPIW1RYUQDycYjjSZR5KH3RLZ612x9z8nMI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802800; c=relaxed/simple; bh=fT3sDIHjSujlwY4VLBHqNBqr18zjKD3cM+JhfiCXGY0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KoRCZEpUv1oef68UDbTXOxfMjf6Dt/jI//83iNxcESDSvbq6+nfIalt4GV6iexXqmpRRE6KZgI5xyLPdyNFla5DSEqCGKDPf4FbXOr+X4g7cdLQM/iv4TGvKYVqjyIrXJqmrmv7hHcZidxKsEETMMt+nXVlStCaOb0Lh03wKVGQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gTYc+9vb; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gTYc+9vb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802800; x=1784338800; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fT3sDIHjSujlwY4VLBHqNBqr18zjKD3cM+JhfiCXGY0=; b=gTYc+9vb7hQveYmNE7Wqq9C3ckLBfyKL9e9BKjFG9X9XKb7H9yJX5YbF B4UIp0COFd0qAQhPGNLoIoZQ8UYPQ2HWNf4oZckBk3nwh1ATIVa2nlDN9 c9xC7RwBODFBDC3Jnv5TB61AclWfxY11WgrRl25Aj+zeN8/p8cWxKtEiR MG2lDn+6ZmPIlkCEsgBJPUeIqEg2AGEarWqhnFKDUqC7tF9NC+6WmdLzz Xr4naZFp00LMdHzBIWXZ9nC7jcBZiqiDhnUp5sOOc14JzHTDDqUgllZ6H UuKFuqNs+UNIlkivHbxVhcwJWl7+l5uEvAeUsVqppdMF5lpdYpYBD3C3o g==; X-CSE-ConnectionGUID: S9q+kh6wTee/2EJdla/9Bg== X-CSE-MsgGUID: 0t/+ilgTSYq2/YBAcjkIfg== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951443" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951443" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:00 -0700 X-CSE-ConnectionGUID: P1XL2ch1T4aOu5bH6ZSr5g== X-CSE-MsgGUID: 2zEQiVstS5ev8vRQIuJKUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918351" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:39:56 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch v2 1/7] x86/pmu: Add helper to detect Intel overcount issues Date: Fri, 18 Jul 2025 09:39:09 +0800 Message-Id: <20250718013915.227452-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng For Intel Atom CPUs, the PMU events "Instruction Retired" or "Branch Instruction Retired" may be overcounted for some certain instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD and complex SGX/SMX/CSTATE instructions/flows. The detailed information can be found in the errata (section SRF7): https://edc.intel.com/content/www/us/en/design/products-and-solutions/proce= ssors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-cores-sp= ecification-update/errata-details/ For the Atom platforms before Sierra Forest (including Sierra Forest), Both 2 events "Instruction Retired" and "Branch Instruction Retired" would be overcounted on these certain instructions, but for Clearwater Forest only "Instruction Retired" event is overcounted on these instructions. So add a helper detect_inst_overcount_flags() to detect whether the platform has the overcount issue and the later patches would relax the precise count check by leveraging the gotten overcount flags from this helper. Signed-off-by: dongsheng [Rewrite comments and commit message - Dapeng] Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- lib/x86/processor.h | 27 ++++++++++++++++++++++++++ x86/pmu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 62f3d578..937f75e4 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -1188,4 +1188,31 @@ static inline bool is_lam_u57_enabled(void) return !!(read_cr3() & X86_CR3_LAM_U57); } =20 +/* Copy from kernel arch/x86/lib/cpu.c */ +static inline u32 x86_family(u32 sig) +{ + u32 x86; + + x86 =3D (sig >> 8) & 0xf; + + if (x86 =3D=3D 0xf) + x86 +=3D (sig >> 20) & 0xff; + + return x86; +} + +static inline u32 x86_model(u32 sig) +{ + u32 fam, model; + + fam =3D x86_family(sig); + + model =3D (sig >> 4) & 0xf; + + if (fam >=3D 0x6) + model +=3D ((sig >> 16) & 0xf) << 4; + + return model; +} + #endif diff --git a/x86/pmu.c b/x86/pmu.c index a6b0cfcc..87365aff 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -159,6 +159,14 @@ static struct pmu_event *gp_events; static unsigned int gp_events_size; static unsigned int fixed_counters_num; =20 +/* + * Flags for Intel "Instruction Retired" and "Branch Instruction Retired" + * overcount flaws. + */ +#define INST_RETIRED_OVERCOUNT BIT(0) +#define BR_RETIRED_OVERCOUNT BIT(1) +static u32 intel_inst_overcount_flags; + static int has_ibpb(void) { return this_cpu_has(X86_FEATURE_SPEC_CTRL) || @@ -959,6 +967,43 @@ static void check_invalid_rdpmc_gp(void) "Expected #GP on RDPMC(64)"); } =20 +/* + * For Intel Atom CPUs, the PMU events "Instruction Retired" or + * "Branch Instruction Retired" may be overcounted for some certain + * instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD + * and complex SGX/SMX/CSTATE instructions/flows. + * + * The detailed information can be found in the errata (section SRF7): + * https://edc.intel.com/content/www/us/en/design/products-and-solutions/p= rocessors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-core= s-specification-update/errata-details/ + * + * For the Atom platforms before Sierra Forest (including Sierra Forest), + * Both 2 events "Instruction Retired" and "Branch Instruction Retired" wo= uld + * be overcounted on these certain instructions, but for Clearwater Forest + * only "Instruction Retired" event is overcounted on these instructions. + */ +static u32 detect_inst_overcount_flags(void) +{ + u32 flags =3D 0; + struct cpuid c =3D cpuid(1); + + if (x86_family(c.a) =3D=3D 0x6) { + switch (x86_model(c.a)) { + case 0xDD: /* Clearwater Forest */ + flags =3D INST_RETIRED_OVERCOUNT; + break; + + case 0xAF: /* Sierra Forest */ + case 0x4D: /* Avaton, Rangely */ + case 0x5F: /* Denverton */ + case 0x86: /* Jacobsville */ + flags =3D INST_RETIRED_OVERCOUNT | BR_RETIRED_OVERCOUNT; + break; + } + } + + return flags; +} + int main(int ac, char **av) { int instruction_idx; @@ -985,6 +1030,8 @@ int main(int ac, char **av) branch_idx =3D INTEL_BRANCHES_IDX; branch_miss_idx =3D INTEL_BRANCH_MISS_IDX; =20 + intel_inst_overcount_flags =3D detect_inst_overcount_flags(); + /* * For legacy Intel CPUS without clflush/clflushopt support, * there is no way to force to trigger a LLC miss, thus set --=20 2.34.1 From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D5D1A5BBC; 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X-CSE-ConnectionGUID: fakO45F6TnWngRsB+1YFxQ== X-CSE-MsgGUID: rnAGqcEYTFSdBHfHR6JeBA== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951447" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951447" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:03 -0700 X-CSE-ConnectionGUID: ahKir1S+SNGcYgdo8tJxOg== X-CSE-MsgGUID: r6CrRDDBTwqLxEM0c7lE+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918361" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:39:59 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch v2 2/7] x86/pmu: Relax precise count validation for Intel overcounted platforms Date: Fri, 18 Jul 2025 09:39:10 +0800 Message-Id: <20250718013915.227452-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng As the VM-Exit/VM-Entry overcount issue on Intel Atom platforms, there is no way to validate the precise count for "instructions" and "branches" events on these overcounted Atom platforms. Thus relax the precise count validation on these overcounted platforms. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 87365aff..04946d10 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -237,10 +237,15 @@ static void adjust_events_range(struct pmu_event *gp_= events, * occur while running the measured code, e.g. if the host takes IRQs. */ if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) { - gp_events[instruction_idx].min =3D LOOP_INSNS; - gp_events[instruction_idx].max =3D LOOP_INSNS; - gp_events[branch_idx].min =3D LOOP_BRANCHES; - gp_events[branch_idx].max =3D LOOP_BRANCHES; + if (!(intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT)) { + gp_events[instruction_idx].min =3D LOOP_INSNS; + gp_events[instruction_idx].max =3D LOOP_INSNS; + } + + if (!(intel_inst_overcount_flags & BR_RETIRED_OVERCOUNT)) { + gp_events[branch_idx].min =3D LOOP_BRANCHES; + gp_events[branch_idx].max =3D LOOP_BRANCHES; + } } =20 /* --=20 2.34.1 From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA2231C84C0; Fri, 18 Jul 2025 01:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802807; cv=none; b=ZhFBBP4qQVu/qpx2nE1abj6OBKAN2u1guUBy6jzo/F+C2qJnSaGGsr03zXbzE+CCL18LFd0inxiZsQwGMXxBBkvYjv61kdAlz9gKMM45WwKPbzjsOoGUVWRCSBpUBlCEvgUa+hSBfViQXchA6GkmhG1qJCkxIaMrpmWzM/6HaKw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802807; c=relaxed/simple; bh=xZaOT2faqwrZtdkqO+qLsZJ8quiYyhmYLU8cnJOdgsM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G9ZezNXKH0PuxDsUYPL+TTNwfRtSaMnWYzBvZMnLdPOL8zPXBNT4IYNTzWL/SK7Ok2EjAbn5Ep7c+H6jHhaJJqJv9KJG5B8jp+Z4uglCVAvF3SygAio86Pcy8vFAGmDUmBlvQ+bByiXPu5t7eDL4mo8origyTq/Mp/2/LmbMQwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=c6ZuPuez; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c6ZuPuez" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802806; x=1784338806; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xZaOT2faqwrZtdkqO+qLsZJ8quiYyhmYLU8cnJOdgsM=; b=c6ZuPuez8dFOhcmEenmEB/2R7V2tVFLHuIg2SLls1zKyeIHkh2U9rf+5 dk7ZNbSqV7luRCIWuN92weJ4jKMay2lSS7kNsgP8Y9fmSKd9fJfjTo+Fu 3dnVNESodvb2v3ERctcAF2jXUqDeDDonTXo1WPmpmaiOetV3qkcvJQ6NV HUsZpQixlXxAA1dNxXKbQpjhgP9gJIKnsBlCOdNvmYawy/8Hj1vO6s4Xw MZzKC99FAvdGY0daLcHw36GpbLVRYhAlhS+Yu+5PEAGokzbMFRDJoMAG9 UVGjk6cAKThf1w0IWYC8TBkouqKrX5kfutoBiIWsx/bl7OMDuKo7vXmQV g==; X-CSE-ConnectionGUID: fBdlW84bStqG95C8sZ9iLQ== X-CSE-MsgGUID: 1zoOoAXjQJazc+nDcL0Xsg== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951476" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951476" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:06 -0700 X-CSE-ConnectionGUID: SGdC1Qa8Sm28DkmbzyI/rg== X-CSE-MsgGUID: nUXgnuv/SWivkYYAVxGoOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918382" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:40:02 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch v2 3/7] x86/pmu: Fix incorrect masking of fixed counters Date: Fri, 18 Jul 2025 09:39:11 +0800 Message-Id: <20250718013915.227452-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng The current implementation mistakenly limits the width of fixed counters to the width of GP counters. Corrects the logic to ensure fixed counters are properly masked according to their own width. Opportunistically refine the GP counter bitwidth processing code. Signed-off-by: dongsheng Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 04946d10..44c728a5 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -556,18 +556,16 @@ static void check_counter_overflow(void) int idx; =20 cnt.count =3D overflow_preset; - if (pmu_use_full_writes()) - cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; - if (i =3D=3D pmu.nr_gp_counters) { if (!pmu.is_intel) break; =20 cnt.ctr =3D fixed_events[0].unit_sel; - cnt.count =3D measure_for_overflow(&cnt); - cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; + cnt.count &=3D (1ull << pmu.fixed_counter_width) - 1; } else { cnt.ctr =3D MSR_GP_COUNTERx(i); + if (pmu_use_full_writes()) + cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; } =20 if (i % 2) --=20 2.34.1 From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E3F61D5CD1; Fri, 18 Jul 2025 01:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802810; cv=none; b=YNv8qeXEiR/pb2zgv8CUkvba90r4xYY8nJ4WZJ8eBKYqrSIWYQ4jnUFxNk+xb8aAOcVPg2ppt/ECNDR1KWsxAhIdARbHB5kA/rfUz4mZzxCN6plPit3tiLV43+FzjPaJSrIa+sFXUvhnGYCZoDLHyOSHVkXjToEHHjM4hYPP0tM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802810; c=relaxed/simple; bh=S7lk8W1qOqN6f2hlk12G1kiNj2WSIVk7J9ru7MHfT5M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fZEDwvTk4n20ym5d20WDrv+4PaZstgJ3tRTPhdHzNn6qDk84JBCKm0TQEit5abkyrks+kGOtjiSFhocbz+1dZTZQQBHs5s31ZM31DdeNmLUfVZLY9tRWeYnFlmTPC/8OM4AKBdBswOMhNQpqNUrFaZUV+s/rk8mqKK3xUDvNgLM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fcyMC768; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fcyMC768" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802810; x=1784338810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S7lk8W1qOqN6f2hlk12G1kiNj2WSIVk7J9ru7MHfT5M=; b=fcyMC768P83qKhLgnYxVn+1dY5Vrd0SpVESE1lDP+PtnlW3XgFsr5l/d eeNUWphzmcJh6+bk2FcQbIyskY0d6uX7Q08cpoyPNVA52bATQh6zRr0Ke kr2DYtab2p2NiocoR8/TxonKAIlzBogx+bYWNjlROZHpjoqm6vuWoDlO8 qfnWU8XpRWQ1nEmd+cV5rlqbSxiBaEGXko4uk7zqlwwWygh5Pjt97m5DC Bk/5/z1bfdrcyBr2BqKo2pkmBoaVj3v/whkvvSGTR/foot1d5eiNq1Ij3 cDOK0/X80ZIH5S7cb9bLtxDC3FozKFOALNDEKifMMB5JmJmf3gj7PDiRW A==; X-CSE-ConnectionGUID: u8QPAHcBS3OBrxLVZKiDvw== X-CSE-MsgGUID: uzx/9HXwR3uGBEK9RHewqA== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951502" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951502" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:10 -0700 X-CSE-ConnectionGUID: e4kx+BFIRx6hZgsV9apqCw== X-CSE-MsgGUID: S74PmfwxRxaA4KWjPvkOIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918402" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:40:06 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch v2 4/7] x86/pmu: Handle instruction overcount issue in overflow test Date: Fri, 18 Jul 2025 09:39:12 +0800 Message-Id: <20250718013915.227452-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng During the execution of __measure(), VM exits (e.g., due to WRMSR/EXTERNAL_INTERRUPT) may occur. On systems affected by the instruction overcount issue, each VM-Exit/VM-Entry can erroneously increment the instruction count by one, leading to false failures in overflow tests. To address this, the patch introduces a range-based validation in place of precise instruction count checks. Additionally, overflow_preset is now statically set to 1 - LOOP_INSNS, rather than being dynamically determined via measure_for_overflow(). These changes ensure consistent and predictable behavior aligned with the intended loop instruction count, while avoiding modifications to the subsequent status and status-clear testing logic. The chosen validation range is empirically derived to maintain test reliability across hardware variations. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 44c728a5..c54c0988 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -518,6 +518,21 @@ static void check_counters_many(void) =20 static uint64_t measure_for_overflow(pmu_counter_t *cnt) { + /* + * During the execution of __measure(), VM exits (e.g., due to + * WRMSR/EXTERNAL_INTERRUPT) may occur. On systems affected by the + * instruction overcount issue, each VM-Exit/VM-Entry can erroneously + * increment the instruction count by one, leading to false failures + * in overflow tests. + * + * To mitigate this, if the overcount issue is detected, we hardcode + * the overflow preset to (1 - LOOP_INSNS) instead of calculating it + * dynamically. This ensures that an overflow will reliably occur, + * regardless of any overcounting caused by VM exits. + */ + if (intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT) + return 1 - LOOP_INSNS; + __measure(cnt, 0); /* * To generate overflow, i.e. roll over to '0', the initial count just @@ -574,8 +589,12 @@ static void check_counter_overflow(void) cnt.config &=3D ~EVNTSEL_INT; idx =3D event_to_global_idx(&cnt); __measure(&cnt, cnt.count); - if (pmu.is_intel) - report(cnt.count =3D=3D 1, "cntr-%d", i); + if (pmu.is_intel) { + if (intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT) + report(cnt.count < 14, "cntr-%d", i); + else + report(cnt.count =3D=3D 1, "cntr-%d", i); + } else report(cnt.count =3D=3D 0xffffffffffff || cnt.count < 7, "cntr-%d", i); =20 --=20 2.34.1 From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B67751DE8BE; Fri, 18 Jul 2025 01:40:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802814; cv=none; b=ppC/ZV5z52Yhr3hB3Db6h7A44LbkY2SRYFkG/9sGQ6wnPkWzPraq2rowr7gyM1VtnuOUSd+urAHPoLNKWd7Duxr45Jc5jT0inybRNwPQ3mwr1nxFZnNpm12AhMK52U/Ftx4kSndcnLa5rA2e1zYH3DLwNJtHU44jY8cAm+FrZLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802814; c=relaxed/simple; bh=4QUPfFjhBY0qsc2M2KLTWST4hhzTyiWf2rdYoO1kkPc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DpdaJ5RbwbfoswtaV/TODpf6IIhPrB6F/mAKX+raOLO3mxlzORTer7oloOU0VUqgFQyjALp87Mjxx/oGtnIOHhcU2XvmDE3bov044T0Wy536TX+pxJW4Gr5OV+R3iui+dC1O1St1QCb4VZUmAJulnFKvqfGtr90Z/iZ+Q7MG3KA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZXVjFL8F; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZXVjFL8F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802813; x=1784338813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4QUPfFjhBY0qsc2M2KLTWST4hhzTyiWf2rdYoO1kkPc=; b=ZXVjFL8FczK8XaZvVjtPy0tjW7s+t7EyjxfFTaUS9S2un9INct8akR1W NnLdYHRuT0rpZndw3kkxUB6GuVxQiti8aEHq9Gj8IzQ/pmco/UWLfSD45 0W0dh7BeD4w76ofHXk0i9mGTAork249ywf0wMfHz2M0CiG9t3wP657mhZ smgd6I5tDPKtS8x+AIbkjoFGwincJyk/cX+lQ45+HD3qzGzgSeL9xblqJ TeWWvvKT+35p93/awyKaV640ERyfH1pACDpUn9RqD32HIGzr2EhWNmgYY 7w97ORfWaFM8hJP4BTdqqr62+WQzz1URgMBArVs4tiuRKN+G9JWh9eyuZ g==; X-CSE-ConnectionGUID: dMOBgshjQ1WjvlBtw7zbNg== X-CSE-MsgGUID: x5UkO3VkQPqEKOBemZz6eg== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951512" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951512" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:13 -0700 X-CSE-ConnectionGUID: RrcKjjsPS/e4ClH0i+tWMQ== X-CSE-MsgGUID: 2rXa9Ds8QtK9wqQu4KaAFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918415" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:40:09 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch v2 5/7] x86/pmu: Expand "llc references" upper limit for broader compatibility Date: Fri, 18 Jul 2025 09:39:13 +0800 Message-Id: <20250718013915.227452-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng Increase the upper limit of the "llc references" test to accommodate results observed on additional Intel CPU models, including CWF and SRF. These CPUs exhibited higher reference counts that previously caused the test to fail. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index c54c0988..445ea6b4 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -116,7 +116,7 @@ struct pmu_event { {"core cycles", 0x003c, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, {"ref cycles", 0x013c, 1*N, 30*N}, - {"llc references", 0x4f2e, 1, 2*N}, + {"llc references", 0x4f2e, 1, 2.5*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, {"branch misses", 0x00c5, 1, 0.1*N}, --=20 2.34.1 From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93D131E32A3; Fri, 18 Jul 2025 01:40:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802817; cv=none; b=tgrJTXsJ346WuVUuBkpdroJDRhatm2Le/96CHFssWUIPwVSJwNve+wn1q16TNyyutfuk8VjM3YSFVmeJF1I28pC6DE8dnd8qV+e08INlZrrEbX6pmTLxwMThJYF93yqmtGoePs2NTgZ7+csCfd82T3rJa+yvNKkCHUW2bxTWkwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802817; c=relaxed/simple; bh=IM6ZpntWH9mILQir1heZmjp9QGGWbJ+kZ3cIa25NE84=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Sm7c696lsdGyaDOKfQStIiipQByh+PjfhCzVmStQojkBDqv5xSrNFIwU5m7x8aWtpSzTS3QZb46ZosRg1gRLsJO7zrzDRpODgWE9vvpxvHOz38zqu+ayInMtKBGCFcuw+Lc/YwPzcgOKqPIBqjRZ+9bE7kjOe4tM/8vy3X2dhLE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IAkbbBOL; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IAkbbBOL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802816; x=1784338816; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IM6ZpntWH9mILQir1heZmjp9QGGWbJ+kZ3cIa25NE84=; b=IAkbbBOLmI9OdukVW9vt1U8Lv0qdBbmjlNdJPYcm6vtx+cpoHrlXhu6C iNOjRZvkOnlbmR3XguTgUL8nBjidT02ouKal6mesVT3bLNNilsfzixrZz qkkpThlmwFdkyUcvbvjpEiauU8Fb/4Ko4axaJFpgkcGkU0B0IJJdpVqc4 RKyaS8bpAt9uEV3cMD5kYgBUnFGwCZVIREpLsBOua3huzTr6h2eJ+KVD0 j66xHukdUBQtu+MAsd6RTwXsJsTYEc8Glwk0SyxOEI3JJZoPhB+hveOaJ kaYPqK8sj6ldpxjmPAdwoPwj5AzmrXAoGrs0MYUqAX66HZQnIf5R+MGBq w==; X-CSE-ConnectionGUID: 77yensJcTuWYwwxJxZQWog== X-CSE-MsgGUID: bPUBkxt8SMucTYk5sVQliQ== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951521" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951521" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:16 -0700 X-CSE-ConnectionGUID: 5538bF8cQuK0PyjURZVbzw== X-CSE-MsgGUID: ULCma+pASkq8u6PQTKbfmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918422" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:40:12 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests patch v2 6/7] x86: pmu_pebs: Remove abundant data_cfg_match calculation Date: Fri, 18 Jul 2025 09:39:14 +0800 Message-Id: <20250718013915.227452-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove abundant data_cfg_match calculation. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu_pebs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 6e73fc34..2848cc1e 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -296,7 +296,6 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size =3D pebs_rec->format_size >> RECORD_SIZE_OFFSET; pebs_idx_match =3D pebs_rec->applicable_counters & bitmask; pebs_size_match =3D pebs_record_size =3D=3D get_pebs_record_size(pebs_da= ta_cfg, use_adaptive); - data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D p= ebs_data_cfg; data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D (use_adaptive ? pebs_data_cfg : 0); expected =3D pebs_idx_match && pebs_size_match && data_cfg_match; --=20 2.34.1 From nobody Mon Oct 6 19:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19DE61EDA03; Fri, 18 Jul 2025 01:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802820; cv=none; b=UugzM6zK4NVpOHXzXDvA04UXcraV3/Mt8K5KNSZWaxNGoCfyVYxRATi7aQqhoVtx8WnxFIy+/VSnAZ1MxcOMPTmpI0n17WnMtIma+oHrrnEeXu22kYSTrqagJom6OjPuF96zQcroJZii6+N2ENzCM4/eNhZHMET0R5y5wQbpYiQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752802820; c=relaxed/simple; bh=0hNsv9KESme0CC07v7qNNGShOQXUwWV1Ff+LbnZiLcI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ku+YRdyd6/VRwfbQBZTzlrYalP6uuYYA9BJHyZo5cjH14582sAATQhYVbftsttcKsVOLm/sEOwmFz8Cb02WXdHrlWFmwqL90YNYNyHSJxUa0iUgheu3lOG1K1v5wEhzZcXnfcOr1s+5ONDN++5pyxrVGLcGXtzMG0zuRKFQ8Jgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HPA4GaZ9; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HPA4GaZ9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752802820; x=1784338820; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0hNsv9KESme0CC07v7qNNGShOQXUwWV1Ff+LbnZiLcI=; b=HPA4GaZ9bcleXb/R66S5GTCzhyMb9E5d7FhU8XJLd0dcxmmzHmHfzGbp vLk3R0YMhMaTnkUQY2NZ7mLWuuG8m9kLQEsWhz2/DLdu5Ff3ORGlYdF5/ UXE22qwpP7MAdCBXzgGC2vGoWNQB4TVXJ048Px9zkuwyPGH+CSd5w4laL 9MUFC+ewIdhbEtMXcd9M//x4XP9fJEh6lGkuq54thQr27vnQutJcnI/W2 XvvUT3lljFepVFe1yzTr5JJYwpOp42Ol8GuVFHgavqQtX+E7+/Uu18H8W K/4GCsK7ug7O+aLIyPZSnQGDOlBOJXyD+O8Q/Cc8mHUKTGNIZSxb7M+5o A==; X-CSE-ConnectionGUID: FUGX8D11SY2EXSzZUcbJDA== X-CSE-MsgGUID: lezntrBPQE+ZYAVEqxaeew== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="54951531" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="54951531" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 18:40:19 -0700 X-CSE-ConnectionGUID: GuyVw/LERkaYaxvH1lFrmQ== X-CSE-MsgGUID: c4oOsBp/Tm6eklQ9uvmY+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="188918429" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 17 Jul 2025 18:40:15 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Xiaoyao Li , Dapeng Mi , Dapeng Mi , Kan Liang Subject: [kvm-unit-tests patch v2 7/7] x86: pmu_pebs: Support to validate timed PEBS record on GNR/SRF Date: Fri, 18 Jul 2025 09:39:15 +0800 Message-Id: <20250718013915.227452-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> References: <20250718013915.227452-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Intel GNR/SRF platform, timed PEBS is introduced. Timed PEBS adds a new "retired latency" field in basic info group to show the timing info. IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to indicate whether timed PEBS is supported. After introducing timed PEBS, the PEBS record format field shrinks to bits[31:0] and the bits[47:32] is used to record retired latency. Thus shrink the record format to bits[31:0] accordingly and avoid the retired latency field is recognized a part of record format to compare and cause failure on GNR/SRF. Please find detailed information about timed PEBS in section 8.4.1 "Timed Processor Event Based Sampling" of "Intel Architecture Instruction Set Extensions and Future Features". Reviewed-by: Kan Liang Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- lib/x86/pmu.h | 6 ++++++ x86/pmu_pebs.c | 8 +++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h index c7dc68c1..86a7a05f 100644 --- a/lib/x86/pmu.h +++ b/lib/x86/pmu.h @@ -20,6 +20,7 @@ #define PMU_CAP_LBR_FMT 0x3f #define PMU_CAP_FW_WRITES (1ULL << 13) #define PMU_CAP_PEBS_BASELINE (1ULL << 14) +#define PMU_CAP_PEBS_TIMING_INFO (1ULL << 17) #define PERF_CAP_PEBS_FORMAT 0xf00 =20 #define EVNSEL_EVENT_SHIFT 0 @@ -188,4 +189,9 @@ static inline bool pmu_has_pebs_baseline(void) return pmu.perf_cap & PMU_CAP_PEBS_BASELINE; } =20 +static inline bool pmu_has_pebs_timing_info(void) +{ + return pmu.perf_cap & PMU_CAP_PEBS_TIMING_INFO; +} + #endif /* _X86_PMU_H_ */ diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 2848cc1e..bc37e8e3 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -277,6 +277,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive unsigned int count =3D 0; bool expected, pebs_idx_match, pebs_size_match, data_cfg_match; void *cur_record; + u64 format_mask; =20 expected =3D (ds->pebs_index =3D=3D ds->pebs_buffer_base) && !pebs_rec->f= ormat_size; if (!(rdmsr(MSR_CORE_PERF_GLOBAL_STATUS) & GLOBAL_STATUS_BUFFER_OVF)) { @@ -289,6 +290,8 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive return; } =20 + /* Record format shrinks to bits[31:0] after timed PEBS is introduced. */ + format_mask =3D pmu_has_pebs_timing_info() ? GENMASK_ULL(31, 0) : GENMASK= _ULL(47, 0); expected =3D ds->pebs_index >=3D ds->pebs_interrupt_threshold; cur_record =3D (void *)pebs_buffer; do { @@ -296,8 +299,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size =3D pebs_rec->format_size >> RECORD_SIZE_OFFSET; pebs_idx_match =3D pebs_rec->applicable_counters & bitmask; pebs_size_match =3D pebs_record_size =3D=3D get_pebs_record_size(pebs_da= ta_cfg, use_adaptive); - data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D - (use_adaptive ? pebs_data_cfg : 0); + data_cfg_match =3D (pebs_rec->format_size & format_mask) =3D=3D (use_ada= ptive ? pebs_data_cfg : 0); expected =3D pebs_idx_match && pebs_size_match && data_cfg_match; report(expected, "PEBS record (written seq %d) is verified (including size, counte= rs and cfg).", count); @@ -327,7 +329,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size, get_pebs_record_size(pebs_data_cfg, use_adapti= ve)); if (!data_cfg_match) printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with the effectiv= e MSR_PEBS_DATA_CFG (0x%lx).\n", - pebs_rec->format_size & 0xffffffffffff, use_adaptive ? pebs_data= _cfg : 0); + pebs_rec->format_size & format_mask, use_adaptive ? pebs_data_cf= g : 0); } } =20 --=20 2.34.1