From nobody Mon Oct 6 19:09:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D576D517; Fri, 18 Jul 2025 00:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752797999; cv=none; b=eaUhyip1Ioy5jghKT1bKtSC6yIeOnP+I7UbUp8IXNcHSgEqFaiJiclqPh7fvxi5YsQ382GgeTZKqy2IDVMDVG2kecRRFct9ziL7nFqhgCK/eL4mTa32cq4EqBXyPcBuW8/mHsUA4PhcIaEr2nlEYApNJcSjS9xlUI92dXFXSHvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752797999; c=relaxed/simple; bh=0JWpwbk6iPo/36WokS/MZjm06ctYIHkLbqOLqgjG0V4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cn6rx0nc8orLWO04tQEc57HzWKggaizQmaHfcR9GPLi/HOrIjT+9QmYNH+utE/w0J/HLe3ZUeUyVYN4I1VzDcPpgL6+Df6yO9X7PaSrHILYDls6SUT4ban6M4Qx5WEnlKP2R1+AqdANsvCrBv7PBIMBVrSG0zBbnlWBzWwoCsd4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=P0g1dfol; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P0g1dfol" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752797998; x=1784333998; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0JWpwbk6iPo/36WokS/MZjm06ctYIHkLbqOLqgjG0V4=; b=P0g1dfolfRIHsSxtnfIg7c/ImAgwwaDGoHFlsuacZE0gyUP1pS6YpQ/w mmZuHplA+WtAs9NPE0nMfj9vH7u42cG8jGdAbzVLNseVHc4XVijmIbOd+ qOunF9gmmEvWL3Y5a8jmPmFthdDIrM4KQn6HhclkBZbNlKFIRZ3QKkrLY yWaIyOOD3oCMhZTbH7Eh4TUpymDu4qsm8RD2JPLn1pv7qG0y8TnjZLP/n ACUrTBB6MXXIAEKN7sybFMMcvT4R7skoTSxK7dySbSMNtuDCnrutJebEY eem9m2AytrqlITkHbvmCnToobR3qAt4SujLh9Ai7evLydCWZ1Kh5+3PL+ Q==; X-CSE-ConnectionGUID: aLyrOix9TqSktNlxqXmyyw== X-CSE-MsgGUID: YKThnbbtTuKyW9MU9uiOaw== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="65780096" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="65780096" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 17:19:58 -0700 X-CSE-ConnectionGUID: Nh2+QS2uSa2Zj85Wv8LHUQ== X-CSE-MsgGUID: Q01DgBdLRRqJL6/EDYi8JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="157322787" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa010.jf.intel.com with ESMTP; 17 Jul 2025 17:19:54 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , Dapeng Mi Subject: [PATCH v2 1/5] KVM: x86/pmu: Correct typo "_COUTNERS" to "_COUNTERS" Date: Fri, 18 Jul 2025 08:19:01 +0800 Message-Id: <20250718001905.196989-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718001905.196989-1-dapeng1.mi@linux.intel.com> References: <20250718001905.196989-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix typos. "_COUTNERS" -> "_COUNTERS". Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- arch/x86/include/asm/kvm_host.h | 8 ++++---- arch/x86/kvm/vmx/pmu_intel.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 46ad65a4d524..0a8010e2859c 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -545,10 +545,10 @@ struct kvm_pmc { #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ KVM_MAX_NR_AMD_GP_COUNTERS) =20 -#define KVM_MAX_NR_INTEL_FIXED_COUTNERS 3 -#define KVM_MAX_NR_AMD_FIXED_COUTNERS 0 -#define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUTNERS,= \ - KVM_MAX_NR_AMD_FIXED_COUTNERS) +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 +#define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 +#define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS,= \ + KVM_MAX_NR_AMD_FIXED_COUNTERS) =20 struct kvm_pmu { u8 version; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 0b173602821b..e8b37a38fbba 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -478,8 +478,8 @@ static __always_inline u64 intel_get_fixed_pmc_eventsel= (unsigned int index) }; u64 eventsel; =20 - BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) !=3D KVM_MAX_NR_INTEL_FIXED_C= OUTNERS); - BUILD_BUG_ON(index >=3D KVM_MAX_NR_INTEL_FIXED_COUTNERS); + BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) !=3D KVM_MAX_NR_INTEL_FIXED_C= OUNTERS); + BUILD_BUG_ON(index >=3D KVM_MAX_NR_INTEL_FIXED_COUNTERS); =20 /* * Yell if perf reports support for a fixed counter but perf doesn't @@ -625,7 +625,7 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) pmu->gp_counters[i].current_config =3D 0; } =20 - for (i =3D 0; i < KVM_MAX_NR_INTEL_FIXED_COUTNERS; i++) { + for (i =3D 0; i < KVM_MAX_NR_INTEL_FIXED_COUNTERS; i++) { pmu->fixed_counters[i].type =3D KVM_PMC_FIXED; pmu->fixed_counters[i].vcpu =3D vcpu; pmu->fixed_counters[i].idx =3D i + KVM_FIXED_PMC_BASE_IDX; --=20 2.34.1 From nobody Mon Oct 6 19:09:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 797CB135A53; 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charset="utf-8" A new bit PERF_CAPABILITIES[17] called "PEBS_TIMING_INFO" bit is added to indicated if PEBS supports to record timing information in a new "Retried Latency" field. Since KVM requires user can only set host consistent PEBS capabilities, otherwise the PERF_CAPABILITIES setting would fail, so add pebs_timing_info bit into "immutable_caps" to block host inconsistent PEBS configuration and cause errors. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c b/tools/te= sting/selftests/kvm/x86/vmx_pmu_caps_test.c index a1f5ff45d518..f8deea220156 100644 --- a/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c @@ -29,7 +29,7 @@ static union perf_capabilities { u64 pebs_baseline:1; u64 perf_metrics:1; u64 pebs_output_pt_available:1; - u64 anythread_deprecated:1; + u64 pebs_timing_info:1; }; u64 capabilities; } host_cap; @@ -44,6 +44,7 @@ static const union perf_capabilities immutable_caps =3D { .pebs_arch_reg =3D 1, .pebs_format =3D -1, .pebs_baseline =3D 1, + .pebs_timing_info =3D 1, }; =20 static const union perf_capabilities format_caps =3D { --=20 2.34.1 From nobody Mon Oct 6 19:09:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C63615E5C2; Fri, 18 Jul 2025 00:20:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752798006; cv=none; b=SopUjgfv3sbj1i31o1xqsGQJ4QzNaT0b2WseyhyndAwu53qCKXSibaUhcOL4ckg2cMFzUkUFlJtMS7C7oCJjT3XfyA4Y3BB2DrNFUHrE8cK6jhORw/3boyubr+rhHIpd3JsCnGGUzZCMtdAbhrniMDau9mcFyetsenHPmvAu7MA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752798006; c=relaxed/simple; bh=pq5KmQTQkWLz3nOKP1PmprywftNpkHCQyc5neVjmIJE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VIzezhEwLcF+qrR9GTEk3s8SU+Bdd54T+HbM+5h5dnPkhASIFGUaLkTPHhM7yTZifQJKsM74t6yqFPlz3QtEVWGOx3DljQHj6mxBKOeob0L9Yt3eDFNMy+zdbqjanbX6TPSzgH/rVHulMOfBfTos5y250NieS+z5B2ihOwDdmOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dYs3P3/V; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dYs3P3/V" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752798005; x=1784334005; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pq5KmQTQkWLz3nOKP1PmprywftNpkHCQyc5neVjmIJE=; b=dYs3P3/V8zGnsdOFZTxiVDlRpFAgiEXt4Z6ZOnmNDDMq11RqfljqpY72 mNgQuW84uQFWbX4aPPILg7mHVTn8z0GbSJShpOol+ChrYjLGX1gaqBbXe sI6u9MGyhVR6R3btEp9hSanCTgfGM0dVVNKFe55a9vfSE/hY2qZLcbijb 9HJT/eMzFoYqAvQK5QhVB6+h2mvFP/0Ojh2wxcuUe4g5dGuPcH8+IkXR9 1f+9nt4kdroIjD3u0ZRAq/IUvKaSZ7hM6ZWjVu9xopmIyJzB6D5qEt7y+ 6Zi7zTNbRV9ggNZboGhfcK8m6yHQQJU/8JabrKdNkhQRwurAoVgndGQRr w==; X-CSE-ConnectionGUID: ciJOsTohTOO5YjapGVVlfw== X-CSE-MsgGUID: SRgifgsBT9ClgV/wtCLb7w== X-IronPort-AV: E=McAfee;i="6800,10657,11495"; a="65780112" X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="65780112" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 17:20:04 -0700 X-CSE-ConnectionGUID: cp03+UbEQ9W1wafmTZI5fw== X-CSE-MsgGUID: faRePdPfTKSnaE7Wfxpfyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,320,1744095600"; d="scan'208";a="157322854" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa010.jf.intel.com with ESMTP; 17 Jul 2025 17:20:00 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , Dapeng Mi Subject: [PATCH v2 3/5] KVM: Selftests: Validate more arch-events in pmu_counters_test Date: Fri, 18 Jul 2025 08:19:03 +0800 Message-Id: <20250718001905.196989-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718001905.196989-1-dapeng1.mi@linux.intel.com> References: <20250718001905.196989-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Clearwater Forest introduces 5 new architectural events (4 topdown level 1 metrics events and LBR inserts event). This patch supports to validate these 5 newly added events. The detailed info about these 5 events can be found in SDM section 21.2.7 "Pre-defined Architectural Performance Events". It becomes unrealistic to traverse all possible combinations of unavailable events mask (may need dozens of minutes to finish all possible combination validation). So only limit unavailable events mask traverse to the first 8 arch-events. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- tools/testing/selftests/kvm/include/x86/pmu.h | 10 +++++++++ .../selftests/kvm/include/x86/processor.h | 7 +++++- tools/testing/selftests/kvm/lib/x86/pmu.c | 5 +++++ .../selftests/kvm/x86/pmu_counters_test.c | 22 ++++++++++++++----- 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/= selftests/kvm/include/x86/pmu.h index 3c10c4dc0ae8..2aabda2da002 100644 --- a/tools/testing/selftests/kvm/include/x86/pmu.h +++ b/tools/testing/selftests/kvm/include/x86/pmu.h @@ -61,6 +61,11 @@ #define INTEL_ARCH_BRANCHES_RETIRED RAW_EVENT(0xc4, 0x00) #define INTEL_ARCH_BRANCHES_MISPREDICTED RAW_EVENT(0xc5, 0x00) #define INTEL_ARCH_TOPDOWN_SLOTS RAW_EVENT(0xa4, 0x01) +#define INTEL_ARCH_TOPDOWN_BE_BOUND RAW_EVENT(0xa4, 0x02) +#define INTEL_ARCH_TOPDOWN_BAD_SPEC RAW_EVENT(0x73, 0x00) +#define INTEL_ARCH_TOPDOWN_FE_BOUND RAW_EVENT(0x9c, 0x01) +#define INTEL_ARCH_TOPDOWN_RETIRING RAW_EVENT(0xc2, 0x02) +#define INTEL_ARCH_LBR_INSERTS RAW_EVENT(0xe4, 0x01) =20 #define AMD_ZEN_CORE_CYCLES RAW_EVENT(0x76, 0x00) #define AMD_ZEN_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00) @@ -80,6 +85,11 @@ enum intel_pmu_architectural_events { INTEL_ARCH_BRANCHES_RETIRED_INDEX, INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX, INTEL_ARCH_TOPDOWN_SLOTS_INDEX, + INTEL_ARCH_TOPDOWN_BE_BOUND_INDEX, + INTEL_ARCH_TOPDOWN_BAD_SPEC_INDEX, + INTEL_ARCH_TOPDOWN_FE_BOUND_INDEX, + INTEL_ARCH_TOPDOWN_RETIRING_INDEX, + INTEL_ARCH_LBR_INSERTS_INDEX, NR_INTEL_ARCH_EVENTS, }; =20 diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 2efb05c2f2fb..232964f2a687 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -265,7 +265,7 @@ struct kvm_x86_cpu_property { #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX,= 8, 15) #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0= , EAX, 16, 23) #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0= , EAX, 24, 31) -#define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0,= 7) +#define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0,= 12) #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, = 0, ECX, 0, 31) #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, ED= X, 0, 4) #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa= , 0, EDX, 5, 12) @@ -332,6 +332,11 @@ struct kvm_x86_pmu_feature { #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) +#define X86_PMU_FEATURE_TOPDOWN_BE_BOUND KVM_X86_PMU_FEATURE(EBX, 8) +#define X86_PMU_FEATURE_TOPDOWN_BAD_SPEC KVM_X86_PMU_FEATURE(EBX, 9) +#define X86_PMU_FEATURE_TOPDOWN_FE_BOUND KVM_X86_PMU_FEATURE(EBX, 10) +#define X86_PMU_FEATURE_TOPDOWN_RETIRING KVM_X86_PMU_FEATURE(EBX, 11) +#define X86_PMU_FEATURE_LBR_INSERTS KVM_X86_PMU_FEATURE(EBX, 12) =20 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) diff --git a/tools/testing/selftests/kvm/lib/x86/pmu.c b/tools/testing/self= tests/kvm/lib/x86/pmu.c index f31f0427c17c..5ab44bf54773 100644 --- a/tools/testing/selftests/kvm/lib/x86/pmu.c +++ b/tools/testing/selftests/kvm/lib/x86/pmu.c @@ -19,6 +19,11 @@ const uint64_t intel_pmu_arch_events[] =3D { INTEL_ARCH_BRANCHES_RETIRED, INTEL_ARCH_BRANCHES_MISPREDICTED, INTEL_ARCH_TOPDOWN_SLOTS, + INTEL_ARCH_TOPDOWN_BE_BOUND, + INTEL_ARCH_TOPDOWN_BAD_SPEC, + INTEL_ARCH_TOPDOWN_FE_BOUND, + INTEL_ARCH_TOPDOWN_RETIRING, + INTEL_ARCH_LBR_INSERTS, }; kvm_static_assert(ARRAY_SIZE(intel_pmu_arch_events) =3D=3D NR_INTEL_ARCH_E= VENTS); =20 diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index 8aaaf25b6111..342a72420177 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -75,6 +75,11 @@ static struct kvm_intel_pmu_event intel_event_to_feature= (uint8_t idx) [INTEL_ARCH_BRANCHES_RETIRED_INDEX] =3D { X86_PMU_FEATURE_BRANCH_INSNS_= RETIRED, X86_PMU_FEATURE_NULL }, [INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] =3D { X86_PMU_FEATURE_BRANCHES_= MISPREDICTED, X86_PMU_FEATURE_NULL }, [INTEL_ARCH_TOPDOWN_SLOTS_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_SLOTS, X= 86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED }, + [INTEL_ARCH_TOPDOWN_BE_BOUND_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_BE_BO= UND, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_TOPDOWN_BAD_SPEC_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_BAD_S= PEC, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_TOPDOWN_FE_BOUND_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_FE_BO= UND, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_TOPDOWN_RETIRING_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_RETIR= ING, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_LBR_INSERTS_INDEX] =3D { X86_PMU_FEATURE_LBR_INSERTS, X86_= PMU_FEATURE_NULL }, }; =20 kvm_static_assert(ARRAY_SIZE(__intel_event_to_feature) =3D=3D NR_INTEL_AR= CH_EVENTS); @@ -171,9 +176,12 @@ static void guest_assert_event_count(uint8_t idx, uint= 32_t pmc, uint32_t pmc_msr fallthrough; case INTEL_ARCH_CPU_CYCLES_INDEX: case INTEL_ARCH_REFERENCE_CYCLES_INDEX: + case INTEL_ARCH_TOPDOWN_BE_BOUND_INDEX: + case INTEL_ARCH_TOPDOWN_FE_BOUND_INDEX: GUEST_ASSERT_NE(count, 0); break; case INTEL_ARCH_TOPDOWN_SLOTS_INDEX: + case INTEL_ARCH_TOPDOWN_RETIRING_INDEX: __GUEST_ASSERT(count >=3D NUM_INSNS_RETIRED, "Expected top-down slots >=3D %u, got count =3D %lu", NUM_INSNS_RETIRED, count); @@ -612,15 +620,19 @@ static void test_intel_counters(void) pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", v, perf_caps[i]); /* - * To keep the total runtime reasonable, test every - * possible non-zero, non-reserved bitmap combination - * only with the native PMU version and the full bit - * vector length. + * To keep the total runtime reasonable, especially after + * the total number of arch-events increasing to 13, It's + * impossible to test every possible non-zero, non-reserved + * bitmap combination. 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The detailed information can be found in the errata (section SRF7): https://edc.intel.com/content/www/us/en/design/products-and-solutions/proce= ssors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-cores-sp= ecification-update/errata-details/ For the Atom platforms before Sierra Forest (including Sierra Forest), Both 2 events "Instruction Retired" and "Branch Instruction Retired" would be overcounted on these certain instructions, but for Clearwater Forest only "Instruction Retired" event is overcounted on these instructions. As the overcount issue on VM-Exit/VM-Entry, it has no way to validate the precise count for these 2 events on these affected Atom platforms, so just relax the precise event count check for these 2 events on these Atom platforms. Signed-off-by: dongsheng Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- tools/testing/selftests/kvm/include/x86/pmu.h | 9 +++++ tools/testing/selftests/kvm/lib/x86/pmu.c | 38 +++++++++++++++++++ .../selftests/kvm/x86/pmu_counters_test.c | 17 ++++++++- 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/= selftests/kvm/include/x86/pmu.h index 2aabda2da002..db14c08abc59 100644 --- a/tools/testing/selftests/kvm/include/x86/pmu.h +++ b/tools/testing/selftests/kvm/include/x86/pmu.h @@ -104,4 +104,13 @@ enum amd_pmu_zen_events { extern const uint64_t intel_pmu_arch_events[]; extern const uint64_t amd_pmu_zen_events[]; =20 +/* + * Flags for "Instruction Retired" and "Branch Instruction Retired" + * overcount flaws. + */ +#define INST_RETIRED_OVERCOUNT BIT(0) +#define BR_RETIRED_OVERCOUNT BIT(1) + +extern uint32_t detect_inst_overcount_flags(void); + #endif /* SELFTEST_KVM_PMU_H */ diff --git a/tools/testing/selftests/kvm/lib/x86/pmu.c b/tools/testing/self= tests/kvm/lib/x86/pmu.c index 5ab44bf54773..fd4ed577c88f 100644 --- a/tools/testing/selftests/kvm/lib/x86/pmu.c +++ b/tools/testing/selftests/kvm/lib/x86/pmu.c @@ -8,6 +8,7 @@ #include =20 #include "kvm_util.h" +#include "processor.h" #include "pmu.h" =20 const uint64_t intel_pmu_arch_events[] =3D { @@ -34,3 +35,40 @@ const uint64_t amd_pmu_zen_events[] =3D { AMD_ZEN_BRANCHES_MISPREDICTED, }; kvm_static_assert(ARRAY_SIZE(amd_pmu_zen_events) =3D=3D NR_AMD_ZEN_EVENTS); + +/* + * For Intel Atom CPUs, the PMU events "Instruction Retired" or + * "Branch Instruction Retired" may be overcounted for some certain + * instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD + * and complex SGX/SMX/CSTATE instructions/flows. + * + * The detailed information can be found in the errata (section SRF7): + * https://edc.intel.com/content/www/us/en/design/products-and-solutions/p= rocessors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-core= s-specification-update/errata-details/ + * + * For the Atom platforms before Sierra Forest (including Sierra Forest), + * Both 2 events "Instruction Retired" and "Branch Instruction Retired" wo= uld + * be overcounted on these certain instructions, but for Clearwater Forest + * only "Instruction Retired" event is overcounted on these instructions. + */ +uint32_t detect_inst_overcount_flags(void) +{ + uint32_t eax, ebx, ecx, edx; + uint32_t flags =3D 0; + + cpuid(1, &eax, &ebx, &ecx, &edx); + if (x86_family(eax) =3D=3D 0x6) { + switch (x86_model(eax)) { + case 0xDD: /* Clearwater Forest */ + flags =3D INST_RETIRED_OVERCOUNT; + break; + case 0xAF: /* Sierra Forest */ + case 0x4D: /* Avaton, Rangely */ + case 0x5F: /* Denverton */ + case 0x86: /* Jacobsville */ + flags =3D INST_RETIRED_OVERCOUNT | BR_RETIRED_OVERCOUNT; + break; + } + } + + return flags; +} diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index 342a72420177..074cdf323406 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -52,6 +52,9 @@ struct kvm_intel_pmu_event { struct kvm_x86_pmu_feature fixed_event; }; =20 + +static uint8_t inst_overcount_flags; + /* * Wrap the array to appease the compiler, as the macros used to construct= each * kvm_x86_pmu_feature use syntax that's only valid in function scope, and= the @@ -163,10 +166,18 @@ static void guest_assert_event_count(uint8_t idx, uin= t32_t pmc, uint32_t pmc_msr =20 switch (idx) { case INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX: - GUEST_ASSERT_EQ(count, NUM_INSNS_RETIRED); + /* Relax precise count check due to VM-EXIT/VM-ENTRY overcount issue */ + if (inst_overcount_flags & INST_RETIRED_OVERCOUNT) + GUEST_ASSERT(count >=3D NUM_INSNS_RETIRED); + else + GUEST_ASSERT_EQ(count, NUM_INSNS_RETIRED); break; case INTEL_ARCH_BRANCHES_RETIRED_INDEX: - GUEST_ASSERT_EQ(count, NUM_BRANCH_INSNS_RETIRED); + /* Relax precise count check due to VM-EXIT/VM-ENTRY overcount issue */ + if (inst_overcount_flags & BR_RETIRED_OVERCOUNT) + GUEST_ASSERT(count >=3D NUM_BRANCH_INSNS_RETIRED); + else + GUEST_ASSERT_EQ(count, NUM_BRANCH_INSNS_RETIRED); break; case INTEL_ARCH_LLC_REFERENCES_INDEX: case INTEL_ARCH_LLC_MISSES_INDEX: @@ -335,6 +346,7 @@ static void test_arch_events(uint8_t pmu_version, uint6= 4_t perf_capabilities, length); vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EVENTS_MASK, unavailable_mask); + sync_global_to_guest(vm, inst_overcount_flags); =20 run_vcpu(vcpu); =20 @@ -673,6 +685,7 @@ int main(int argc, char *argv[]) =20 kvm_pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); 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17 Jul 2025 17:20:07 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , Dapeng Mi Subject: [PATCH v2 5/5] KVM: selftests: Relax branches event count check for event_filter test Date: Fri, 18 Jul 2025 08:19:05 +0800 Message-Id: <20250718001905.196989-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250718001905.196989-1-dapeng1.mi@linux.intel.com> References: <20250718001905.196989-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the branches event overcount issue on Atom platforms, once there are VM-Exits triggered (external interrupts) in the guest loop, the measured branch event count could be larger than NUM_BRANCHES, this would lead to the pmu_event_filter_test print warning to info the measured branches event count is mismatched with expected number (NUM_BRANCHES). To eliminate this warning, relax the branches event count check on the Atom platform which have the branches event overcount issue. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- tools/testing/selftests/kvm/x86/pmu_event_filter_test.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tool= s/testing/selftests/kvm/x86/pmu_event_filter_test.c index c15513cd74d1..9c1a92f05786 100644 --- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c @@ -60,6 +60,8 @@ struct { uint64_t instructions_retired; } pmc_results; =20 +static uint8_t inst_overcount_flags; + /* * If we encounter a #GP during the guest PMU sanity check, then the guest * PMU is not functional. Inform the hypervisor via GUEST_SYNC(0). @@ -214,8 +216,10 @@ static void remove_event(struct __kvm_pmu_event_filter= *f, uint64_t event) do { \ uint64_t br =3D pmc_results.branches_retired; \ uint64_t ir =3D pmc_results.instructions_retired; \ + bool br_matched =3D inst_overcount_flags & BR_RETIRED_OVERCOUNT ? \ + br >=3D NUM_BRANCHES : br =3D=3D NUM_BRANCHES; \ \ - if (br && br !=3D NUM_BRANCHES) \ + if (br && !br_matched) \ pr_info("%s: Branch instructions retired =3D %lu (expected %u)\n", \ __func__, br, NUM_BRANCHES); \ TEST_ASSERT(br, "%s: Branch instructions retired =3D %lu (expected > 0)",= \ @@ -850,6 +854,9 @@ int main(int argc, char *argv[]) if (use_amd_pmu()) test_amd_deny_list(vcpu); =20 + if (use_intel_pmu()) + inst_overcount_flags =3D detect_inst_overcount_flags(); + test_without_filter(vcpu); test_member_deny_list(vcpu); test_member_allow_list(vcpu); --=20 2.34.1