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QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 181 +++++++++++++++++++++++++++++++= +++- 1 file changed, 180 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 142338069a74cc6c263e17d84efa22ccd0c26813..24299430b195026e896c365d80a= 0036713f00d35 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3372,12 +3373,190 @@ camcc: clock-controller@ad00000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm6150-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_CORE_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm6150-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", "bus", "core", "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-25600000 { + opp-hz =3D /bits/ 64 <25600000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-164000000 { + opp-hz =3D /bits/ 64 <164000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sm6150-dsi-phy-14nm"; + reg =3D <0x0 0x0ae94400 0x0 0x100>, + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x188>; 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QCS615 has a DP port, and DP support will be added in a later patch. Signed-off-by: Li Liu Signed-off-by: Fange Zhang Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 90 ++++++++++++++++++++++++++++= ++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index a6652e4817d1c218c7981b04daeb035e2852ac1a..f41e0763170df40c5d10497049a= e74ab4aee4950 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -38,6 +38,18 @@ xo_board_clk: xo-board-clk { }; }; =20 + dp-dsi0-connector { + compatible =3D "dp-connector"; + label =3D "DSI0"; + type =3D "mini"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint =3D <&dsi2dp_bridge_out>; + }; + }; + }; + regulator-usb2-vbus { compatible =3D "regulator-fixed"; regulator-name =3D "USB2_VBUS"; @@ -217,6 +229,84 @@ &gcc { <&sleep_clk>; }; =20 +&i2c2 { + clock-frequency =3D <400000>; + status =3D "okay"; + + io_expander: gpio@3e { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3e>; + interrupts-extended =3D <&tlmm 58 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + semtech,probe-reset; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9542"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + bridge@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupts-extended =3D <&io_expander 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + wakeup-source; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi2dp_bridge_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi2dp_bridge_out: endpoint { + remote-endpoint =3D <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&dsi2dp_bridge_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + &pm8150_gpios { usb2_en: usb2-en-state { pins =3D "gpio10"; --=20 2.34.1