From nobody Mon Oct 6 21:00:49 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 123802367A9 for ; Thu, 17 Jul 2025 21:02:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752786167; cv=none; b=bvIMaE5+uFNzmzKo6qK9ykwtoZwcP+DbzbQenZhViIkTkyDenMVisdFx/DGB3Lfx9Y2QOh6W+QePEzu7pXIYc0kWtC9iSZhqXg/F6PFqFO003A5VysH2+lQhJCFDGfZm03yqYwGAiwZ4SpX9mvdaeRxPtaBL0lGAG9d4vCihquY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752786167; c=relaxed/simple; bh=3iqPS74Vm3U8TVu2LqxzGlONC7F3fEEx0C3HxO9oOX8=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Content-Type; b=gJ1uu1Vn5o8/Dot6iziRUqDfVb+g3A5o96qB9VSwvk58vx8Kykcmp0q11mZWyjRD3DHLBxTDfNjfS41GnswTL7pOY6COHCg1BZLCUVc2AvhyrBIJXTD068zThm9qB/ClhYnFQMxLPkaKe+BCDjjxYoQ4L15fl/G0Ng1Mzw/NAjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=iLmY1Eg5; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="iLmY1Eg5" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-236725af87fso19718715ad.3 for ; Thu, 17 Jul 2025 14:02:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1752786165; x=1753390965; darn=vger.kernel.org; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=TDJzHa5Jjh3EgodtOKHDgfY+ccZxVF0sXpFhOe3DuRk=; b=iLmY1Eg59iQ404M3s+t6O8sv7Pehl8V4yM24wXCEf0Gn+rYKic9f3HWwHkOXHKTJ4l VS4Ps/4EQ03OSuPpECW9QadFob8RIU8+O542c3T54ZtP6rgTD5G3wZQwfwg59vDYB4FQ X1jhFY5LbPrHYxfTv8J7OqThUROz/+xTy68yFxhkZbVTLwbI8+bVbUZ5UacIhNyExLe7 WqxD0KUVQQSwT7LumFaGLH90D+oJKAxXcESmCFMFOhFpdILRBbKueriTNB8epQKppwxa i5fgOxIxSotQuO3BB2YFVzQfaOpi1eL61lPj44iICzL4zdjftzFsF8Jmy6OEnxw2Q5zg D6XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752786165; x=1753390965; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=TDJzHa5Jjh3EgodtOKHDgfY+ccZxVF0sXpFhOe3DuRk=; b=fPgqB3YAH91za0gMDP0qKXigIt7gdzdNTB1IRhE7rHmTSBo66dRrY75UVQMNeF2iK2 7VWa1xTA7Zp0tBtxeBxDVgrgEm6rn/livZx9XKbHoUmMi5iy+AgPyHczBOraPMlkRorO O25PdsEdcG8iIOz+i7hwkEc4WDY+a41lBIre7kRkF0CmhzNGZwhBT7qAhGf5hVILrReC rkTXjwB0pbkav8d1YnLxcXnNbHWtWjQxFWnVrYEzF1ZrANiPd0cEU1vjUS9CBwlVYTpD 3y3plEgrvIorYUQ7C+Xrp1SNTGmmirC4ylg0cZUCF5XlsPPqz5UhkPmUcuXq7wf3f7xt thAw== X-Forwarded-Encrypted: i=1; AJvYcCULB8k6ZepsEzTMivJ5NROt+SdghysTI8gkh7BcqOUQ1C3CUj52MkPpptwPLM/nuPBnXnC7kBSWJtfN5/g=@vger.kernel.org X-Gm-Message-State: AOJu0YzBLQJw9v77EnSCGPdX9hOqgyegiksvpG9nylxiN3Alyb36AZwB JlFkt6WYFUeaKirIoK4iaV6D1ysc8VAMohbkVa3m96g/7YGOhTRFNXAQmsxq00F+GXQ+UKKeGii emvlluJokxQ== X-Google-Smtp-Source: AGHT+IFT0swixNXm9qdjS7EOMnt4hM5uFE2a5kg8QJcjgZGnBz12S1+iF2upqqz1KJ2dctapi//tVG7rYgTV X-Received: from plgy14.prod.google.com ([2002:a17:903:22ce:b0:237:ca39:8d92]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:3c2c:b0:234:c8f6:1b17 with SMTP id d9443c01a7336-23e3035f29bmr77170915ad.38.1752786165430; Thu, 17 Jul 2025 14:02:45 -0700 (PDT) Date: Thu, 17 Jul 2025 14:02:25 -0700 In-Reply-To: <20250717210233.1143622-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250717210233.1143622-1-irogers@google.com> X-Mailer: git-send-email 2.50.0.727.gbf7dc18ff4-goog Message-ID: <20250717210233.1143622-5-irogers@google.com> Subject: [PATCH v2 04/12] perf parse-events: Allow the cpu term to be a PMU or CPU range From: Ian Rogers To: Thomas Falcon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Ben Gainey , James Clark , Howard Chu , Weilin Wang , Levi Yun , "Dr. David Alan Gilbert" , Zhongqiu Han , Blake Jones , Yicong Yang , Anubhav Shelat , Thomas Richter , Jean-Philippe Romain , Song Liu , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On hybrid systems, events like msr/tsc/ will aggregate counts across all CPUs. Often metrics only want a value like msr/tsc/ for the cores on which the metric is being computed. Listing each CPU with terms cpu=3D0,cpu=3D1.. is laborious and would need to be encoded for all variations of a CPU model. Allow the cpumask from a PMU to be an argument to the cpu term. For example in the following the cpumask of the cstate_pkg PMU selects the CPUs to count msr/tsc/ counter upon: ``` $ cat /sys/bus/event_source/devices/cstate_pkg/cpumask 0 $ perf stat -A -e 'msr/tsc,cpu=3Dcstate_pkg/' -a sleep 0.1 Performance counter stats for 'system wide': CPU0 252,621,253 msr/tsc,cpu=3Dcstate_pkg/ 0.101184092 seconds time elapsed ``` As the cpu term is now also allowed to be a string, allow it to encode a range of CPUs (a list can't be supported as ',' is already a special token). The "event qualifiers" section of the `perf list` man page is updated to detail the additional behavior. The man page formatting is tidied up in this section, as it was incorrectly appearing within the "parameterized events" section. Reviewed-by: Thomas Falcon Signed-off-by: Ian Rogers --- tools/perf/Documentation/perf-list.txt | 25 +++++++++----- tools/perf/util/parse-events.c | 47 +++++++++++++++++++++----- 2 files changed, 54 insertions(+), 18 deletions(-) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentat= ion/perf-list.txt index ce0735021473..28215306a78a 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -278,26 +278,33 @@ also be supplied. For example: =20 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=3D0x2/' ... =20 -EVENT QUALIFIERS: +EVENT QUALIFIERS +---------------- =20 It is also possible to add extra qualifiers to an event: =20 percore: =20 -Sums up the event counts for all hardware threads in a core, e.g.: - - - perf stat -e cpu/event=3D0,umask=3D0x3,percore=3D1/ + Sums up the event counts for all hardware threads in a core, e.g.: + perf stat -e cpu/event=3D0,umask=3D0x3,percore=3D1/ =20 cpu: =20 -Specifies the CPU to open the event upon. The value may be repeated to -specify opening the event on multiple CPUs: + Specifies a CPU or a range of CPUs to open the event upon. It may + also reference a PMU to copy the CPU mask from. The value may be + repeated to specify opening the event on multiple CPUs. =20 + Example 1: to open the instructions event on CPUs 0 and 2, the + cycles event on CPUs 1 and 2: + perf stat -e instructions/cpu=3D0,cpu=3D2/,cycles/cpu=3D1-2/ -a sleep 1 =20 - perf stat -e instructions/cpu=3D0,cpu=3D2/,cycles/cpu=3D1,cpu=3D2/ -a sl= eep 1 - perf stat -e data_read/cpu=3D0/,data_write/cpu=3D1/ -a sleep 1 + Example 2: to open the data_read uncore event on CPU 0 and the + data_write uncore event on CPU 1: + perf stat -e data_read/cpu=3D0/,data_write/cpu=3D1/ -a sleep 1 =20 + Example 3: to open the software msr/tsc/ event only on the CPUs + matching those from the cpu_core PMU: + perf stat -e msr/tsc,cpu=3Dcpu_core/ -a sleep 1 =20 EVENT GROUPS ------------ diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 3fd6cc0c2794..a337e4d22ff2 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -187,10 +187,22 @@ static struct perf_cpu_map *get_config_cpu(const stru= ct parse_events_terms *head =20 list_for_each_entry(term, &head_terms->terms, list) { if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_CPU) { - struct perf_cpu_map *cpu =3D perf_cpu_map__new_int(term->val.num); - - perf_cpu_map__merge(&cpus, cpu); - perf_cpu_map__put(cpu); + struct perf_cpu_map *term_cpus; + + if (term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM) { + term_cpus =3D perf_cpu_map__new_int(term->val.num); + } else { + struct perf_pmu *pmu =3D perf_pmus__find(term->val.str); + + if (pmu && perf_cpu_map__is_empty(pmu->cpus)) + term_cpus =3D pmu->is_core ? cpu_map__online() : NULL; + else if (pmu) + term_cpus =3D perf_cpu_map__get(pmu->cpus); + else + term_cpus =3D perf_cpu_map__new(term->val.str); + } + perf_cpu_map__merge(&cpus, term_cpus); + perf_cpu_map__put(term_cpus); } } =20 @@ -1048,15 +1060,32 @@ do { \ return -EINVAL; } break; - case PARSE_EVENTS__TERM_TYPE_CPU: - CHECK_TYPE_VAL(NUM); - if (term->val.num >=3D (u64)cpu__max_present_cpu().cpu) { + case PARSE_EVENTS__TERM_TYPE_CPU: { + struct perf_cpu_map *map; + + if (term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM) { + if (term->val.num >=3D (u64)cpu__max_present_cpu().cpu) { + parse_events_error__handle(err, term->err_val, + strdup("too big"), + /*help=3D*/NULL); + return -EINVAL; + } + break; + } + assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_STR); + if (perf_pmus__find(term->val.str) !=3D NULL) + break; + + map =3D perf_cpu_map__new(term->val.str); + if (!map) { parse_events_error__handle(err, term->err_val, - strdup("too big"), - NULL); + strdup("not a valid PMU or CPU number"), + /*help=3D*/NULL); return -EINVAL; } + perf_cpu_map__put(map); break; + } case PARSE_EVENTS__TERM_TYPE_DRV_CFG: case PARSE_EVENTS__TERM_TYPE_USER: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: --=20 2.50.0.727.gbf7dc18ff4-goog