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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55943b61134sm3079983e87.162.2025.07.17.07.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 07:22:01 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Svyatoslav Ryhel , Dmitry Osipenko Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 1/5] dt-bindings: display: tegra: document MIPI calibration for Tegra20/Tegra30 Date: Thu, 17 Jul 2025 17:21:35 +0300 Message-ID: <20250717142139.57621-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250717142139.57621-1-clamor95@gmail.com> References: <20250717142139.57621-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adjust Tegra114 MIPI calibration schema to include Tegra20/Tegra30 MIPI calibration logic. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra114-mipi.yaml | 41 ++++++++++++++++--- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra11= 4-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra1= 14-mipi.yaml index 193ddb105283..ddf1b9fff085 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.= yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.= yaml @@ -16,6 +16,8 @@ properties: =20 compatible: enum: + - nvidia,tegra20-mipi + - nvidia,tegra30-mipi - nvidia,tegra114-mipi - nvidia,tegra124-mipi - nvidia,tegra210-mipi @@ -25,12 +27,12 @@ properties: maxItems: 1 =20 clocks: - items: - - description: module clock + minItems: 1 + maxItems: 2 =20 clock-names: - items: - - const: mipi-cal + minItems: 1 + maxItems: 2 =20 power-domains: maxItems: 1 @@ -42,7 +44,36 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 const: 1 =20 -additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-dsi + - nvidia,tegra30-dsi + then: + properties: + clocks: + items: + - description: VI module clock + - description: CSI module clock + + clock-names: + items: + - const: vi + - const: csi + else: + properties: + clocks: + items: + - description: module clock + + clock-names: + items: + - const: mipi-cal + +unevaluatedProperties: false =20 required: - compatible --=20 2.48.1 From nobody Mon Oct 6 18:56:28 2025 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCCDD2F7CF1; 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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55943b61134sm3079983e87.162.2025.07.17.07.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 07:22:03 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Svyatoslav Ryhel , Dmitry Osipenko Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 2/5] clk: tegra20: reparent dsi clock to pll_d_out0 Date: Thu, 17 Jul 2025 17:21:36 +0300 Message-ID: <20250717142139.57621-3-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250717142139.57621-1-clamor95@gmail.com> References: <20250717142139.57621-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra20.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra2= 0.c index 2c58ce25af75..551ef0cf0c9a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -802,9 +802,8 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_MC] =3D clk; =20 /* dsi */ - clk =3D tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, - 48, periph_clk_enb_refcnt); - clk_register_clkdev(clk, NULL, "dsi"); + clk =3D tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0, clk_base, + 0, 48, periph_clk_enb_refcnt); clks[TEGRA20_CLK_DSI] =3D clk; =20 /* pex */ --=20 2.48.1 From nobody Mon Oct 6 18:56:28 2025 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 501082F7D15; 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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55943b61134sm3079983e87.162.2025.07.17.07.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 07:22:04 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Svyatoslav Ryhel , Dmitry Osipenko Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 3/5] gpu/drm: host1x: mipi: add Tegra20/Tegra30 MIPI calibration logic Date: Thu, 17 Jul 2025 17:21:37 +0300 Message-ID: <20250717142139.57621-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250717142139.57621-1-clamor95@gmail.com> References: <20250717142139.57621-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra20/Tegra30 have no dedicated MIPI calibration device and calibration registers are incorporated into CSI. Lets reuse Tegra114 calibration framework and add Tegra20/Tegra30 as a special case. Signed-off-by: Svyatoslav Ryhel --- drivers/gpu/host1x/mipi.c | 82 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index e51b43dd15a3..cfaa27e0f892 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -61,6 +61,13 @@ #define MIPI_CAL_CONFIG_DSID_CLK 0x1d #define MIPI_CAL_CONFIG_CSIE_CLK 0x1d =20 +/* DSI V0 controller */ +#define CSI_CIL_PAD_CONFIG 0x09 +#define CSI_CILA_MIPI_CAL_CONFIG 0x0a +#define CSI_CILB_MIPI_CAL_CONFIG 0x0b +#define CSI_DSI_MIPI_CAL_CONFIG 0x14 +#define CSI_MIPIBIAS_PAD_CONFIG 0x15 + /* for data and clock lanes */ #define MIPI_CAL_CONFIG_SELECT (1 << 21) =20 @@ -92,6 +99,8 @@ struct tegra_mipi_pad { }; =20 struct tegra_mipi_soc { + bool dsi_v0; + bool has_clk_lane; const struct tegra_mipi_pad *pads; unsigned int num_pads; @@ -122,6 +131,7 @@ struct tegra_mipi { void __iomem *regs; struct mutex lock; struct clk *clk; + struct clk *csi_clk; =20 unsigned long usage_count; }; @@ -265,6 +275,9 @@ int tegra_mipi_enable(struct tegra_mipi_device *dev) { int err =3D 0; =20 + if (dev->mipi->soc->dsi_v0) + return 0; + mutex_lock(&dev->mipi->lock); =20 if (dev->mipi->usage_count++ =3D=3D 0) @@ -281,6 +294,9 @@ int tegra_mipi_disable(struct tegra_mipi_device *dev) { int err =3D 0; =20 + if (dev->mipi->soc->dsi_v0) + return 0; + mutex_lock(&dev->mipi->lock); =20 if (--dev->mipi->usage_count =3D=3D 0) @@ -300,6 +316,9 @@ int tegra_mipi_finish_calibration(struct tegra_mipi_dev= ice *device) u32 value; int err; =20 + if (mipi->soc->dsi_v0) + return 0; + err =3D readl_relaxed_poll_timeout(status_reg, value, !(value & MIPI_CAL_STATUS_ACTIVE) && (value & MIPI_CAL_STATUS_DONE), 50, @@ -311,6 +330,43 @@ int tegra_mipi_finish_calibration(struct tegra_mipi_de= vice *device) } EXPORT_SYMBOL(tegra_mipi_finish_calibration); =20 +static int tegra20_mipi_calibration(struct tegra_mipi_device *device) +{ + struct tegra_mipi *mipi =3D device->mipi; + const struct tegra_mipi_soc *soc =3D mipi->soc; + u32 value; + int err; + + err =3D clk_enable(mipi->csi_clk); + if (err < 0) + return err; + + mutex_lock(&mipi->lock); + + value =3D MIPI_CAL_CONFIG_TERMOS(soc->termos); + tegra_mipi_writel(mipi, value, CSI_CILA_MIPI_CAL_CONFIG); + + value =3D MIPI_CAL_CONFIG_TERMOS(soc->termos); + tegra_mipi_writel(mipi, value, CSI_CILB_MIPI_CAL_CONFIG); + + value =3D MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) | + MIPI_CAL_CONFIG_HSPUOS(soc->hspuos); + tegra_mipi_writel(mipi, value, CSI_DSI_MIPI_CAL_CONFIG); + + value =3D MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) | + MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref); + tegra_mipi_writel(mipi, value, CSI_MIPIBIAS_PAD_CONFIG); + + tegra_mipi_writel(mipi, 0x0, CSI_CIL_PAD_CONFIG); + + mutex_unlock(&mipi->lock); + + clk_disable(mipi->csi_clk); + clk_disable(mipi->clk); + + return 0; +} + int tegra_mipi_start_calibration(struct tegra_mipi_device *device) { const struct tegra_mipi_soc *soc =3D device->mipi->soc; @@ -322,6 +378,9 @@ int tegra_mipi_start_calibration(struct tegra_mipi_devi= ce *device) if (err < 0) return err; =20 + if (soc->dsi_v0) + return tegra20_mipi_calibration(device); + mutex_lock(&device->mipi->lock); =20 value =3D MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) | @@ -386,6 +445,15 @@ int tegra_mipi_start_calibration(struct tegra_mipi_dev= ice *device) } EXPORT_SYMBOL(tegra_mipi_start_calibration); =20 +static const struct tegra_mipi_soc tegra20_mipi_soc =3D { + .dsi_v0 =3D true, + .pad_drive_down_ref =3D 0x5, + .pad_drive_up_ref =3D 0x7, + .hspdos =3D 0x4, + .hspuos =3D 0x3, + .termos =3D 0x4, +}; + static const struct tegra_mipi_pad tegra114_mipi_pads[] =3D { { .data =3D MIPI_CAL_CONFIG_CSIA }, { .data =3D MIPI_CAL_CONFIG_CSIB }, @@ -399,6 +467,7 @@ static const struct tegra_mipi_pad tegra114_mipi_pads[]= =3D { }; =20 static const struct tegra_mipi_soc tegra114_mipi_soc =3D { + .dsi_v0 =3D false, .has_clk_lane =3D false, .pads =3D tegra114_mipi_pads, .num_pads =3D ARRAY_SIZE(tegra114_mipi_pads), @@ -426,6 +495,7 @@ static const struct tegra_mipi_pad tegra124_mipi_pads[]= =3D { }; =20 static const struct tegra_mipi_soc tegra124_mipi_soc =3D { + .dsi_v0 =3D false, .has_clk_lane =3D true, .pads =3D tegra124_mipi_pads, .num_pads =3D ARRAY_SIZE(tegra124_mipi_pads), @@ -443,6 +513,7 @@ static const struct tegra_mipi_soc tegra124_mipi_soc = =3D { }; =20 static const struct tegra_mipi_soc tegra132_mipi_soc =3D { + .dsi_v0 =3D false, .has_clk_lane =3D true, .pads =3D tegra124_mipi_pads, .num_pads =3D ARRAY_SIZE(tegra124_mipi_pads), @@ -473,6 +544,7 @@ static const struct tegra_mipi_pad tegra210_mipi_pads[]= =3D { }; =20 static const struct tegra_mipi_soc tegra210_mipi_soc =3D { + .dsi_v0 =3D false, .has_clk_lane =3D true, .pads =3D tegra210_mipi_pads, .num_pads =3D ARRAY_SIZE(tegra210_mipi_pads), @@ -490,6 +562,8 @@ static const struct tegra_mipi_soc tegra210_mipi_soc = =3D { }; =20 static const struct of_device_id tegra_mipi_of_match[] =3D { + { .compatible =3D "nvidia,tegra20-mipi", .data =3D &tegra20_mipi_soc }, + { .compatible =3D "nvidia,tegra30-mipi", .data =3D &tegra20_mipi_soc }, { .compatible =3D "nvidia,tegra114-mipi", .data =3D &tegra114_mipi_soc }, { .compatible =3D "nvidia,tegra124-mipi", .data =3D &tegra124_mipi_soc }, { .compatible =3D "nvidia,tegra132-mipi", .data =3D &tegra132_mipi_soc }, @@ -525,6 +599,14 @@ static int tegra_mipi_probe(struct platform_device *pd= ev) return PTR_ERR(mipi->clk); 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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55943b61134sm3079983e87.162.2025.07.17.07.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 07:22:06 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Svyatoslav Ryhel , Dmitry Osipenko Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 4/5] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30 Date: Thu, 17 Jul 2025 17:21:38 +0300 Message-ID: <20250717142139.57621-5-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250717142139.57621-1-clamor95@gmail.com> References: <20250717142139.57621-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra20/Tegra30 are fully compatible with existing tegra DSI driver apart clock configuration and MIPI calibration which are addressed by this patch. Signed-off-by: Svyatoslav Ryhel --- drivers/gpu/drm/tegra/drm.c | 2 ++ drivers/gpu/drm/tegra/dsi.c | 69 ++++++++++++++++++++++--------------- drivers/gpu/drm/tegra/dsi.h | 10 ++++++ 3 files changed, 54 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 4596073fe28f..5d64cd57e764 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_= drm_suspend, =20 static const struct of_device_id host1x_drm_subdevs[] =3D { { .compatible =3D "nvidia,tegra20-dc", }, + { .compatible =3D "nvidia,tegra20-dsi", }, { .compatible =3D "nvidia,tegra20-hdmi", }, { .compatible =3D "nvidia,tegra20-gr2d", }, { .compatible =3D "nvidia,tegra20-gr3d", }, { .compatible =3D "nvidia,tegra30-dc", }, + { .compatible =3D "nvidia,tegra30-dsi", }, { .compatible =3D "nvidia,tegra30-hdmi", }, { .compatible =3D "nvidia,tegra30-gr2d", }, { .compatible =3D "nvidia,tegra30-gr3d", }, diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 3f91a24ebef2..85bcb8bee1ae 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -662,39 +662,48 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) { u32 value; =20 - value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + /* Tegra20/30 uses DSIv0 while Tegra114+ uses DSIv1 */ + if (of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra20-dsi") || + of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra30-dsi")) { + value =3D DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) | + DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) | + DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) | + DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + } else { + /* + * XXX Is this still needed? The module reset is deasserted right + * before this function is called. + */ + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); + + value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + + value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | + DSI_PAD_OUT_CLK(0x0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); + + value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | + DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); + } =20 return 0; } =20 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { - u32 value; int err; =20 - /* - * XXX Is this still needed? The module reset is deasserted right - * before this function is called. - */ - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); - /* start calibration */ tegra_dsi_pad_enable(dsi); =20 - value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | - DSI_PAD_OUT_CLK(0x0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); - - value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | - DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - err =3D tegra_mipi_start_calibration(dsi->mipi); if (err < 0) return err; @@ -1615,7 +1624,7 @@ static int tegra_dsi_probe(struct platform_device *pd= ev) goto remove; } =20 - dsi->clk_lp =3D devm_clk_get(&pdev->dev, "lp"); + dsi->clk_lp =3D devm_clk_get_optional(&pdev->dev, "lp"); if (IS_ERR(dsi->clk_lp)) { err =3D dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), "cannot get low-power clock\n"); @@ -1636,10 +1645,14 @@ static int tegra_dsi_probe(struct platform_device *= pdev) goto remove; } =20 - err =3D tegra_dsi_setup_clocks(dsi); - if (err < 0) { - dev_err(&pdev->dev, "cannot setup clocks\n"); - goto remove; + /* Tegra20/Tegra30 do not use DSI parent muxing */ + if (!of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra20-dsi") && + !of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra30-dsi")) { + err =3D tegra_dsi_setup_clocks(dsi); + if (err < 0) { + dev_err(&pdev->dev, "cannot setup clocks\n"); + return err; + } } =20 regs =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1709,6 +1722,8 @@ static const struct of_device_id tegra_dsi_of_match[]= =3D { { .compatible =3D "nvidia,tegra132-dsi", }, { .compatible =3D "nvidia,tegra124-dsi", }, { .compatible =3D "nvidia,tegra114-dsi", }, + { .compatible =3D "nvidia,tegra30-dsi", }, + { .compatible =3D "nvidia,tegra20-dsi", }, { }, }; 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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55943b61134sm3079983e87.162.2025.07.17.07.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 07:22:07 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Svyatoslav Ryhel , Dmitry Osipenko Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 5/5] ARM: tegra: add MIPI calibration binding for Tegra20/Tegra30 Date: Thu, 17 Jul 2025 17:21:39 +0300 Message-ID: <20250717142139.57621-6-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250717142139.57621-1-clamor95@gmail.com> References: <20250717142139.57621-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MIPI calibration device node for Tegra20 and Tegra30. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra20.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/nvidia/tegra30.dtsi | 18 ++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvid= ia/tegra20.dtsi index 92d422f83ea4..521261045cc8 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -74,6 +74,16 @@ vi@54080000 { status =3D "disabled"; }; =20 + /* DSI MIPI calibration logic is a part of VI/CSI */ + mipi: mipi@54080220 { + compatible =3D "nvidia,tegra20-mipi"; + reg =3D <0x54080220 0x100>; + clocks =3D <&tegra_car TEGRA20_CLK_VI>, + <&tegra_car TEGRA20_CLK_CSI>; + clock-names =3D "vi", "csi"; + #nvidia,mipi-calibrate-cells =3D <1>; + }; + epp@540c0000 { compatible =3D "nvidia,tegra20-epp"; reg =3D <0x540c0000 0x00040000>; @@ -219,9 +229,13 @@ dsi@54300000 { clock-names =3D "dsi", "parent"; resets =3D <&tegra_car 48>; reset-names =3D "dsi"; + nvidia,mipi-calibrate =3D <&mipi 0>; power-domains =3D <&pd_core>; operating-points-v2 =3D <&dsi_dvfs_opp_table>; status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; }; }; =20 diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvid= ia/tegra30.dtsi index 50b0446f43fc..c52ad3715505 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -164,6 +164,16 @@ vi@54080000 { status =3D "disabled"; }; =20 + /* DSI MIPI calibration logic is a part of VI/CSI */ + mipi: mipi@54080220 { + compatible =3D "nvidia,tegra30-mipi"; + reg =3D <0x54080220 0x100>; + clocks =3D <&tegra_car TEGRA30_CLK_VI>, + <&tegra_car TEGRA30_CLK_CSI>; + clock-names =3D "vi", "csi"; + #nvidia,mipi-calibrate-cells =3D <1>; + }; + epp@540c0000 { compatible =3D "nvidia,tegra30-epp"; reg =3D <0x540c0000 0x00040000>; @@ -321,9 +331,13 @@ dsi@54300000 { clock-names =3D "dsi", "parent"; resets =3D <&tegra_car 48>; reset-names =3D "dsi"; + nvidia,mipi-calibrate =3D <&mipi 0>; power-domains =3D <&pd_core>; operating-points-v2 =3D <&dsia_dvfs_opp_table>; status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; }; =20 dsi@54400000 { @@ -334,9 +348,13 @@ dsi@54400000 { clock-names =3D "dsi", "parent"; resets =3D <&tegra_car 84>; reset-names =3D "dsi"; + nvidia,mipi-calibrate =3D <&mipi 0>; power-domains =3D <&pd_core>; operating-points-v2 =3D <&dsib_dvfs_opp_table>; status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; }; }; =20 --=20 2.48.1