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Thu, 17 Jul 2025 07:22:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E8.mail.protection.outlook.com (10.167.240.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8943.21 via Frontend Transport; Thu, 17 Jul 2025 07:22:12 +0000 Received: from localhost.localdomain (unknown [172.16.64.25]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 1FF714160507; Thu, 17 Jul 2025 15:22:10 +0800 (CST) From: Peter Chen To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, jassisinghbrar@gmail.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, maz@kernel.org, sudeep.holla@arm.com, kajetan.puchalski@arm.com, eballetb@redhat.com, Peter Chen , Guomin Chen , Gary Yang Subject: [PATCH v10 8/9] arm64: dts: cix: Add sky1 base dts initial support Date: Thu, 17 Jul 2025 15:22:08 +0800 Message-Id: <20250717072209.176807-9-peter.chen@cixtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250717072209.176807-1-peter.chen@cixtech.com> References: <20250717072209.176807-1-peter.chen@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E8:EE_|KL1PR0601MB5702:EE_ X-MS-Office365-Filtering-Correlation-Id: 0aeef978-1aa0-42dc-f071-08ddc502a61f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 07:22:12.2414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0aeef978-1aa0-42dc-f071-08ddc502a61f X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR0601MB5702 Content-Type: text/plain; charset="utf-8" CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, and Orion O6 is the motherboard launched by Radxa. See below for detail: https://docs.radxa.com/en/orion/o6/getting-started/introduction In this commit, it only adds limited components for running initramfs at Orion O6. Tested-by: Enric Balletbo i Serra Tested-by: Kajetan Puchalski Signed-off-by: Peter Chen Signed-off-by: Guomin Chen Signed-off-by: Gary Yang Reviewed-by: Krzysztof Kozlowski --- Changes for v10: - Address comments from Krzysztof about "shmem" node and delete two blank l= ines. Changes for v7: - Refine *_scmi_mem nodes for their properties ordering - Delete Krzysztof Kozlowski and Fugang Duan's tag due to substantial chang= es - Add two Tested-by tags from Enric Balletbo i Serra and Kajetan Puchalski Changes for v6: - Add mailbox, scmi and uart support Changes for v5: - Delete pmu-spe node which need to refine, and add it in future Changes for v4: - Add ppi-partition entry for gic-v3 node, and let pmu-a520 and pmu-a720's = interrupt entry get its handle - Remove gic-v3's #redistributor-regions and redistributor-stride properties - Change gic-v3's #interrupt-cells as 4, and change all interrupt specifier= s accordingly - Remove "arm,no-tick-in-suspend" for timer due to global counter is at alw= ays-on power domain - Remove timer's clock frequency due to firmware has already set it - Add Krzysztof Kozlowski's reviewed-by Changes for v3: - Fix two dts coding sytle issues=20 Changes for v2: - Corrects the SoF tag's name - Fix several coding sytle issues - move linux,cma node to dts file - delete memory node, memory size is passed by firmware - delete uart2 node which will be added in future patches - Improve for pmu and cpu node to stands for more specific cpu model - Improve the timer node and add hypervisor virtual timer irq - Pass "make O=3D$OUTKNL CHECK_DTBS=3Dy W=3D1 cix/sky1-orion-o6.dtb" arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/cix/Makefile | 2 + arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 39 +++ arch/arm64/boot/dts/cix/sky1.dtsi | 330 ++++++++++++++++++++++ 4 files changed, 372 insertions(+) create mode 100644 arch/arm64/boot/dts/cix/Makefile create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..8e7ccd0027bd 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom subdir-y +=3D cavium +subdir-y +=3D cix subdir-y +=3D exynos subdir-y +=3D freescale subdir-y +=3D hisilicon diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Mak= efile new file mode 100644 index 000000000000..ed3713982012 --- /dev/null +++ b/arch/arm64/boot/dts/cix/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CIX) +=3D sky1-orion-o6.dtb diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts new file mode 100644 index 000000000000..d74964d53c3b --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +/dts-v1/; + +#include "sky1.dtsi" +/ { + model =3D "Radxa Orion O6"; + compatible =3D "radxa,orion-o6", "cix,sky1"; + + aliases { + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D &uart2; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x28000000>; + linux,cma-default; + }; + }; + +}; + +&uart2 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi new file mode 100644 index 000000000000..7dfe7677e649 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x200>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x300>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu4: cpu@400 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x400>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu5: cpu@500 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x500>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu6: cpu@600 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x600>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu7: cpu@700 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x700>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu8: cpu@800 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x800>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu9: cpu@900 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x900>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu10: cpu@a00 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0xa00>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu11: cpu@b00 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0xb00>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + core4 { + cpu =3D <&cpu4>; + }; + core5 { + cpu =3D <&cpu5>; + }; + core6 { + cpu =3D <&cpu6>; + }; + core7 { + cpu =3D <&cpu7>; + }; + core8 { + cpu =3D <&cpu8>; + }; + core9 { + cpu =3D <&cpu9>; + }; + core10 { + cpu =3D <&cpu10>; + }; + core11 { + cpu =3D <&cpu11>; + }; + }; + }; + }; + + firmware { + ap_to_pm_scmi: scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; + shmem =3D <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + pmu-a520 { + compatible =3D "arm,cortex-a520-pmu"; + interrupts =3D ; + }; + + pmu-a720 { + compatible =3D "arm,cortex-a720-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x20 0>; + dma-ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + uart0: serial@40b0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x040b0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH= _UART0_APB>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart1: serial@40c0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x040c0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH= _UART1_APB>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart2: serial@40d0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x040d0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH= _UART2_APB>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart3: serial@40e0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x040e0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH= _UART3_APB>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + mbox_ap2se: mailbox@5060000 { + compatible =3D "cix,sky1-mbox"; + reg =3D <0x0 0x05060000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + cix,mbox-dir =3D "tx"; + }; + + mbox_se2ap: mailbox@5070000 { + compatible =3D "cix,sky1-mbox"; + reg =3D <0x0 0x05070000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + cix,mbox-dir =3D "rx"; + }; + + ap2pm_scmi_mem: shmem@6590000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x06590000 0x0 0x80>; + reg-io-width =3D <4>; + }; + + mbox_ap2pm: mailbox@6590080 { + compatible =3D "cix,sky1-mbox"; + reg =3D <0x0 0x06590080 0x0 0xff80>; + interrupts =3D ; + #mbox-cells =3D <1>; + cix,mbox-dir =3D "tx"; + }; + + pm2ap_scmi_mem: shmem@65a0000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x065a0000 0x0 0x80>; + reg-io-width =3D <4>; + }; + + mbox_pm2ap: mailbox@65a0080 { + compatible =3D "cix,sky1-mbox"; + reg =3D <0x0 0x065a0080 0x0 0xff80>; + interrupts =3D ; + #mbox-cells =3D <1>; + cix,mbox-dir =3D "rx"; + }; + + mbox_sfh2ap: mailbox@8090000 { + compatible =3D "cix,sky1-mbox"; + reg =3D <0x0 0x08090000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + cix,mbox-dir =3D "rx"; + }; + + mbox_ap2sfh: mailbox@80a0000 { + compatible =3D "cix,sky1-mbox"; + reg =3D <0x0 0x080a0000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + cix,mbox-dir =3D "tx"; + }; + + gic: interrupt-controller@e010000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x0e010000 0 0x10000>, /* GICD */ + <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ + interrupts =3D ; + #interrupt-cells =3D <4>; + interrupt-controller; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@e050000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x0e050000 0x0 0x30000>; + msi-controller; + #msi-cells =3D <1>; + }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_partition1: interrupt-partition-1 { + affinity =3D <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts =3D , + , + , + , + ; + }; +}; --=20 2.25.1