From nobody Mon Oct 6 22:52:27 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68C35EEC3; Thu, 17 Jul 2025 01:16:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752714992; cv=none; b=DRCSeQpICwrhsoaF+XOOphokOYomkLwYpOZi/GYdCtjyeCIjNnfGtTKKx/nCpG3qBKJLZHs4Ha+xr49v8W506DOlBkPgiwEeT5RCOY8/ZBjhPBZhCn5BP5BbLXYj5vKmenYW+m7bV8ao1MLacUP7Bo0TZc26740/bNb4vhXVf5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752714992; c=relaxed/simple; bh=AVGwKN7MDdaOPTY0IeSTCb9+7XZuCkfnL6VpTUccQ9o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L1YSSG0c4gxRhw9fi3YX/BlouSxlJVnF80+lIxgVWMeF6l1PdGQ+aN23b8hg3MrdTAA39raUne24HmBihiFm0xFSi1YV/ys6Enw+d5wJDbhFJsqkKSqkhIysJ9VlRXA37Ug7Vc3DcV8pB5bjX2QA+fuSzpZrlzsBPUFrRm8xrSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4bjFLQ0bwhz1FNHL; Thu, 17 Jul 2025 09:13:50 +0800 (CST) Received: from dggpemf500015.china.huawei.com (unknown [7.185.36.143]) by mail.maildlp.com (Postfix) with ESMTPS id B1FEE180044; Thu, 17 Jul 2025 09:16:27 +0800 (CST) Received: from huawei.com (10.50.165.33) by dggpemf500015.china.huawei.com (7.185.36.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 17 Jul 2025 09:16:27 +0800 From: Longfang Liu To: , , , , CC: , , , , Subject: [PATCH v6 2/3] migration: qm updates BAR configuration Date: Thu, 17 Jul 2025 09:15:01 +0800 Message-ID: <20250717011502.16050-3-liulongfang@huawei.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20250717011502.16050-1-liulongfang@huawei.com> References: <20250717011502.16050-1-liulongfang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpemf500015.china.huawei.com (7.185.36.143) Content-Type: text/plain; charset="utf-8" On new platforms greater than QM_HW_V3, the configuration region for the live migration function of the accelerator device is no longer placed in the VF, but is instead placed in the PF. Therefore, the configuration region of the live migration function needs to be opened when the QM driver is loaded. When the QM driver is uninstalled, the driver needs to clear this configuration. Signed-off-by: Longfang Liu Reviewed-by: Shameer Kolothum --- drivers/crypto/hisilicon/qm.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index d3f5d108b898..0a8888304e15 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -242,6 +242,9 @@ #define QM_QOS_MAX_CIR_U 6 #define QM_AUTOSUSPEND_DELAY 3000 =20 +#define QM_MIG_REGION_SEL 0x100198 +#define QM_MIG_REGION_EN 0x1 + /* abnormal status value for stopping queue */ #define QM_STOP_QUEUE_FAIL 1 #define QM_DUMP_SQC_FAIL 3 @@ -3004,11 +3007,36 @@ static void qm_put_pci_res(struct hisi_qm *qm) pci_release_mem_regions(pdev); } =20 +static void hisi_mig_region_clear(struct hisi_qm *qm) +{ + u32 val; + + /* Clear migration region set of PF */ + if (qm->fun_type =3D=3D QM_HW_PF && qm->ver > QM_HW_V3) { + val =3D readl(qm->io_base + QM_MIG_REGION_SEL); + val &=3D ~BIT(0); + writel(val, qm->io_base + QM_MIG_REGION_SEL); + } +} + +static void hisi_mig_region_enable(struct hisi_qm *qm) +{ + u32 val; + + /* Select migration region of PF */ + if (qm->fun_type =3D=3D QM_HW_PF && qm->ver > QM_HW_V3) { + val =3D readl(qm->io_base + QM_MIG_REGION_SEL); + val |=3D QM_MIG_REGION_EN; + writel(val, qm->io_base + QM_MIG_REGION_SEL); + } +} + static void hisi_qm_pci_uninit(struct hisi_qm *qm) { struct pci_dev *pdev =3D qm->pdev; =20 pci_free_irq_vectors(pdev); + hisi_mig_region_clear(qm); qm_put_pci_res(qm); pci_disable_device(pdev); } @@ -5630,6 +5658,7 @@ int hisi_qm_init(struct hisi_qm *qm) goto err_free_qm_memory; =20 qm_cmd_init(qm); + hisi_mig_region_enable(qm); =20 return 0; =20 --=20 2.24.0