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Thu, 17 Jul 2025 12:16:45 -0700 (PDT) From: Raphael Gallais-Pou Date: Thu, 17 Jul 2025 21:15:34 +0200 Subject: [PATCH 3/4] ARM: dts: sti: extract display subsystem out of soc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250717-sti-rework-v1-3-46d516fb1ebb@gmail.com> References: <20250717-sti-rework-v1-0-46d516fb1ebb@gmail.com> In-Reply-To: <20250717-sti-rework-v1-0-46d516fb1ebb@gmail.com> To: Alain Volmat , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Patrice Chotard , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10843; i=rgallaispou@gmail.com; h=from:subject:message-id; bh=Wiu/65e3susvS7JkHh1yHaahU+pjFzGTsPfFYQByFWw=; b=owEBbQKS/ZANAwAKAechimjUEsK1AcsmYgBoeUwYzf7hOYj6ppQRFLV+8X9OCA8WzrVH8DOrN W6WahlUEF6JAjMEAAEKAB0WIQQgmXv2E+fvbV/9ui/nIYpo1BLCtQUCaHlMGAAKCRDnIYpo1BLC tcp0D/9PM8j3Fqnq+WEeu2zRJNkflTpxsxy4Sh2KeHUoi/zsiPwxJd7hwjSmrzukOsSsbG7hth2 23QhQpBXKwUApvtodc82b2/9FPWCTa6n5RUcUcFCFeO6jZowQg7uFozKaMSSGs6xCsQsfKrkJY6 RPqZnZVRREpZg102KGOslpvBK0KPFxPVKufcIn6ep8NmX1XOMigkdkqW116bryrfUsaEmobOfju c69yF/JU0Xhf8kdCOVUVD5u0v1wOeQqwR5HHOcfQZdATU+6LoOIP1cKRP/qeDbi7cSOBm5V8ncb TKVHginXdiuldgvg9rsH3QWZvNEymY4fQMcuyh7cPa9S1f4etGuac45Pzo0oWElxSCQOg13muio 2fJNY3qOBTaWxQITe8hWNUpIP5x455YuFIe/NYutGHY1HD/eazIY6aLtgTp9OtmtEmqX4daF6nO 7tyJHhzzmxngNGoO9LIgLD1czx0Kq20S52hwwI1tzMfEgW0dWfFHRIh1EJcK76B+f2de62YkaQ8 bPwf2hsZrbljJqHOLKp5OdH2bvyrwUlwCAH2xqiM+n0Ayqn/BVmSmOUUWOyq6pvEHiQXfu58ctK 4tmXrxwDws3pbIrjD85aVA154ZnT6/Gi0bu99ciLCpHcMhOQbvyC9xQBR6m18ZWaSv/n/wfMiDr 8jBo4Yt8YeOLYww== X-Developer-Key: i=rgallaispou@gmail.com; a=openpgp; fpr=20997BF613E7EF6D5FFDBA2FE7218A68D412C2B5 The display subsystem represent how IPs are interacting together and have nothing to do within the SoC node. Extract it from the SoC node and let IPs nodes in the Soc node. Several nodes did not use conventional name: * sti-display-subsystem -> display-subsystem * sti-controller -> display-controller * sti-tvout -> encoder * sti-hda -> analog * sti-hqvdp -> plane Signed-off-by: Raphael Gallais-Pou Acked-by: Alain Volmat --- arch/arm/boot/dts/st/stih410.dtsi | 316 +++++++++++++++++++++++-----------= ---- 1 file changed, 188 insertions(+), 128 deletions(-) diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih4= 10.dtsi index d56343f44fda4e9e1de2e5efc86e2d984bad14b4..47d66d7eb07a3d73d98b3e21d62= b2253aa1171e4 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -34,6 +34,41 @@ usb2_picophy2: phy3 { status =3D "disabled"; }; =20 + display-subsystem { + compatible =3D "st,sti-display-subsystem"; + ports =3D <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>; + + assigned-clocks =3D <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>; + + assigned-clock-parents =3D <0>, + <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + + assigned-clock-rates =3D <297000000>, + <297000000>, + <0>, + <400000000>, + <400000000>; + }; + soc { ohci0: usb@9a03c00 { compatible =3D "st,st-ohci-300x"; @@ -99,153 +134,178 @@ ehci1: usb@9a83e00 { status =3D "disabled"; }; =20 - sti-display-subsystem@0 { - compatible =3D "st,sti-display-subsystem"; + compositor: display-controller@9d11000 { + compatible =3D "st,stih407-compositor"; + reg =3D <0x9d11000 0x1000>; + + clock-names =3D "compo_main", + "compo_aux", + "pix_main", + "pix_aux", + "pix_gdp1", + "pix_gdp2", + "pix_gdp3", + "pix_gdp4", + "main_parent", + "aux_parent"; + + clocks =3D <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + reset-names =3D "compo-main", "compo-aux"; + resets =3D <&softreset STIH407_COMPO_SOFTRESET>, + <&softreset STIH407_COMPO_SOFTRESET>; + st,vtg =3D <&vtg_main>, <&vtg_aux>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + compo_main_out: endpoint { + remote-endpoint =3D <&tvout_in0>; + }; + }; + + port@1 { + reg =3D <1>; + compo_aux_out: endpoint { + remote-endpoint =3D <&tvout_in1>; + }; + }; + }; + }; + + tvout: encoder@8d08000 { + compatible =3D "st,stih407-tvout"; + reg =3D <0x8d08000 0x1000>; + reg-names =3D "tvout-reg"; + reset-names =3D "tvout"; + resets =3D <&softreset STIH407_HDTVOUT_SOFTRESET>; #address-cells =3D <1>; #size-cells =3D <1>; + assigned-clocks =3D <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>; =20 - reg =3D <0 0>; - assigned-clocks =3D <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents =3D <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, + assigned-clock-parents =3D <&clk_s_d2_quadfs 0>, + <&clk_tmdsout_hdmi>, <&clk_s_d2_quadfs 0>, + <&clk_s_d0_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; =20 - assigned-clock-rates =3D <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible =3D "st,stih407-compositor"; - reg =3D <0x9d11000 0x1000>; - - clock-names =3D "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks =3D <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names =3D "compo-main", "compo-aux"; - resets =3D <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg =3D <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible =3D "st,stih407-tvout"; - reg =3D <0x8d08000 0x1000>; - reg-names =3D "tvout-reg"; - reset-names =3D "tvout"; - resets =3D <&softreset STIH407_HDTVOUT_SOFTRESET>; + ports { #address-cells =3D <1>; - #size-cells =3D <1>; - assigned-clocks =3D <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; + #size-cells =3D <0>; =20 - assigned-clock-parents =3D <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; + port@0 { + reg =3D <0>; + tvout_in0: endpoint { + remote-endpoint =3D <&compo_main_out>; + }; + }; + + port@1 { + reg =3D <1>; + tvout_in1: endpoint { + remote-endpoint =3D <&compo_aux_out>; + }; + }; + + port@2 { + reg =3D <2>; + tvout_out0: endpoint { + remote-endpoint =3D <&hdmi_in>; + }; + }; + + port@3 { + reg =3D <3>; + tvout_out1: endpoint { + remote-endpoint =3D <&hda_in>; + }; + }; }; + }; =20 - sti_hdmi: sti-hdmi@8d04000 { - compatible =3D "st,stih407-hdmi"; - reg =3D <0x8d04000 0x1000>; - reg-names =3D "hdmi-reg"; - #sound-dai-cells =3D <0>; - interrupts =3D ; - interrupt-names =3D "irq"; - clock-names =3D "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; + sti_hdmi: hdmi@8d04000 { + compatible =3D "st,stih407-hdmi"; + reg =3D <0x8d04000 0x1000>; + reg-names =3D "hdmi-reg"; + #sound-dai-cells =3D <0>; + interrupts =3D ; + interrupt-names =3D "irq"; + clock-names =3D "pix", + "tmds", + "phy", + "audio", + "main_parent", + "aux_parent"; =20 - clocks =3D <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; + clocks =3D <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; =20 - hdmi,hpd-gpio =3D <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names =3D "hdmi"; - resets =3D <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc =3D <&hdmiddc>; + hdmi,hpd-gpio =3D <&pio5 3 GPIO_ACTIVE_LOW>; + reset-names =3D "hdmi"; + resets =3D <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; + ddc =3D <&hdmiddc>; + + port { + hdmi_in: endpoint { + remote-endpoint =3D <&tvout_out0>; + }; }; + }; =20 - sti-hda@8d02000 { - compatible =3D "st,stih407-hda"; - status =3D "disabled"; - reg =3D <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names =3D "hda-reg", "video-dacs-ctrl"; - clock-names =3D "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks =3D <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; + analog@8d02000 { + compatible =3D "st,stih407-hda"; + status =3D "disabled"; + reg =3D <0x8d02000 0x400>, <0x92b0120 0x4>; + reg-names =3D "hda-reg", "video-dacs-ctrl"; + clock-names =3D "pix", + "hddac", + "main_parent", + "aux_parent"; + clocks =3D <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; =20 - sti-hqvdp@9c00000 { - compatible =3D "st,stih407-hqvdp"; - reg =3D <0x9C00000 0x100000>; - clock-names =3D "hqvdp", "pix_main"; - clocks =3D <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names =3D "hqvdp"; - resets =3D <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg =3D <&vtg_main>; + port { + hda_in: endpoint { + remote-endpoint =3D <&tvout_out1>; + }; }; }; =20 + hqvdp: plane@9c00000 { + compatible =3D "st,stih407-hqvdp"; + reg =3D <0x9C00000 0x100000>; + clock-names =3D "hqvdp", "pix_main"; + clocks =3D <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; + reset-names =3D "hqvdp"; + resets =3D <&softreset STIH407_HDQVDP_SOFTRESET>; + st,vtg =3D <&vtg_main>; + }; + bdisp0:bdisp@9f10000 { compatible =3D "st,stih407-bdisp"; reg =3D <0x9f10000 0x1000>; --=20 2.50.1