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Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-tpg.c | 737 ++++++++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-tpg.h | 130 +++++ drivers/media/platform/qcom/camss/camss.h | 5 + 4 files changed, 873 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 76845a456c459538b8e9f782dd58e3b59aff3ef1..e4cf3033b8798cf0ffeff85409a= e4ed3559879c1 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -24,5 +24,6 @@ qcom-camss-objs +=3D \ camss-vfe.o \ camss-video.o \ camss-format.o \ + camss-tpg.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-tpg.c b/drivers/media/= platform/qcom/camss/camss-tpg.c new file mode 100644 index 0000000000000000000000000000000000000000..3ef5b6dcdf2f7e8bbe442667d0f= df64ee30e2923 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.c @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-tpg.c + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +const char * const testgen_payload_modes[] =3D { + "Disabled", + "Incrementing", + "Alternating 0x55/0xAA", + NULL, + NULL, + "Pseudo-random Data", + "User Specified", + NULL, + NULL, + "Color bars", + NULL +}; + +static const struct tpg_format_info formats_gen1[] =3D { + { + MEDIA_BUS_FMT_SBGGR8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SGBRG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SGRBG8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SRGGB8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_SBGGR10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SGBRG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SGRBG10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SRGGB10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, + { + MEDIA_BUS_FMT_SBGGR12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_SGBRG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_SGRBG12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_SRGGB12_1X12, + DATA_TYPE_RAW_12BIT, + ENCODE_FORMAT_UNCOMPRESSED_12_BIT, + }, + { + MEDIA_BUS_FMT_Y8_1X8, + DATA_TYPE_RAW_8BIT, + ENCODE_FORMAT_UNCOMPRESSED_8_BIT, + }, + { + MEDIA_BUS_FMT_Y10_1X10, + DATA_TYPE_RAW_10BIT, + ENCODE_FORMAT_UNCOMPRESSED_10_BIT, + }, +}; + +const struct tpg_formats tpg_formats_gen1 =3D { + .nformats =3D ARRAY_SIZE(formats_gen1), + .formats =3D formats_gen1 +}; + +const struct tpg_format_info *tpg_get_fmt_entry(const struct tpg_format_in= fo *formats, + unsigned int nformats, + u32 code) +{ + unsigned int i; + + for (i =3D 0; i < nformats; i++) + if (code =3D=3D formats[i].code) + return &formats[i]; + + WARN(1, "Unknown format\n"); + + return &formats[0]; +} + +/* + * tpg_set_clock_rates - Calculate and set clock rates on tpg module + * @tpg: tpg device + */ +static int tpg_set_clock_rates(struct tpg_device *tpg) +{ + struct device *dev =3D tpg->camss->dev; + int i, j; + int ret; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + u64 min_rate =3D 0; + long round_rate; + + camss_add_clock_margin(&min_rate); + + for (j =3D 0; j < clock->nfreqs; j++) + if (min_rate < clock->freq[j]) + break; + + if (j =3D=3D clock->nfreqs) { + dev_err(dev, + "clock is too high for TPG\n"); + return -EINVAL; + } + + /* if clock is not available */ + /* set highest possible tpg clock rate */ + if (min_rate =3D=3D 0) + j =3D clock->nfreqs - 1; + + round_rate =3D clk_round_rate(clock->clk, clock->freq[j]); + if (round_rate < 0) { + dev_err(dev, "clk round rate failed: %ld\n", + round_rate); + return -EINVAL; + } + + tpg->timer_clk_rate =3D round_rate; + + ret =3D clk_set_rate(clock->clk, tpg->timer_clk_rate); + if (ret < 0) { + dev_err(dev, "clk set rate failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +/* + * tpg_set_power - Power on/off tpg module + * @sd: tpg V4L2 subdevice + * @on: Requested power state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_power(struct v4l2_subdev *sd, int on) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct device *dev =3D tpg->camss->dev; + + if (on) { + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + ret =3D tpg_set_clock_rates(tpg); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + ret =3D camss_enable_clocks(tpg->nclocks, tpg->clock, dev); + if (ret < 0) { + pm_runtime_put_sync(dev); + return ret; + } + + enable_irq(tpg->irq); + + tpg->res->hw_ops->reset(tpg); + + tpg->res->hw_ops->hw_version(tpg); + } else { + disable_irq(tpg->irq); + + camss_disable_clocks(tpg->nclocks, tpg->clock); + + pm_runtime_put_sync(dev); + } + + return 0; +} + +/* + * tpg_set_stream - Enable/disable streaming on tpg module + * @sd: tpg V4L2 subdevice + * @enable: Requested streaming state + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + int ret =3D 0; + + if (enable) { + ret =3D v4l2_ctrl_handler_setup(&tpg->ctrls); + if (ret < 0) { + dev_err(tpg->camss->dev, + "could not sync v4l2 controls: %d\n", ret); + return ret; + } + } + + tpg->res->hw_ops->configure_stream(tpg, enable); + + return 0; +} + +/* + * __tpg_get_format - Get pointer to format structure + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad from which format is requested + * @which: TRY or ACTIVE format + * + * Return pointer to TRY or ACTIVE format structure + */ +static struct v4l2_mbus_framefmt * +__tpg_get_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + if (which =3D=3D V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_state_get_format(sd_state, + pad); + + return &tpg->fmt[pad]; +} + +/* + * tpg_try_format - Handle try format by pad subdev method + * @tpg: tpg device + * @cfg: V4L2 subdev pad configuration + * @pad: pad on which format is requested + * @fmt: pointer to v4l2 format structure + * @which: wanted subdev format + */ +static void tpg_try_format(struct tpg_device *tpg, + struct v4l2_subdev_state *sd_state, + unsigned int pad, + struct v4l2_mbus_framefmt *fmt, + enum v4l2_subdev_format_whence which) +{ + unsigned int i; + + switch (pad) { + case MSM_TPG_PAD_SINK: + /* Test generator is enabled, set format on source */ + /* pad to allow test generator usage */ + + for (i =3D 0; i < tpg->res->formats->nformats; i++) + if (tpg->res->formats->formats[i].code =3D=3D fmt->code) + break; + + /* If not found, use SBGGR8 as default */ + if (i >=3D tpg->res->formats->nformats) + fmt->code =3D MEDIA_BUS_FMT_SBGGR8_1X8; + + fmt->width =3D clamp_t(u32, fmt->width, 1, 8191); + fmt->height =3D clamp_t(u32, fmt->height, 1, 8191); + + fmt->field =3D V4L2_FIELD_NONE; + fmt->colorspace =3D V4L2_COLORSPACE_SRGB; + + break; + case MSM_TPG_PAD_SRC: + /* Set and return a format same as sink pad */ + + *fmt =3D *__tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + which); + + break; + } +} + +/* + * tpg_enum_mbus_code - Handle format enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @code: pointer to v4l2_subdev_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + if (code->pad =3D=3D MSM_TPG_PAD_SINK) { + if (code->index >=3D tpg->res->formats->nformats) + return -EINVAL; + + code->code =3D tpg->res->formats->formats[code->index].code; + } else { + if (code->index > 0) + return -EINVAL; + + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SINK, + code->which); + + code->code =3D format->code; + } + + return 0; +} + +/* + * tpg_enum_frame_size - Handle frame size enumeration + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fse: pointer to v4l2_subdev_frame_size_enum structure + * return -EINVAL or zero on success + */ +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt format; + + if (fse->index !=3D 0) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D 1; + format.height =3D 1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->min_width =3D format.width; + fse->min_height =3D format.height; + + if (format.code !=3D fse->code) + return -EINVAL; + + format.code =3D fse->code; + format.width =3D -1; + format.height =3D -1; + tpg_try_format(tpg, sd_state, fse->pad, &format, fse->which); + fse->max_width =3D format.width; + fse->max_height =3D format.height; + + return 0; +} + +/* + * tpg_get_format - Handle get format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + fmt->format =3D *format; + + return 0; +} + +/* + * tpg_set_format - Handle set format by pads subdev method + * @sd: tpg V4L2 subdevice + * @cfg: V4L2 subdev pad configuration + * @fmt: pointer to v4l2 subdev format structure + * + * Return -EINVAL or zero on success + */ +static int tpg_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct tpg_device *tpg =3D v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format =3D __tpg_get_format(tpg, sd_state, fmt->pad, fmt->which); + if (!format) + return -EINVAL; + + tpg_try_format(tpg, sd_state, fmt->pad, &fmt->format, + fmt->which); + *format =3D fmt->format; + + if (fmt->pad =3D=3D MSM_TPG_PAD_SINK) { + format =3D __tpg_get_format(tpg, sd_state, + MSM_TPG_PAD_SRC, + fmt->which); + + *format =3D fmt->format; + tpg_try_format(tpg, sd_state, MSM_TPG_PAD_SRC, + format, + fmt->which); + } + return 0; +} + +/* + * tpg_init_formats - Initialize formats on all pads + * @sd: tpg V4L2 subdevice + * @fh: V4L2 subdev file handle + * + * Initialize all pad formats with default values. + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_init_formats(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct v4l2_subdev_format format =3D { + .pad =3D MSM_TPG_PAD_SINK, + .which =3D fh ? V4L2_SUBDEV_FORMAT_TRY : + V4L2_SUBDEV_FORMAT_ACTIVE, + .format =3D { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .width =3D 1920, + .height =3D 1080 + } + }; + + return tpg_set_format(sd, fh ? fh->state : NULL, &format); +} + +/* + * tpg_set_test_pattern - Set test generator's pattern mode + * @tpg: TPG device + * @value: desired test pattern mode + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_set_test_pattern(struct tpg_device *tpg, s32 value) +{ + return tpg->res->hw_ops->configure_testgen_pattern(tpg, value); +} + +/* + * tpg_s_ctrl - Handle set control subdev method + * @ctrl: pointer to v4l2 control structure + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tpg_device *tpg =3D container_of(ctrl->handler, + struct tpg_device, ctrls); + int ret =3D -EINVAL; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret =3D tpg_set_test_pattern(tpg, ctrl->val); + break; + } + + return ret; +} + +static const struct v4l2_ctrl_ops tpg_ctrl_ops =3D { + .s_ctrl =3D tpg_s_ctrl, +}; + +/* + * msm_tpg_subdev_init - Initialize tpg device structure and resources + * @tpg: tpg device + * @res: tpg module resources table + * @id: tpg module id + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id) +{ + struct device *dev =3D camss->dev; + struct platform_device *pdev =3D to_platform_device(dev); + int i, j; + int ret; + + tpg->camss =3D camss; + tpg->id =3D id; + tpg->res =3D &res->tpg; + tpg->res->hw_ops->subdev_init(tpg); + + /* Memory */ + tpg->base =3D devm_platform_ioremap_resource_byname(pdev, res->reg[0]); + if (IS_ERR(tpg->base)) + return PTR_ERR(tpg->base); + + /* Interrupt */ + ret =3D platform_get_irq_byname(pdev, res->interrupt[0]); + if (ret < 0) + return ret; + + tpg->irq =3D ret; + snprintf(tpg->irq_name, sizeof(tpg->irq_name), "%s_%s%d", + dev_name(dev), MSM_TPG_NAME, tpg->id); + + ret =3D devm_request_irq(dev, tpg->irq, tpg->res->hw_ops->isr, + IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, + tpg->irq_name, tpg); + if (ret < 0) { + dev_err(dev, "request_irq failed: %d\n", ret); + return ret; + } + + /* Clocks */ + tpg->nclocks =3D 0; + while (res->clock[tpg->nclocks]) + tpg->nclocks++; + + tpg->clock =3D devm_kcalloc(dev, + tpg->nclocks, sizeof(*tpg->clock), + GFP_KERNEL); + if (!tpg->clock) + return -ENOMEM; + + for (i =3D 0; i < tpg->nclocks; i++) { + struct camss_clock *clock =3D &tpg->clock[i]; + + clock->clk =3D devm_clk_get(dev, res->clock[i]); + if (IS_ERR(clock->clk)) + return PTR_ERR(clock->clk); + + clock->name =3D res->clock[i]; + + clock->nfreqs =3D 0; + while (res->clock_rate[i][clock->nfreqs]) + clock->nfreqs++; + + if (!clock->nfreqs) { + clock->freq =3D NULL; + continue; + } + + clock->freq =3D devm_kcalloc(dev, + clock->nfreqs, + sizeof(*clock->freq), + GFP_KERNEL); + if (!clock->freq) + return -ENOMEM; + + for (j =3D 0; j < clock->nfreqs; j++) + clock->freq[j] =3D res->clock_rate[i][j]; + } + + return 0; +} + +/* + * tpg_link_setup - Setup tpg connections + * @entity: Pointer to media entity structure + * @local: Pointer to local pad + * @remote: Pointer to remote pad + * @flags: Link flags + * + * Rreturn 0 on success + */ +static int tpg_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + if (flags & MEDIA_LNK_FL_ENABLED) + if (media_pad_remote_pad_first(local)) + return -EBUSY; + + return 0; +} + +static const struct v4l2_subdev_core_ops tpg_core_ops =3D { + .s_power =3D tpg_set_power, +}; + +static const struct v4l2_subdev_video_ops tpg_video_ops =3D { + .s_stream =3D tpg_set_stream, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops =3D { + .enum_mbus_code =3D tpg_enum_mbus_code, + .enum_frame_size =3D tpg_enum_frame_size, + .get_fmt =3D tpg_get_format, + .set_fmt =3D tpg_set_format, +}; + +static const struct v4l2_subdev_ops tpg_v4l2_ops =3D { + .core =3D &tpg_core_ops, + .video =3D &tpg_video_ops, + .pad =3D &tpg_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops tpg_v4l2_internal_ops =3D { + .open =3D tpg_init_formats, +}; + +static const struct media_entity_operations tpg_media_ops =3D { + .link_setup =3D tpg_link_setup, + .link_validate =3D v4l2_subdev_link_validate, +}; + +/* + * msm_tpg_register_entity - Register subdev node for tpg module + * @tpg: tpg device + * @v4l2_dev: V4L2 device + * + * Return 0 on success or a negative error code otherwise + */ +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev) +{ + struct v4l2_subdev *sd =3D &tpg->subdev; + struct media_pad *pads =3D tpg->pads; + struct device *dev =3D tpg->camss->dev; + int ret; + + v4l2_subdev_init(sd, &tpg_v4l2_ops); + sd->internal_ops =3D &tpg_v4l2_internal_ops; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; + snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", + MSM_TPG_NAME, tpg->id); + v4l2_set_subdevdata(sd, tpg); + + ret =3D v4l2_ctrl_handler_init(&tpg->ctrls, 1); + if (ret < 0) { + dev_err(dev, "Failed to init ctrl handler: %d\n", ret); + return ret; + } + + tpg->testgen_mode =3D v4l2_ctrl_new_std_menu_items(&tpg->ctrls, + &tpg_ctrl_ops, V4L2_CID_TEST_PATTERN, + tpg->testgen.nmodes, 0, 0, + tpg->testgen.modes); + + if (tpg->ctrls.error) { + dev_err(dev, "Failed to init ctrl: %d\n", tpg->ctrls.error); + ret =3D tpg->ctrls.error; + goto free_ctrl; + } + + tpg->subdev.ctrl_handler =3D &tpg->ctrls; + + ret =3D tpg_init_formats(sd, NULL); + if (ret < 0) { + dev_err(dev, "Failed to init format: %d\n", ret); + goto free_ctrl; + } + + pads[MSM_TPG_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; + pads[MSM_TPG_PAD_SRC].flags =3D MEDIA_PAD_FL_SOURCE; + + sd->entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + sd->entity.ops =3D &tpg_media_ops; + ret =3D media_entity_pads_init(&sd->entity, MSM_TPG_PADS_NUM, pads); + if (ret < 0) { + dev_err(dev, "Failed to init media entity: %d\n", ret); + goto free_ctrl; + } + + ret =3D v4l2_device_register_subdev(v4l2_dev, sd); + if (ret < 0) { + dev_err(dev, "Failed to register subdev: %d\n", ret); + media_entity_cleanup(&sd->entity); + goto free_ctrl; + } + + return 0; + +free_ctrl: + v4l2_ctrl_handler_free(&tpg->ctrls); + + return ret; +} + +/* + * msm_tpg_unregister_entity - Unregister tpg module subdev node + * @tpg: tpg device + */ +void msm_tpg_unregister_entity(struct tpg_device *tpg) +{ + v4l2_device_unregister_subdev(&tpg->subdev); + media_entity_cleanup(&tpg->subdev.entity); + v4l2_ctrl_handler_free(&tpg->ctrls); +} diff --git a/drivers/media/platform/qcom/camss/camss-tpg.h b/drivers/media/= platform/qcom/camss/camss-tpg.h new file mode 100644 index 0000000000000000000000000000000000000000..63fdb090481cf1297890e3cd501= 91f4bc103fc95 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * camss-tpg.h + * + * Qualcomm MSM Camera Subsystem - TPG Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef QC_MSM_CAMSS_TPG_H +#define QC_MSM_CAMSS_TPG_H + +#include +#include +#include +#include +#include +#include +#include + +#define MSM_TPG_PAD_SINK 0 +#define MSM_TPG_PAD_SRC 1 +#define MSM_TPG_PADS_NUM 2 + +#define DATA_TYPE_RAW_8BIT 0x2a +#define DATA_TYPE_RAW_10BIT 0x2b +#define DATA_TYPE_RAW_12BIT 0x2c + +#define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 +#define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 +#define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 +#define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 +#define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 +#define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 +#define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 + +#define MSM_TPG_NAME "msm_tpg" + +enum tpg_testgen_mode { + TPG_PAYLOAD_MODE_DISABLED =3D 0, + TPG_PAYLOAD_MODE_INCREMENTING =3D 1, + TPG_PAYLOAD_MODE_ALTERNATING_55_AA =3D 2, + TPG_PAYLOAD_MODE_RANDOM =3D 5, + TPG_PAYLOAD_MODE_USER_SPECIFIED =3D 6, + TPG_PAYLOAD_MODE_COLOR_BARS =3D 9, + TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 =3D 9, /* excluding disabled */ +}; + +struct tpg_testgen_config { + enum tpg_testgen_mode mode; + const char * const*modes; + u8 nmodes; +}; + +struct tpg_format_info { + u32 code; + u8 data_type; + u8 encode_format; +}; + +struct tpg_formats { + unsigned int nformats; + const struct tpg_format_info *formats; +}; + +struct tpg_device; + +struct tpg_hw_ops { + void (*configure_stream)(struct tpg_device *tpg, u8 enable); + + int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val); + + u32 (*hw_version)(struct tpg_device *tpg); + + irqreturn_t (*isr)(int irq, void *dev); + + int (*reset)(struct tpg_device *tpg); + + void (*subdev_init)(struct tpg_device *tpg); +}; + +struct tpg_subdev_resources { + u8 lane_cnt; + u8 vc_cnt; + const struct tpg_formats *formats; + const struct tpg_hw_ops *hw_ops; +}; + +struct tpg_device { + struct camss *camss; + u8 id; + struct v4l2_subdev subdev; + struct media_pad pads[MSM_TPG_PADS_NUM]; + void __iomem *base; + void __iomem *base_clk_mux; + u32 irq; + char irq_name[30]; + struct camss_clock *clock; + int nclocks; + u32 timer_clk_rate; + struct tpg_testgen_config testgen; + struct v4l2_mbus_framefmt fmt[MSM_TPG_PADS_NUM]; + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *testgen_mode; + const struct tpg_subdev_resources *res; + const struct tpg_format *formats; + unsigned int nformats; +}; + +struct camss_subdev_resources; + +const struct tpg_format_info *tpg_get_fmt_entry(const struct tpg_format_in= fo *formats, + unsigned int nformats, + u32 code); + +int msm_tpg_subdev_init(struct camss *camss, + struct tpg_device *tpg, + const struct camss_subdev_resources *res, u8 id); + +int msm_tpg_register_entity(struct tpg_device *tpg, + struct v4l2_device *v4l2_dev); + +void msm_tpg_unregister_entity(struct tpg_device *tpg); + +extern const char * const testgen_payload_modes[]; + +extern const struct tpg_formats tpg_formats_gen1; + +extern const struct tpg_hw_ops tpg_ops_gen1; + +#endif /* QC_MSM_CAMSS_TPG_H */ diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index b5600a8b2c4b3972633d42938feec9265b44dec5..99392e3bada80a8736b2c317308= e510e5a7c66ea 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -21,6 +21,7 @@ #include "camss-csid.h" #include "camss-csiphy.h" #include "camss-ispif.h" +#include "camss-tpg.h" #include "camss-vfe.h" #include "camss-format.h" =20 @@ -51,6 +52,7 @@ struct camss_subdev_resources { char *interrupt[CAMSS_RES_MAX]; union { struct csiphy_subdev_resources csiphy; + struct tpg_subdev_resources tpg; struct csid_subdev_resources csid; struct vfe_subdev_resources vfe; }; @@ -100,6 +102,7 @@ struct camss_resources { enum camss_version version; const char *pd_name; const struct camss_subdev_resources *csiphy_res; + const struct camss_subdev_resources *tpg_res; const struct camss_subdev_resources *csid_res; const struct camss_subdev_resources *ispif_res; const struct camss_subdev_resources *vfe_res; @@ -107,6 +110,7 @@ struct camss_resources { const struct resources_icc *icc_res; const unsigned int icc_path_num; const unsigned int csiphy_num; + const unsigned int tpg_num; const unsigned int csid_num; const unsigned int vfe_num; int (*link_entities)(struct camss *camss); @@ -118,6 +122,7 @@ struct camss { struct media_device media_dev; struct device *dev; struct csiphy_device *csiphy; + struct tpg_device *tpg; struct csid_device *csid; struct ispif_device *ispif; struct vfe_device *vfe; --=20 2.34.1 From nobody Mon Oct 6 21:02:50 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D897E1F869E; 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Thu, 17 Jul 2025 03:20:34 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56H3KXsg018042 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Jul 2025 03:20:33 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 16 Jul 2025 20:20:31 -0700 From: Wenmeng Liu Date: Thu, 17 Jul 2025 11:20:06 +0800 Subject: [PATCH v2 2/3] media: qcom: camss: Add link support for TPG common Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250717-lemans_tpg-v2-2-a2538659349c@quicinc.com> References: <20250717-lemans_tpg-v2-0-a2538659349c@quicinc.com> In-Reply-To: <20250717-lemans_tpg-v2-0-a2538659349c@quicinc.com> To: Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab CC: , , , Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/camss-csid.c | 44 +++++++++++++++++----- drivers/media/platform/qcom/camss/camss.c | 52 ++++++++++++++++++++++= ++++ 2 files changed, 87 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 5284b5857368c37c202cd89dad6ae8042b637537..1ee4c4cc61cb32ce731dd812352= 2cc729d1ae3bb 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1226,6 +1226,23 @@ void msm_csid_get_csid_id(struct media_entity *entit= y, u8 *id) *id =3D csid->id; } =20 +/* + * csid_get_csiphy_tpg_lane_assign - Calculate lane assign by tpg lane num + * @num - tpg lane num + * + * Return lane assign + */ +static u32 csid_get_csiphy_tpg_lane_assign(int num) +{ + u32 lane_assign =3D 0; + int i; + + for (i =3D (num - 1); i >=3D 0; i--) + lane_assign |=3D i << (i * 4); + + return lane_assign; +} + /* * csid_get_lane_assign - Calculate CSI2 lane assign configuration paramet= er * @lane_cfg - CSI2 lane configuration @@ -1266,6 +1283,7 @@ static int csid_link_setup(struct media_entity *entit= y, struct csid_device *csid; struct csiphy_device *csiphy; struct csiphy_lanes_cfg *lane_cfg; + struct tpg_device *tpg; =20 sd =3D media_entity_to_v4l2_subdev(entity); csid =3D v4l2_get_subdevdata(sd); @@ -1277,18 +1295,26 @@ static int csid_link_setup(struct media_entity *ent= ity, return -EBUSY; =20 sd =3D media_entity_to_v4l2_subdev(remote->entity); - csiphy =3D v4l2_get_subdevdata(sd); + if (strnstr(sd->name, MSM_TPG_NAME, strlen(MSM_TPG_NAME))) { + tpg =3D v4l2_get_subdevdata(sd); =20 - /* If a sensor is not linked to CSIPHY */ - /* do no allow a link from CSIPHY to CSID */ - if (!csiphy->cfg.csi2) - return -EPERM; + csid->phy.lane_cnt =3D tpg->res->lane_cnt; + csid->phy.csiphy_id =3D tpg->id; + csid->phy.lane_assign =3D csid_get_csiphy_tpg_lane_assign(csid->phy.lan= e_cnt); + } else { + csiphy =3D v4l2_get_subdevdata(sd); + + /* If a sensor is not linked to CSIPHY */ + /* do no allow a link from CSIPHY to CSID */ + if (!csiphy->cfg.csi2) + return -EPERM; =20 - csid->phy.csiphy_id =3D csiphy->id; + csid->phy.csiphy_id =3D csiphy->id; =20 - lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; - csid->phy.lane_cnt =3D lane_cfg->num_data; - csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg); + lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; + csid->phy.lane_cnt =3D lane_cfg->num_data; + csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg); + } } /* Decide which virtual channels to enable based on which source pads are= enabled */ if (local->flags & MEDIA_PAD_FL_SOURCE) { diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index af5c9326736f9c8576816c91b73ad3e1d3a49dbf..34f71039038e881ced9c9f06bd7= 0915b5c5f610f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3913,6 +3913,19 @@ static int camss_init_subdevices(struct camss *camss) } } =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) { + ret =3D msm_tpg_subdev_init(camss, &camss->tpg[i], + &res->tpg_res[i], i); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init tpg%d sub-device: %d\n", + i, ret); + return ret; + } + } + } + /* note: SM8250 requires VFE to be initialized before CSID */ for (i =3D 0; i < camss->res->vfe_num; i++) { ret =3D msm_vfe_subdev_init(camss, &camss->vfe[i], @@ -4002,6 +4015,23 @@ static int camss_link_entities(struct camss *camss) } } =20 + for (i =3D 0; i < camss->res->tpg_num; i++) { + for (j =3D 0; j < camss->res->csid_num; j++) { + ret =3D media_create_pad_link(&camss->tpg[i].subdev.entity, + MSM_TPG_PAD_SRC, + &camss->csid[j].subdev.entity, + MSM_CSID_PAD_SINK, + 0); + if (ret < 0) { + camss_link_err(camss, + camss->tpg[i].subdev.entity.name, + camss->csid[j].subdev.entity.name, + ret); + return ret; + } + } + } + if (camss->ispif) { for (i =3D 0; i < camss->res->csid_num; i++) { for (j =3D 0; j < camss->ispif->line_num; j++) { @@ -4106,6 +4136,19 @@ static int camss_register_entities(struct camss *cam= ss) } } =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) { + ret =3D msm_tpg_register_entity(&camss->tpg[i], + &camss->v4l2_dev); + if (ret < 0) { + dev_err(camss->dev, + "Failed to register tpg%d entity: %d\n", + i, ret); + goto err_reg_tpg; + } + } + } + for (i =3D 0; i < camss->res->csid_num; i++) { ret =3D msm_csid_register_entity(&camss->csid[i], &camss->v4l2_dev); @@ -4149,6 +4192,10 @@ static int camss_register_entities(struct camss *cam= ss) for (i--; i >=3D 0; i--) msm_csid_unregister_entity(&camss->csid[i]); =20 + i =3D camss->res->tpg_num; +err_reg_tpg: + for (i--; i >=3D 0; i--) + msm_tpg_unregister_entity(&camss->tpg[i]); i =3D camss->res->csiphy_num; err_reg_csiphy: for (i--; i >=3D 0; i--) @@ -4170,6 +4217,11 @@ static void camss_unregister_entities(struct camss *= camss) for (i =3D 0; i < camss->res->csiphy_num; i++) msm_csiphy_unregister_entity(&camss->csiphy[i]); =20 + if (camss->tpg) { + for (i =3D 0; i < camss->res->tpg_num; i++) + msm_tpg_unregister_entity(&camss->tpg[i]); + } + for (i =3D 0; i < camss->res->csid_num; i++) msm_csid_unregister_entity(&camss->csid[i]); =20 --=20 2.34.1 From nobody Mon Oct 6 21:02:50 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A55A81FF601; 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Thu, 17 Jul 2025 03:20:37 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56H3KaeG007573 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Jul 2025 03:20:36 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 16 Jul 2025 20:20:34 -0700 From: Wenmeng Liu Date: Thu, 17 Jul 2025 11:20:07 +0800 Subject: [PATCH v2 3/3] media: qcom: camss: tpg: Add TPG support for SA8775P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250717-lemans_tpg-v2-3-a2538659349c@quicinc.com> References: <20250717-lemans_tpg-v2-0-a2538659349c@quicinc.com> In-Reply-To: <20250717-lemans_tpg-v2-0-a2538659349c@quicinc.com> To: Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab CC: , , , Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen3.c | 17 ++ drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 245 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 56 +++++ 4 files changed, 319 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index e4cf3033b8798cf0ffeff85409ae4ed3559879c1..274fa1e8fef3ce972a94e735565= 1c3801bc1dddc 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -25,5 +25,6 @@ qcom-camss-objs +=3D \ camss-video.o \ camss-format.o \ camss-tpg.o \ + camss-tpg-gen1.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 581399b6a767fc2ba0764dc0f5228e737cdd0d67..2af4fc039948a1a43a2e4eed330= 04cbfd6bf66fb 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -69,6 +69,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_NUM_EN 27 +#define CSI2_RX_CFG0_TPG_NUM_SEL 28 =20 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -112,7 +114,10 @@ static void __csid_configure_rx(struct csid_device *cs= id, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; + struct tpg_device *tpg; =20 + camss =3D csid->camss; val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; @@ -120,6 +125,18 @@ static void __csid_configure_rx(struct csid_device *cs= id, if (IS_CSID_690(csid) && (vc > 3)) val |=3D 1 << CSI2_RX_CFG0_VC_MODE; =20 + if (camss->tpg) { + tpg =3D &camss->tpg[phy->csiphy_id]; + + if (tpg->testgen.mode > 0) { + val |=3D (phy->csiphy_id + 1) << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 1 << CSI2_RX_CFG0_TPG_NUM_EN; + } else { + val |=3D 0 << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 0 << CSI2_RX_CFG0_TPG_NUM_EN; + } + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..a8899ccac52b0ad66296182f3fb= 70ad34bb1f711 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-tpg-gen1.c + * + * Qualcomm MSM Camera Subsystem - TPG (Test Patter Generator) Module + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +#define TPG_HW_VERSION 0x0 +#define HW_VERSION_STEPPING 0 +#define HW_VERSION_REVISION 16 +#define HW_VERSION_GENERATION 28 + +#define TPG_HW_STATUS 0x4 + +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_CTRL 0x64 +#define TPG_CTRL_TEST_EN 0 +#define TPG_CTRL_PHY_SEL 3 +#define TPG_CTRL_NUM_ACTIVE_LANES 4 +#define TPG_CTRL_VC_DT_PATTERN_ID 6 +#define TPG_CTRL_OVERLAP_SHDR_EN 10 +#define TPG_CTRL_NUM_ACTIVE_VC 30 +#define NUM_ACTIVE_VC_0_ENABLED 0 +#define NUM_ACTIVE_VC_0_1_ENABLED 1 +#define NUM_ACTIVE_VC_0_1_2_ENABLED 2 +#define NUM_ACTIVE_VC_0_1_3_ENABLED 3 + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +#define TPG_VC_n_CFG0_VC_NUM 0 +#define TPG_VC_n_CFG0_NUM_ACTIVE_DT 8 +#define NUM_ACTIVE_SLOTS_0_ENABLED 0 +#define NUM_ACTIVE_SLOTS_0_1_ENABLED 1 +#define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2 +#define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3 +#define TPG_VC_n_CFG0_NUM_BATCH 12 +#define TPG_VC_n_CFG0_NUM_FRAMES 16 + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) + +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) + +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +#define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN 0 +#define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN 3 +#define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN 4 +#define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN 5 +#define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD 8 +#define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN 16 +#define TPG_VC_n_COLOR_BARS_CFG_SIZE_X 24 +#define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y 28 + +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +#define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT 0 +#define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH 16 + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +#define TPG_VC_m_DT_n_CFG_1_DATA_TYPE 0 +#define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK 8 +#define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK 16 + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +#define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE 0 +#define TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD 4 +#define TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT 28 + +#define TPG_VC_n_COLOR_BAR_CFA_COLOR0(n) (0xB0 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR1(n) (0xB4 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR2(n) (0xB8 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR3(n) (0xBC + (n) * 0x60) + +/* Line offset between VC(n) and VC(n-1), n form 1 to 3 */ +#define TPG_VC_n_SHDR_CFG (0x84 + (n) * 0x60) + +#define TPG_TOP_IRQ_STATUS 0x1E0 +#define TPG_TOP_IRQ_MASK 0x1E4 +#define TPG_TOP_IRQ_CLEAR 0x1E8 +#define TPG_TOP_IRQ_SET 0x1EC +#define TPG_IRQ_CMD 0x1F0 +#define TPG_CLEAR 0x1F4 + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg =3D &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 lane_cnt =3D tpg->res->lane_cnt; + u8 i; + u8 dt_cnt =3D 0; + u32 val; + + /* Loop through all enabled VCs and configure stream for each */ + for (i =3D 0; i < tpg->res->vc_cnt; i++) { + input_format =3D &tpg->fmt[MSM_TPG_PAD_SRC + i]; + format =3D tpg_get_fmt_entry(tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + + val =3D (input_format->height & 0xffff) << TPG_VC_m_DT_n_CFG_0_FRAME_HEI= GHT; + val |=3D (input_format->width & 0xffff) << TPG_VC_m_DT_n_CFG_0_FRAME_WID= TH; + writel_relaxed(val, tpg->base + TPG_VC_m_DT_n_CFG_0(i, dt_cnt)); + + val =3D format->data_type << TPG_VC_m_DT_n_CFG_1_DATA_TYPE; + writel_relaxed(val, tpg->base + TPG_VC_m_DT_n_CFG_1(i, dt_cnt)); + + val =3D (tg->mode - 1) << TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE; + val |=3D 0xBE << TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD; + val |=3D format->encode_format << TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT; + writel_relaxed(val, tpg->base + TPG_VC_m_DT_n_CFG_2(i, dt_cnt)); + + writel_relaxed(0xA00, tpg->base + TPG_VC_n_COLOR_BARS_CFG(i)); + + writel_relaxed(0x4701, tpg->base + TPG_VC_n_HBI_CFG(i)); + writel_relaxed(0x438, tpg->base + TPG_VC_n_VBI_CFG(i)); + + writel_relaxed(0x12345678, tpg->base + TPG_VC_n_LSFR_SEED(i)); + + /* configure one DT, infinite frames */ + val =3D i << TPG_VC_n_CFG0_VC_NUM; + val |=3D 0 << TPG_VC_n_CFG0_NUM_FRAMES; + writel_relaxed(val, tpg->base + TPG_VC_n_CFG0(i)); + } + + writel_relaxed(1, tpg->base + TPG_TOP_IRQ_MASK); + + val =3D 1 << TPG_CTRL_TEST_EN; + val |=3D 0 << TPG_CTRL_PHY_SEL; + val |=3D (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; + val |=3D 0 << TPG_CTRL_VC_DT_PATTERN_ID; + val |=3D (tpg->res->vc_cnt - 1) << TPG_CTRL_NUM_ACTIVE_VC; + writel_relaxed(val, tpg->base + TPG_CTRL); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + writel_relaxed(0, tpg->base + TPG_CTRL); + writel_relaxed(0, tpg->base + TPG_TOP_IRQ_MASK); + writel_relaxed(1, tpg->base + TPG_TOP_IRQ_CLEAR); + writel_relaxed(1, tpg->base + TPG_IRQ_CMD); + writel_relaxed(1, tpg->base + TPG_CLEAR); +} + +static void tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + if (enable) + tpg_stream_on(tpg); + else + tpg_stream_off(tpg); +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val > 0 && val <=3D TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode =3D val; + + return 0; +} + +/* + * tpg_hw_version - tpg hardware version query + * @tpg: tpg device + * + * Return HW version or error + */ +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version; + u32 hw_gen; + u32 hw_rev; + u32 hw_step; + + hw_version =3D readl_relaxed(tpg->base + TPG_HW_VERSION); + hw_gen =3D (hw_version >> HW_VERSION_GENERATION) & 0xF; + hw_rev =3D (hw_version >> HW_VERSION_REVISION) & 0xFFF; + hw_step =3D (hw_version >> HW_VERSION_STEPPING) & 0xFFFF; + dev_dbg(tpg->camss->dev, "tpg HW Version =3D %u.%u.%u\n", + hw_gen, hw_rev, hw_step); + + return hw_version; +} + +/* + * tpg_isr - tpg module interrupt service routine + * @irq: Interrupt line + * @dev: tpg device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t tpg_isr(int irq, void *dev) +{ + struct tpg_device *tpg =3D dev; + u32 val; + + val =3D readl_relaxed(tpg->base + TPG_TOP_IRQ_STATUS); + writel_relaxed(val, tpg->base + TPG_TOP_IRQ_CLEAR); + writel_relaxed(1, tpg->base + TPG_IRQ_CMD); + + return IRQ_HANDLED; +} + +/* + * tpg_reset - Trigger reset on tpg module and wait to complete + * @tpg: tpg device + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_reset(struct tpg_device *tpg) +{ + writel_relaxed(0, tpg->base + TPG_CTRL); + writel_relaxed(0, tpg->base + TPG_TOP_IRQ_MASK); + writel_relaxed(1, tpg->base + TPG_TOP_IRQ_CLEAR); + writel_relaxed(1, tpg->base + TPG_IRQ_CMD); + writel_relaxed(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes =3D testgen_payload_modes; + tpg->testgen.nmodes =3D TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 =3D { + .configure_stream =3D tpg_configure_stream, + .configure_testgen_pattern =3D tpg_configure_testgen_pattern, + .hw_version =3D tpg_hw_version, + .isr =3D tpg_isr, + .reset =3D tpg_reset, + .subdev_init =3D tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 34f71039038e881ced9c9f06bd70915b5c5f610f..ced31e3655a52a7b2e55b109085= cf24a9e230f1d 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2935,6 +2935,53 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, }; =20 +static const struct camss_subdev_resources tpg_res_8775p[] =3D { + /* TPG0 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx" }, + .clock_rate =3D { { 400000000 } }, + .reg =3D { "tpg0" }, + .interrupt =3D { "tpg0" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG1 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx" }, + .clock_rate =3D { { 400000000 } }, + .reg =3D { "tpg1" }, + .interrupt =3D { "tpg1" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG2 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx" }, + .clock_rate =3D { { 400000000 } }, + .reg =3D { "tpg2" }, + .interrupt =3D { "tpg2" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] =3D { /* CSID0 */ { @@ -4445,6 +4492,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; =20 + if (camss->res->version =3D=3D CAMSS_8775P) { + camss->tpg =3D devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid =3D devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->cs= id), GFP_KERNEL); if (!camss->csid) @@ -4638,11 +4692,13 @@ static const struct camss_resources sa8775p_resourc= es =3D { .version =3D CAMSS_8775P, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8775p, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sa8775p, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_sa8775p, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8775p), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_sa8775p), --=20 2.34.1