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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b5e3cb7sm2002195ad.17.2025.07.17.16.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 16:28:51 -0700 (PDT) From: Jessica Zhang Date: Thu, 17 Jul 2025 16:28:43 -0700 Subject: [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250717-dp_mst_bindings-v3-1-72ce08285703@oss.qualcomm.com> References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> In-Reply-To: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Jessica Zhang , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, Rob Clark Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b5e3cb7sm2002195ad.17.2025.07.17.16.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 16:28:56 -0700 (PDT) From: Jessica Zhang Date: Thu, 17 Jul 2025 16:28:45 -0700 Subject: [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250717-dp_mst_bindings-v3-3-72ce08285703@oss.qualcomm.com> References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> In-Reply-To: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Jessica Zhang , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, Rob Clark Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; a=ed25519-sha256; t=1752794927; l=7576; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=Z7Q5MhFNW++3sg2l+MY10L8IMh9EAArq7s0Yr3E5sqQ=; b=bXvkMgRG/fOCiubHjM5Jn0LKe5/Q9lqISkXucJ1CRsxFEN778kZWlM3xXVklsfaaCbVIwiSFB ycoZ/YlAjoBCOiAORpn6mMaJdtIv28Sf0ik3WqYNt6hPeRhc20TpUZb X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDIwNiBTYWx0ZWRfXwrrZjX37D7aU 3pvXGO7JfANZdbensnFcznZ9WdeaCHYBifGdXIgAwVaFnWQBh0JUX1FkzuZ2RloVF0zBVIXboBP H+mLMxM5tQBwpLv7QKm366bGmPahr3Sg0z8kcWtP9Z/j3kr0MBBzL6OM7ctyYebM2noLaryi634 7pm4YT6NOVtaPh7Fe56lJmSapZP5ko3hKehBg++ucPJZH4IW/Qur0YRF54mGUPTU+sTrXvdI5q+ 1xJazbjHsrBxR0JsTdnwHHOBdnc21ncxGX6y/1I15hEZaK3/VfTjiaXBpQ4VDAt5DYJn4g8RKJT xfg7D0iuSDGLPoFco9TnOuj7gcXOwOWthwyN7SAP+8IphnnqnDTUKKyn04IPo1/cmGcBfm8pYQo yyIGhDyz4pD0hgWE6Uitj+40BVWUPUeiQl1YrJPANj722gVl4WDSEsQpHi8inVTyOmlmAOPG X-Proofpoint-GUID: p_pn2UIyzZ0rdJm5Zz9IkK94z3_73V5z X-Proofpoint-ORIG-GUID: p_pn2UIyzZ0rdJm5Zz9IkK94z3_73V5z X-Authority-Analysis: v=2.4 cv=Y+r4sgeN c=1 sm=1 tr=0 ts=6879873a cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=y-iibUknMj623qMt5boA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_04,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=987 phishscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170206 From: Abhinav Kumar Current documentation of assigned-clock-parents for dp controller does not describe its functionality correctly making it harder to extend it for adding multiple streams. Instead of fixing up the documentation, drop the assigned-clock-parents and assigned-clocks along with the usages in the chipset specific MDSS yaml files. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang --- .../devicetree/bindings/display/msm/dp-controller.yaml | 15 -----------= ---- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 4 ---- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 5 ----- .../devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml | 3 --- .../devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ------ .../devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml | 5 ----- .../devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml | 5 ----- 7 files changed, 43 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 4676aa8db2f4..d8d94f62c102 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -73,16 +73,6 @@ properties: - const: ctrl_link_iface - const: stream_pixel =20 - assigned-clocks: - items: - - description: link clock source - - description: pixel clock source - - assigned-clock-parents: - items: - - description: phy 0 parent - - description: phy 1 parent - phys: maxItems: 1 =20 @@ -209,11 +199,6 @@ examples: "ctrl_link", "ctrl_link_iface", "stream_pixel"; =20 - assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - - assigned-clock-parents =3D <&dp_phy 0>, <&dp_phy 1>; - phys =3D <&dp_phy>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index 1053b3bc4908..2dc76a074da1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -391,10 +391,6 @@ examples: "ctrl_link_iface", "stream_pixel"; =20 - assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents =3D <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy= 1>; - phys =3D <&mdss0_dp0_phy>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.= yaml index 870144b53cec..eef5627133db 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -214,11 +214,6 @@ examples: "ctrl_link_iface", "stream_pixel"; =20 - assigned-clocks =3D <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents =3D <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK= _CLK>, - <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DI= V_CLK>; - phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml index 7a0555b15ddf..a2b71b476357 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml @@ -267,9 +267,6 @@ examples: <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents =3D <&dp_phy 0>, <&dp_phy 1>; phys =3D <&dp_phy>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 2947f27e0585..9e52ac9c0eb4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -296,9 +296,6 @@ examples: "ctrl_link", "ctrl_link_iface", "stream_pixel"; - assigned-clocks =3D <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; - assigned-clock-parents =3D <&mdss_edp_phy 0>, <&mdss_edp_phy 1= >; =20 phys =3D <&mdss_edp_phy>; phy-names =3D "dp"; @@ -387,9 +384,6 @@ examples: "ctrl_link", "ctrl_link_iface", "stream_pixel"; - assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents =3D <&dp_phy 0>, <&dp_phy 1>; phys =3D <&dp_phy>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml index 13c5d5ffabde..eafea2fe1c95 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml @@ -399,11 +399,6 @@ examples: "ctrl_link_iface", "stream_pixel"; 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b5e3cb7sm2002195ad.17.2025.07.17.16.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 16:28:58 -0700 (PDT) From: Jessica Zhang Date: Thu, 17 Jul 2025 16:28:46 -0700 Subject: [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250717-dp_mst_bindings-v3-4-72ce08285703@oss.qualcomm.com> References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> In-Reply-To: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Jessica Zhang , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, Rob Clark Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; a=ed25519-sha256; t=1752794927; l=9121; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=lan3Y5KBTR4cC/ZtMB5SWaedJPpSyDvP8y8bQq9zCvE=; b=03eVzWqFidZ25JCpT9tqz5QUjDSx8ROwLmP2YHgRtifUoqZFZLYxbfvtojjYFYbp6auumdoDV x1KCbFJSL3pB3unjE//ooy8DahduBmsIAsAICXBdlJl0Er/9xwN22r0 X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Authority-Analysis: v=2.4 cv=dKimmPZb c=1 sm=1 tr=0 ts=6879873c cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iZctjB8Tiv542dVYzCoA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: S2BzONdcWZnI7m_v72M0BLqM-TQ2tCLU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDIwNiBTYWx0ZWRfX0CSvmMa6VH3F /+JZ3IJFiHskb81TkppZZE+dYHf9d9Jiq/+T5hOCiD58b95f22BCt52ubEtFG6QLznVaoB3oIAh voYQmvHyKiW3yXvUKMTtv473kfTkYWOLmSQWKZ8P+qbmE5BZhZZ9x0NkIXDvlWYIVfkIWyX2WB7 wnRxB0vUz53ENVwgv7N4JSMGWxWSAVGgWAvc9YQN5aXGF6yEXQoQRrbOFrKk/mV90/pngBCuWeY hwUNOqduHXX9uJ59dAjqnNDe+AkDp4pOMSP1OzCQz3gLPCEUfNY7ABo8duejtX9w4H2ALZtcAlg i3/ig/18JxCWbka5djpeoNmPVrm53lHuxQb6bl+0fsZJdC+MS6X3QJyj2jG20GeGL5/HjooChIo TWQ5ZOeJIgtDhk8kfV6lmIXq1BT5giPPnrUcH7GIDaY1hR6cyy7uqEBj9U6RLT4c1uWwvgP6 X-Proofpoint-ORIG-GUID: S2BzONdcWZnI7m_v72M0BLqM-TQ2tCLU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_04,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170206 From: Abhinav Kumar On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, the display port controller can support more than one pixel stream (multi-stream transport). These chipsets can support up to 4 stream pixel clocks for display port controller. To support MST on these platforms, add the appropriate stream pixel clock bindings Since this mode is not supported on all chipsets, add exception rules and min/max items to clearly mark which chipsets support only SST mode (single stream) and which ones support MST. Note: On chipsets that do support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. In addition, many chipsets depend on the "sm8350-dp" compatibility string but not all (ex. SM6350) support MST. Because of these reasons, the min/maxItem for MST-supported platforms is a range of 5-8. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang --- .../bindings/display/msm/dp-controller.yaml | 36 ++++++++++++++++++= +++- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- 6 files changed, 59 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index d8d94f62c102..2893f097df82 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -58,20 +58,28 @@ properties: maxItems: 1 =20 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock + - description: Display Port stream 2 Pixel clock + - description: Display Port stream 3 Pixel clock =20 clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel + - const: stream_2_pixel + - const: stream_3_pixel =20 phys: maxItems: 1 @@ -173,6 +181,32 @@ allOf: required: - "#sound-dai-cells" =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + - qcom,sc7280-dp + - qcom,sc8180x-dp + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + - qcom,sm8150-dp + - qcom,sm8350-dp + - qcom,sm8650-dp + - qcom,x1e80100-dp + then: + properties: + clocks: + minItems: 5 + maxItems: 8 + + else: + properties: + clocks: + minItems: 5 + maxItems: 5 + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index 2dc76a074da1..0af1e5cd1691 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -384,12 +384,18 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>, + <&dispcc_dptx0_pixel2_clk>, + <&dispcc_dptx0_pixel3_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; =20 phys =3D <&mdss0_dp0_phy>; phy-names =3D "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.= yaml index eef5627133db..0a8bda583469 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -207,12 +207,14 @@ examples: <&dispcc_disp_cc_mdss_dptx0_aux_clk>, <&dispcc_disp_cc_mdss_dptx0_link_clk>, <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; phy-names =3D "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 9e52ac9c0eb4..f8fffc168a71 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -378,12 +378,14 @@ examples: <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; phys =3D <&dp_phy>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index 0858dd61fb0f..0bc0edc41341 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -401,12 +401,14 @@ examples: <&disp_cc_mdss_dptx0_aux_clk>, <&disp_cc_mdss_dptx0_link_clk>, <&disp_cc_mdss_dptx0_link_intf_clk>, - <&disp_cc_mdss_dptx0_pixel0_clk>; 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b5e3cb7sm2002195ad.17.2025.07.17.16.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 16:29:00 -0700 (PDT) From: Jessica Zhang Date: Thu, 17 Jul 2025 16:28:47 -0700 Subject: [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250717-dp_mst_bindings-v3-5-72ce08285703@oss.qualcomm.com> References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> In-Reply-To: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Jessica Zhang , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, Rob Clark Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; a=ed25519-sha256; t=1752794927; l=26884; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=Eo6Wy62P8HtW0Q4HjhWR3xKbDOiW9UUfKZH66pv4erc=; b=J7086Q2E1oZhhsTkVGHCxkYRAp51smmyKiw2239g5+4gsg4jvR8VUm8FdNlIHzx+bfEs+7Dmi DRBkmYPYQvIAFePSFwq62FVbLNn56oaEM8ZpDgfW2ejtTmtx7+8tqEy X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-ORIG-GUID: q_Xz1oQo33SX8OHmsNv4VFyOe9VUQjtJ X-Authority-Analysis: v=2.4 cv=RtXFLDmK c=1 sm=1 tr=0 ts=6879873f cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=M642VWYP8yQGdStLr8gA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDIwNiBTYWx0ZWRfX3UeiGDjBMomE WDDAC6CBaoU5cpWHTqNErrDstp+q4SsgUKCfdKSc7rY8KkFqiMhpCcM/PR0qIo+TKs/Mzt3yC67 9/Bi/5MTthu7fCVReKlBcT1rJYtudeKuJ/bCA3LSJR5Dbsnav7SqNrT8SLHg87D5+lMbxdDac76 IygKjadoUZuuGDPMo1wVkKHq59pzGK75Q63cCJLuBqyVH3y10BVfiliQ5L6LKky4IOtdneXD20a xFS/u91HMooDL20uGMCKbob2WpEpqtkuaTiJZS8pb6JaatXlxsgyIxi+PEoIECa9XBgzI7HlVq5 P4JWDOpt4UjRAqBiE00VPR6wXi6pgfcC2N9gB6KtMz/XugoJqkegmkZwMiGU3vvOkIZBv4I4DBz s4KUmoS48tp5lBbeZ7NO7DawcJa3o/gB71kMTPcH4pfHVCyUkJEsTwcYxgkh2OVf0GMfVZNS X-Proofpoint-GUID: q_Xz1oQo33SX8OHmsNv4VFyOe9VUQjtJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_04,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxlogscore=514 priorityscore=1501 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170206 The following chipsets support 2 total pixel streams: - sa8775p (on mdss_dp1) - sc8180x - sc8280xp (mdss_dp0-2 only) - sm8150 - sm8350 - sm8450 - sm8650 - x1e80100 The following chipset also supports 4 total pixel streams: - sa8775p (mdss_dp0 only) Add the appropriate amount of pixel stream clocks for their respective displayport-controllers. Signed-off-by: Jessica Zhang --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 ++++++++++++---- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 +++++++--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-------= ---- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++----- 12 files changed, 167 insertions(+), 69 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 45f536633f64..2c85eb2fc79a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4237,15 +4237,28 @@ mdss0_dp0: displayport-controller@af54000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; phys =3D <&mdss0_dp0_phy>; phy-names =3D "dp"; =20 @@ -4316,15 +4329,20 @@ mdss0_dp1: displayport-controller@af5c000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp1_phy 0>, + <&mdss0_dp1_phy 1>, + <&mdss0_dp1_phy 1>; phys =3D <&mdss0_dp1_phy>; phy-names =3D "dp"; =20 diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/q= com/sar2130p.dtsi index b0e342810ae7..96090a948ade 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -2139,16 +2139,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index b1cc3bc1aec8..48b6a17dcea0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5012,15 +5012,19 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; phy-names =3D "dp"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index b84e47a461a0..ca188c7f1f26 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3233,16 +3233,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; @@ -3311,16 +3315,20 @@ mdss_dp1: displayport-controller@ae98000 { <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 87555a119d94..11ea2fa0b853 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 { <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; @@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 { <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 { <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss0>; interrupts =3D <14>; phys =3D <&mdss0_dp2_phy>; @@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp2_phy 1>; operating-points-v2 =3D <&mdss0_dp2_opp_table>; =20 #sound-dai-cells =3D <0>; @@ -5669,10 +5682,12 @@ mdss1_dp0: displayport-controller@22090000 { <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss1>; interrupts =3D <12>; phys =3D <&mdss1_dp0_phy>; @@ -5680,8 +5695,11 @@ mdss1_dp0: displayport-controller@22090000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; operating-points-v2 =3D <&mdss1_dp0_opp_table>; =20 #sound-dai-cells =3D <0>; @@ -5741,10 +5759,12 @@ mdss1_dp1: displayport-controller@22098000 { <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss1>; interrupts =3D <13>; phys =3D <&mdss1_dp1_phy>; @@ -5752,8 +5772,11 @@ mdss1_dp1: displayport-controller@22098000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; operating-points-v2 =3D <&mdss1_dp1_opp_table>; =20 #sound-dai-cells =3D <0>; @@ -5813,10 +5836,12 @@ mdss1_dp2: displayport-controller@2209a000 { <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss1>; interrupts =3D <14>; phys =3D <&mdss1_dp2_phy>; @@ -5824,8 +5849,11 @@ mdss1_dp2: displayport-controller@2209a000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp2_phy 1>; operating-points-v2 =3D <&mdss1_dp2_opp_table>; =20 #sound-dai-cells =3D <0>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index cdb47359c4c8..3a21a2e2c04d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3894,16 +3894,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index f0d18fd37aaf..fc7c610c15d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4774,16 +4774,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 971c828a7555..6a930292edd3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2872,16 +2872,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 54c6d0fdb2af..b0680ef30c1f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 71a7e3b57ece..226c457338d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3545,16 +3545,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 495ea9bfd008..72c63afe9029 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5388,16 +5388,20 @@ mdss_dp0: displayport-controller@af54000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&dp_opp_table>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a8eb4c5fe99f..e86b6cb20096 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5306,16 +5306,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&mdss_dp0_opp_table>; @@ -5389,16 +5393,20 @@ mdss_dp1: displayport-controller@ae98000 { <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&mdss_dp1_opp_table>; @@ -5472,16 +5480,20 @@ mdss_dp2: displayport-controller@ae9a000 { <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-330a90d4ffasm5480891fa.6.2025.07.19.02.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jul 2025 02:14:46 -0700 (PDT) From: Dmitry Baryshkov To: Jessica Zhang Cc: Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou Subject: [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P Date: Sat, 19 Jul 2025 12:14:45 +0300 Message-Id: <20250719091445.3126775-1-dmitry.baryshkov@oss.qualcomm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE5MDA5MSBTYWx0ZWRfX9T/NKwnsq6HD M4qaNqwpXhuMpzO7f9WxIWAW7SXE7HFnDuBNpDkdMoNxIqOHhs9ObULZGJfLfM/aDYj+YOa3845 A+yf2YnO8df2rfZCeI6OIh2O+9U9oRXLLcD7YmNPpxNJXN5oHKeAz1hfamDlof10SbDsHAW3knk n4GjZQCaneYolflJinRXq4MtcFKANRBZNXUprj2Q7ItbAHaWh5/UIpTG/0ctC0+EJZdbwTxbpal e7io1E5EsK0ofwynsbCyTIjG2w29ojei70kBJVea+mGjOVhoawUW5+H4ZF5oTHbFmzNmycfqHiB 7ykDF3eF/FWrDffMN/w9+qM2/Fs+DxEg0oYXnOMCT31yoAOeV8YIwxX6nTNTRjQXtEWOg07D+2J Za1FwaV6r7TRLmqc3RavysdIYNkFfz9+VfQYrhegZrXLFBMxXKeskfuJxNy2XGawQIXHmo8M X-Authority-Analysis: v=2.4 cv=Jb68rVKV c=1 sm=1 tr=0 ts=687b6209 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=jb3qBSlP78txkkNFhucA:9 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: PTnTiaqN_d5iwhhw9YVMEgrppT23J2Fv X-Proofpoint-ORIG-GUID: PTnTiaqN_d5iwhhw9YVMEgrppT23J2Fv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-19_01,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507190091 Content-Type: text/plain; charset="utf-8" On Qualcomm SA8775P and X1E80100 the DP controller might be driving either a DisplayPort or a eDP sink (depending on the PHY that is tied to the controller). Reflect that in the schema. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) --- Jessica, your X1E8 patch also triggers warnings for several X1E8-based laptops. Please include this patch into the series (either separately or, better, by squashing into your first patch). --- .../bindings/display/msm/dp-controller.yaml | 26 ++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 4676aa8db2f4..55e37ec74591 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -176,12 +176,26 @@ allOf: properties: "#sound-dai-cells": false else: - properties: - aux-bus: false - reg: - minItems: 5 - required: - - "#sound-dai-cells" + if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + - qcom,x1e80100-dp + then: + oneOf: + - required: + - aux-bus + - required: + - "#sound-dai-cells" + else: + properties: + aux-bus: false + reg: + minItems: 5 + required: + - "#sound-dai-cells" =20 additionalProperties: false =20 --=20 2.39.5