From nobody Mon Oct 6 22:52:30 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9EC932F548C; Wed, 16 Jul 2025 16:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682360; cv=none; b=r+8umwHYefSJIpxn0MXhPxBj8OIs0Xzsj/1cEWWQAohuzpc0X9FC0goFg5pSM6rsiVWQk4hObQI8qgFxcG3EW1FoUZ5GLxuQzblGTJbaN3pP7uGMskSj3f8vUglXNJXmwx9aWll1KqwDF2clVRoBi9xnn/HkVqrPjsJ94LEtgTE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682360; c=relaxed/simple; bh=Nw4LXknYCgQgu+MQeSZw1L6tp0DyfN/viD1SQX8qois=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=WphtbqffQD/3f84O6t04XVyOOZmlUQFSj8mQaWsaqvglMN2VqRoUAPL2byJmZZc7xq9N+a3QVomjQvoRKFYjsadxGk+xFHlMmv+mVGAIojRpzRdtuEyBHjDbgxoWzVWi3+X6ORY6cfUw6lWBclA1jkfrnSN9c+Pa/lDLeBx6htA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Z0utB+Ja; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Z0utB+Ja" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version: Content-Type; bh=aKqO8ZFw8Cu+RbQvK9ETURYLI9DYzDI2/InISu28Jh4=; b=Z0utB+JaTQaiB2Y4aP1kjvV9fOM5Px33vjnMCcQ/9q454nqE/36/RHpuCatWN6 3InPT/7zFQF+9M2PmBARQSf5dycOMDtS9bJ6GievAVa/OagnR+JXd6bgpLYKczQH 7fcT3CpFMq5MCxpARYTHEWWcUNTYccx9/6ahTmlU4/Af0= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgAnMkhWz3doF6jWAw--.24466S9; Thu, 17 Jul 2025 00:12:13 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 7/7] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode Date: Thu, 17 Jul 2025 00:12:03 +0800 Message-Id: <20250716161203.83823-8-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S9 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1rCrWfWF15ArWUXF18Xwb_yoWxuFW3pF W5ua4SkF40qrW7uFsrA3W5ZrnxtFnIv347Aa92kw15uF129FyUGFyIva43KF1akrs7u3W7 XrWDtrsa93ZxtrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEwvtiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwaMo2h3yadzKwABsa The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam Reviewed-by: Ilpo J=C3=A4rvinen --- Changes since v8 ~ v13: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.c= om - Kconfig add "select PCI_HOST_HELPERS" --- .../pci/controller/cadence/pcie-cadence-ep.c | 38 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 8ab6cf70c18e..4f0d2ee5e513 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -21,12 +21,13 @@ =20 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; =20 if (vfn =3D=3D 0) return fn; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn =3D fn + first_vf_offset + ((vfn - 1) * stride); @@ -38,10 +39,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *ep= c, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u32 reg; + u16 cap; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -227,9 +229,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u= 8 fn, u8 vfn, u8 nr_irqs) struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* @@ -249,9 +252,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u= 8 fn, u8 vfn) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Validate that the MSI feature is actually enabled. */ @@ -272,9 +276,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, = u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -292,9 +297,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, = u8 fn, u8 vfn, { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -380,11 +386,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie= _ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask =3D 0xff; + u8 msi_count, cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -432,14 +438,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u64 pci_addr, pci_addr_mask =3D 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -482,16 +488,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie =3D &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask =3D 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf =3D &ep->epf[fn]; if (vfn > 0) epf =3D &epf->epf[vfn - 1]; @@ -565,7 +571,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs =3D sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -589,12 +597,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cap + PCI_EXP_DEVCAP, value); } } =20 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 38f7a8cdf7f1..f0fdeb3863f1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) =20 -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */ --=20 2.25.1