From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C834F263F5F; Wed, 16 Jul 2025 16:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682355; cv=none; b=M2PWagqGCAuYFqEbx9kC2aWUjEqlRcQsPD1sRlv2gMVoHtH5G5cXMHCQHztgsV9ZgGpZOcKb6Oy2WZgr89KPCQmBkWl76rD48nBZPzvzs832/7BDXUXf8lFeqQGHlP5rfjKirbCQp3IqcUMez1KrYSPmfGRSmBTg3DrkohRfLLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682355; c=relaxed/simple; bh=b3SoGKLeVxEoNXjs8FeqCT0UfXpUtfv5yFWrYc7kX/k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TGww9A/5L8H19uwZ4oca+NW+9SFYtitxUcwOVaP2I3ATIqbQKhdBj6lBp+wbxRSa9dDPhGuYu/IEJwS9QLxnGjRKfnY6jpWS3xsfhhG57lF/gcdPm+6w4vhEosJICQYZxmVYfpyJQ1mHb6Odds3ZpYIpCJnHOt/gG3tbN9RUDNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=anYL3Ya2; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="anYL3Ya2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ws X/XzDFYl5gZ/hOmtj100DtUZjYraRlhsA9nZOlLWg=; b=anYL3Ya2KwQipXP9AY z05KQ94RM5MyhKou7IBvTz7BxZ7tjOO9gSepQQzBZdIZS7Xz/ksXQDzaWNOr0BQ/ pfBLSGckySTexiRLjdUCMJs4HULIDLq44W1zEO93Fw8KEupNH3hF4G4NMnfi4to7 nfAsscCGChLndCdH1E0hMsETM= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgAnMkhWz3doF6jWAw--.24466S3; Thu, 17 Jul 2025 00:12:09 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 1/7] PCI: Introduce generic bus config read helper function Date: Thu, 17 Jul 2025 00:11:57 +0800 Message-Id: <20250716161203.83823-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7uF18WF13CFW8ZFyfAF4rAFb_yoW8KFW8pF W5AF13Cr48JF13JFsYvay8CFy5GFZ7tay7GrWxJ3sxZF43Ca4UAasFgFy5Xr12grWDur1S van5GFyUC3Z8AFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zM6wZUUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQwSMo2h3yP1-BwAAs6 Content-Type: text/plain; charset="utf-8" The primary PCI config space accessors are tied to the size of the read (byte/word/dword). Upcoming refactoring of PCI capability discovery logic requires passing a config accessor function that must be able to perform read with different sizes. Add any size config space read accessor pci_bus_read_config() to allow giving it as the config space accessor to the upcoming PCI capability discovery macro. Reconstructs the PCI function discovery logic to prepare for unified configuration of access modes. No function changes are intended. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam --- Changes since v13: - None Changes since v12: - Optimize the function return values. Changes since v9 ~ v11: - None Changes since v8: - The new split is patch 1/6. - The patch commit message were modified. --- drivers/pci/access.c | 15 +++++++++++++++ drivers/pci/pci.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index b123da16b63b..ba66f55d2524 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -85,6 +85,21 @@ EXPORT_SYMBOL(pci_bus_write_config_byte); EXPORT_SYMBOL(pci_bus_write_config_word); EXPORT_SYMBOL(pci_bus_write_config_dword); =20 +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 siz= e, + u32 *val) +{ + struct pci_bus *bus =3D priv; + + if (size =3D=3D 1) + return pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); + else if (size =3D=3D 2) + return pci_bus_read_config_word(bus, devfn, where, (u16 *)val); + else if (size =3D=3D 4) + return pci_bus_read_config_dword(bus, devfn, where, val); + else + return PCIBIOS_BAD_REGISTER_NUMBER; +} + int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 12215ee72afb..e7d31ed56731 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -90,6 +90,8 @@ extern bool pci_early_dump; bool pcie_cap_has_lnkctl(const struct pci_dev *dev); bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); bool pcie_cap_has_rtctl(const struct pci_dev *dev); +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 siz= e, + u32 *val); =20 /* Functions internal to the PCI core code */ =20 --=20 2.25.1 From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3952E2F5326; Wed, 16 Jul 2025 16:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682363; cv=none; b=smcUchgndjmstkp5/5hj+qFw40Vt7qCsLwA+DviDNeJCP2Mcpae3dzq/oYnnqDId25+J3WlLopwCzhEOnx8o1PwgErLbFN7SM1Z3xVWDRVOtrZjNBzsyNCM+VyiRytvdsMR0rE8dIKWX2D+p0IVHJNkAoEPwgtVSV4+GtwYJfaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682363; c=relaxed/simple; bh=MuAVVOvs+dYPPYaUff6Ssjm8q8yOoAflNmFG0bj6b9M=; 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Thu, 17 Jul 2025 00:12:09 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 2/7] PCI: Clean up __pci_find_next_cap_ttl() readability Date: Thu, 17 Jul 2025 00:11:58 +0800 Message-Id: <20250716161203.83823-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7tFyUuF4UZw1fZr45GFWUXFb_yoW8tw43pF 98Ca47Ar48JF4xCw4vk3W2yry3XayDCrW8GrWagwn8uFy7t3W8twsI9F1ayFnrXrZ293W5 XFyqv3s0gF90yaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pitCztUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwiMo2h3yady6wAAsU Content-Type: text/plain; charset="utf-8" Refactor the __pci_find_next_cap_ttl() to improve code clarity: - Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF. - Use ALIGN_DOWN() for position alignment instead of manual bitmask. - Extract PCI capability fields via FIELD_GET() with standardized masks. - Add necessary headers (linux/align.h). No functional changes intended. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam --- Changes since v13: - None Changes since v12: - Modify the commit message and the code format issue. Changes since v11: - None Changes since v10: - Remove #include and add macro definition comments. Changes since v9: - None Changes since v8: - Split into patch 1/6, patch 2/6. - The --- drivers/pci/pci.c | 9 +++++---- include/uapi/linux/pci_regs.h | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e9448d55113b..1d1d147d007a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -432,17 +433,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus= , unsigned int devfn, pci_bus_read_config_byte(bus, devfn, pos, &pos); =20 while ((*ttl)--) { - if (pos < 0x40) + if (pos < PCI_STD_HEADER_SIZEOF) break; - pos &=3D ~3; + pos =3D ALIGN_DOWN(pos, 4); pci_bus_read_config_word(bus, devfn, pos, &ent); =20 - id =3D ent & 0xff; + id =3D FIELD_GET(PCI_CAP_ID_MASK, ent); if (id =3D=3D 0xff) break; if (id =3D=3D cap) return pos; - pos =3D (ent >> 8); + pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); } return 0; } diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a3a3e942dedf..5f9e7633e6e0 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -207,6 +207,9 @@ =20 /* Capability lists */ =20 +#define PCI_CAP_ID_MASK 0x00ff /* Capability ID mask */ +#define PCI_CAP_LIST_NEXT_MASK 0xff00 /* Next Capability Pointer mask */ + #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ --=20 2.25.1 From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 396092F5C4A; Wed, 16 Jul 2025 16:12:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682362; cv=none; b=u6qT92FxuPMsmt5F0OdLmJy8jRqRTy9iSds43o5GilPdOwg1GJt0bQ4zWmltjFR2aFJ9ew56pgal4S4wq5YSwYBqCGbV/aGbJq98vCqLR3s7VOqO2t3rqj47jb8/H8xqVdfqXX1T38b/FCJLQAlXxlWUi0cgjf/bAjtjCGKKciY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682362; c=relaxed/simple; bh=lbhNMPZx1aYP7gAMfozxg+bB50npQM1hkFWtVjZkD3k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MdqcBEbgR6rL2X7hVythJIq3u6rTFzvWqDbhBNi8a3DiuorTfJBNdhWT9fwhBFZ9aKAfjNjKJgduseq9UM0Ek7A3EAiOh+aynEqWprQ4oQ3wNtQS8BR2H8C3kShYkGcR/2zmHJE8jJbFad9y2TVZt7YROZRs6l5S02SXqNuMeqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=nrJMjv56; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="nrJMjv56" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=sh RUqCP2zBWrwajTx563Fzrw3poUzwMnZ80zo73Eq0M=; b=nrJMjv56ABJ7IpgFHQ NaaojJjG1ZNhL39t+WHUO4i/HBoA4aOGYGTpMmOFLpK1dNBL4wspEcIxtYJn7OZO hCWFdrizYdzEd6vru/cItphzOo/3xTxmq+GE/SIkRGPB4fUkxxpLC8lKCefChsVN CWOl5+8OrqA6Od7K/132MM3Uk= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgAnMkhWz3doF6jWAw--.24466S5; Thu, 17 Jul 2025 00:12:10 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 3/7] PCI: Refactor standard capability search into common macro Date: Thu, 17 Jul 2025 00:11:59 +0800 Message-Id: <20250716161203.83823-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S5 X-Coremail-Antispam: 1Uf129KBjvJXoW3XrW7ZF1fZF1ftFyxZFWkWFg_yoWxJr4kpF W3A3WayrW8J3W7tanIva10kFyaqan7J3y29rW7Gwn8ZF12ka4vqa4SyF1YqFy2grZ7u3W7 Xa98tFykG3WYyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRIksPUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhKMo2h3yLuCeAADsS Content-Type: text/plain; charset="utf-8" The PCI Capability search functionality is duplicated across the PCI core and several controller drivers. The core's current implementation requires fully initialized PCI device and bus structures, which prevents controller drivers from using it during early initialization phases before these structures are available. Move the Capability search logic into a header-based macro that accepts a config space accessor function as an argument. This enables controller drivers to perform Capability discovery using their early access mechanisms prior to full device initialization while sharing the Capability search code. Convert the existing PCI core Capability search implementation to use this new macro. Controller drivers can later use the same macros with their early access mechanisms while maintaining the existing protection against infinite loops through preserved TTL checks. The ttl parameter was originally an additional safeguard to prevent infinite loops in corrupted config space. However, the PCI_FIND_NEXT_CAP() macro already enforces a TTL limit internally. Removing redundant ttl handling simplifies the interface while maintaining the safety guarantee. This aligns with the macro's design intent of encapsulating TTL management. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v13: - Split patch for searching standard capability. Changes since v12: - Delete __pci_find_next_cap, use PCI_FIND_NEXT_CAP_TTL() directly. - Modify the doc description of the function. Changes since v11: - Add #include , solve the compilation warnings caused by= the subsequent patch calls. Changes since v10: - Remove #include . - The patch commit message were modified. Changes since v9: - None Changes since v8: - The patch commit message were modified. --- drivers/pci/pci.c | 42 ++++++++---------------------------------- drivers/pci/pci.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1d1d147d007a..c590f697c011 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,7 +9,6 @@ */ =20 #include -#include #include #include #include @@ -424,36 +423,10 @@ static int pci_dev_str_match(struct pci_dev *dev, con= st char *p, return 1; } =20 -static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, - u8 pos, int cap, int *ttl) -{ - u8 id; - u16 ent; - - pci_bus_read_config_byte(bus, devfn, pos, &pos); - - while ((*ttl)--) { - if (pos < PCI_STD_HEADER_SIZEOF) - break; - pos =3D ALIGN_DOWN(pos, 4); - pci_bus_read_config_word(bus, devfn, pos, &ent); - - id =3D FIELD_GET(PCI_CAP_ID_MASK, ent); - if (id =3D=3D 0xff) - break; - if (id =3D=3D cap) - return pos; - pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); - } - return 0; -} - static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) { - int ttl =3D PCI_FIND_CAP_TTL; - - return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); + return PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, cap, bus, devfn); } =20 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) @@ -649,7 +622,7 @@ EXPORT_SYMBOL_GPL(pci_get_dsn); =20 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) { - int rc, ttl =3D PCI_FIND_CAP_TTL; + int rc; u8 cap, mask; =20 if (ht_cap =3D=3D HT_CAPTYPE_SLAVE || ht_cap =3D=3D HT_CAPTYPE_HOST) @@ -657,8 +630,8 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u= 8 pos, int ht_cap) else mask =3D HT_5BIT_CAP_MASK; =20 - pos =3D __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, - PCI_CAP_ID_HT, &ttl); + pos =3D PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, + PCI_CAP_ID_HT, dev->bus, dev->devfn); while (pos) { rc =3D pci_read_config_byte(dev, pos + 3, &cap); if (rc !=3D PCIBIOS_SUCCESSFUL) @@ -667,9 +640,10 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, = u8 pos, int ht_cap) if ((cap & mask) =3D=3D ht_cap) return pos; =20 - pos =3D __pci_find_next_cap_ttl(dev->bus, dev->devfn, - pos + PCI_CAP_LIST_NEXT, - PCI_CAP_ID_HT, &ttl); + pos =3D PCI_FIND_NEXT_CAP(pci_bus_read_config, + pos + PCI_CAP_LIST_NEXT, + PCI_CAP_ID_HT, dev->bus, + dev->devfn); } =20 return 0; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index e7d31ed56731..7465501a21e3 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -2,6 +2,8 @@ #ifndef DRIVERS_PCI_H #define DRIVERS_PCI_H =20 +#include +#include #include =20 struct pcie_tlp_log; @@ -93,6 +95,49 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 siz= e, u32 *val); =20 +/* Standard Capability finder */ +/** + * PCI_FIND_NEXT_CAP - Find a PCI standard capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search + * @cap: Capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Iterates through the capability list in PCI config space to find + * @cap. Implements TTL (time-to-live) protection against infinite loops. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_CAP(read_cfg, start, cap, args...) \ +({ \ + int __ttl =3D PCI_FIND_CAP_TTL; \ + u8 __id, __found_pos =3D 0; \ + u8 __pos =3D (start); \ + u16 __ent; \ + \ + read_cfg(args, __pos, 1, (u32 *)&__pos); \ + \ + while (__ttl--) { \ + if (__pos < PCI_STD_HEADER_SIZEOF) \ + break; \ + \ + __pos =3D ALIGN_DOWN(__pos, 4); \ + read_cfg(args, __pos, 2, (u32 *)&__ent); \ + \ + __id =3D FIELD_GET(PCI_CAP_ID_MASK, __ent); \ + if (__id =3D=3D 0xff) \ + break; \ + \ + if (__id =3D=3D (cap)) { \ + __found_pos =3D __pos; \ + break; \ + } \ + \ + __pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ =20 #ifdef CONFIG_DMI --=20 2.25.1 From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 395A02F5C48; Wed, 16 Jul 2025 16:12:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682361; cv=none; b=ultTcFhHQ5ffS3RlVkxFcqmQlijy/abazawUWOnIj3O0Db6/9gGVwxMW0XuRLw495EVmxHskKS+c6LAqrM031urkJckhSt0z5/4Pe1FYeKcOfnLjeeuPYLuMA9tQZwZ5Hxjgunj53vIhgcsukQQ3NFM1UEwleL3jj7KjzxSzdUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682361; c=relaxed/simple; bh=ynfFaEATL7WgfPAqPdV/qIxMEciE6FSsbl+MwHQEKV4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ImfDW6SosApOKX2KTN9hkYjPNfbsrCM26YD+sIT6kRYwGjb9RyBsJZxfeOt7EY5Ff9EwvKCZe8xqHvD9tpkRmM9IRoLDkAQCIuf2ZBLrgWchtcRKy9OW4DLiM50TTe9Tyy9I5+jESfeio7TuUwv9voiNgGzUPsPZTCNyk4wn7ls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=KH1k+y23; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="KH1k+y23" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ro JvHk5rWJ2i+4wCDc9OT17SNF6HWD0IX9y4ezkRwgo=; b=KH1k+y239l4CX1VC1c CLaQmvzVFjtgaXWiOX3i2zQWcBLc53CMLZn3kw7YDVlxRUqZQPlHmRGESWJle1fw KiP0iSrkXWHtQ+9+aswTYnfjEgj039ooHVJ9vNJUVxET3TS1mlu8MLHiCtjzdYfu RB0ZOGgtzYh5fSYcmQ/BR0A1U= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgAnMkhWz3doF6jWAw--.24466S6; Thu, 17 Jul 2025 00:12:11 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 4/7] PCI: Refactor extended capability search into common macro Date: Thu, 17 Jul 2025 00:12:00 +0800 Message-Id: <20250716161203.83823-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFyrtrW7CrW5XF4xJw43Wrg_yoWrXF15pr W3Aw1SyryrJa12qwnIva10gF1Ygan7JayUWFWfG34rZFyDCF1rCrWftayagFy7trZruF1S qFs5JFWrC3ZFyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEwvtiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxCMo2h3yP1-SwAAsi Content-Type: text/plain; charset="utf-8" Move the extended Capability search logic into a header-based macro that accepts a config space accessor function as an argument. This enables controller drivers to perform Capability discovery using their early access mechanisms prior to full device initialization while sharing the Capability search code. Convert the existing PCI core extended Capability search implementation to use this new macro. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v13: - Split patch for searching extended capability. Changes since v12: - Delete __pci_find_next_cap, use PCI_FIND_NEXT_CAP_TTL() directly. - Modify the doc description of the function. Changes since v11: - Add #include , solve the compilation warnings caused by= the subsequent patch calls. Changes since v10: - Remove #include . - The patch commit message were modified. Changes since v9: - None Changes since v8: - The patch commit message were modified. --- drivers/pci/pci.c | 35 ++--------------------------------- drivers/pci/pci.h | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c590f697c011..b72fd950ff92 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -527,42 +527,11 @@ EXPORT_SYMBOL(pci_bus_find_capability); */ u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) { - u32 header; - int ttl; - u16 pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - if (dev->cfg_size <=3D PCI_CFG_SPACE_SIZE) return 0; =20 - if (start) - pos =3D start; - - if (pci_read_config_dword(dev, pos, &header) !=3D PCIBIOS_SUCCESSFUL) - return 0; - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (pci_read_config_dword(dev, pos, &header) !=3D PCIBIOS_SUCCESSFUL) - break; - } - - return 0; + return PCI_FIND_NEXT_EXT_CAP(pci_bus_read_config, start, cap, + dev->bus, dev->devfn); } EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 7465501a21e3..17b7db127dad 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -138,6 +138,46 @@ int pci_bus_read_config(void *priv, unsigned int devfn= , int where, u32 size, __found_pos; \ }) =20 +/* Extended Capability finder */ +/** + * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search (0 for initial search) + * @cap: Extended capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Searches the extended capability space in PCI config registers + * for @cap. Implements TTL protection against infinite loops using + * a calculated maximum search count. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, args...) \ +({ \ + u16 __pos =3D (start) ?: PCI_CFG_SPACE_SIZE; \ + u16 __found_pos =3D 0; \ + int __ttl, __ret; \ + u32 __header; \ + \ + __ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ + while (__ttl-- > 0 && __pos >=3D PCI_CFG_SPACE_SIZE) { \ + __ret =3D read_cfg(args, __pos, 4, &__header); \ + if (__ret !=3D PCIBIOS_SUCCESSFUL) \ + break; \ + \ + if (__header =3D=3D 0) \ + break; \ + \ + if (PCI_EXT_CAP_ID(__header) =3D=3D (cap) && __pos !=3D start) {\ + __found_pos =3D __pos; \ + break; \ + } \ + \ + __pos =3D PCI_EXT_CAP_NEXT(__header); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ =20 #ifdef CONFIG_DMI --=20 2.25.1 From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 439B62F5466; Wed, 16 Jul 2025 16:12:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682358; cv=none; b=W2fC3HtAw/M0QrtVJ2xP8ZDmOuqELym7ThsdlxZW8Sovnt+TqV+I2EV1bFmBoMCZgXOIu5NRfhh6l30BRa0mJUbOhQB7TYJ9uMQGnGKm0WttfsX/iLF4kh5HiN16ZX+H+zGWeIvAm8YS+tXwVEgWSdzP21OMDTQXRDw4wzgWLsk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682358; c=relaxed/simple; bh=5QRhjTY61OamMuKmyL25IGxdeBzFuqBgtEG2oUdBnEo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EHXX9T3vakrjG/sgEhCwWO6g179r3PVghl9IW/Tel6C+HIfa/VdXDK1886AzFuzD2HQNcAlWGy7aYOuI7jktP1SgYDgo61tHRuMNHItlQr/Xk7aoOq5r+Rjge7sK3koyqkCbR+Pad6tzG2oJMs9DwMifSD5ti6WCgK/Pa5/u0kA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=eoKMaiHn; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="eoKMaiHn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=t7 nhK9QibaYlqN4aFk40gKliWnYXZDrUuUsAUWHP5PM=; b=eoKMaiHnFmjpqXdyNx phuJNs93GBgimMXcWWqm3EmCg8e8UztD1AsL3EtQezEtKen71gkGyBFbji7rvGLP /eq1lxBZ0z57Vv23/ppFEvRM27svIsZJKxnwfO5xiYfQbXsNVj2If+ENDnZHZaGv r9T9xt5s7mXLcSQkrWfdJsD+U= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgAnMkhWz3doF6jWAw--.24466S7; Thu, 17 Jul 2025 00:12:12 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 5/7] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Thu, 17 Jul 2025 00:12:01 +0800 Message-Id: <20250716161203.83823-6-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S7 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrCr4UAF1ruw1kCw1DAwb_yoWrZFWUp3 yrAwn0yF4UAr1aqw1DZFnIv3W3AF9xAF1xAa97Gwnavry2kryUJ340krWagrnakrZFgFya gr4kJFyrArnxtFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEwvtiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwKMo2h3yadzGQAAst Content-Type: text/plain; charset="utf-8" Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam --- Changes since v13: - Use simplified macro definitions: PCI_FIND_NEXT_CAP(), PCI_FIND_NEXT_EXT_= CAP(). Changes since v12: - Modify the function's return value and format issues. Changes since v11: - Resolve compilation errors. s/dw_pcie_read_dbi/dw_pcie_read*_dbi Changes since v10: - None Changes since v9: - Resolved [v9 4/6] compilation error. The latest 6.15 rc1 merge __dw_pcie_find_vsec_capability, which uses=20 dw_pcie_find_next_ext_capability. Changes since v8: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.c= om/ - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/dwc/pcie-designware.c | 83 ++++---------------- 1 file changed, 16 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 4d794964fa0f..b503cb4bcb28 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -213,83 +213,32 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type =3D ver; } =20 -/* - * These interfaces resemble the pci_find_*capability() interfaces, but th= ese - * are for configuring host controllers, which are bridges *to* PCI device= s but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; + struct dw_pcie *pci =3D priv; =20 - reg =3D dw_pcie_readw_dbi(pci, cap_ptr); - cap_id =3D (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; - - if (cap_id =3D=3D cap) - return cap_ptr; + if (size =3D=3D 4) + *val =3D dw_pcie_readl_dbi(pci, where); + else if (size =3D=3D 2) + *val =3D dw_pcie_readw_dbi(pci, where); + else if (size =3D=3D 1) + *val =3D dw_pcie_readb_dbi(pci, where); + else + return PCIBIOS_BAD_REGISTER_NUMBER; =20 - next_cap_ptr =3D (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCIBIOS_SUCCESSFUL; } =20 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg =3D dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr =3D (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); =20 -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos =3D start; - - header =3D dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header =3D dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); =20 @@ -302,8 +251,8 @@ static u16 __dw_pcie_find_vsec_capability(struct dw_pci= e *pci, u16 vendor_id, if (vendor_id !=3D dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) return 0; =20 - while ((vsec =3D dw_pcie_find_next_ext_capability(pci, vsec, - PCI_EXT_CAP_ID_VNDR))) { + while ((vsec =3D PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, + PCI_EXT_CAP_ID_VNDR, pci))) { header =3D dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); if (PCI_VNDR_HEADER_ID(header) =3D=3D vsec_id) return vsec; --=20 2.25.1 From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9EC251A2541; Wed, 16 Jul 2025 16:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682360; cv=none; b=pYaXMAT/BjMS//++xjv+Z2gyLeeRcmnAp63N1doVnOXsTEG1uMGEeHMbjisPo93x/5Me76T72p/mlYDePGB/NpgfC8njXSqZ6HpbWW7db1ncfUoeP4lq8a5MfkaCYUNPea7NF5GySaBtEoPqAJhRCmIyuSV3wOSObZJheyXSfEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682360; c=relaxed/simple; bh=i0U1QoZbUHprU/1Nv3qGW39aq37fpJdJY8SqLfGBog0=; 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Thu, 17 Jul 2025 00:12:13 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 6/7] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities Date: Thu, 17 Jul 2025 00:12:02 +0800 Message-Id: <20250716161203.83823-7-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S8 X-Coremail-Antispam: 1Uf129KBjvJXoWxury7Ww48Ar17Cw4Duw13CFg_yoW5Kw17pF WDCFyfCF1rJFW3uFn3A3W5Xr13tFnak342ya92kw17ZF17ur1UGFnFgFy3Kr9xKrsrWr17 X3yDJFykKr1YyFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEwvtiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhmMo2h3yLuC+AAAsa Content-Type: text/plain; charset="utf-8" Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam --- Changes since v13: - Use simplified macro definitions: PCI_FIND_NEXT_CAP(), PCI_FIND_NEXT_EXT_= CAP(). Changes since v12: - Modify the function's return value. Changes since v11: - Modify the return value of cdns_pcie_readw from u32 to u16.=20 - Modify the return value of cdns_pcie_readb from u32 to u8.=20 Changes since v8 ~ v10: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.c= om - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/cadence/pcie-cadence.c | 30 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 13 ++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 70a19573440e..7b2955e4fafb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -8,6 +8,36 @@ #include =20 #include "pcie-cadence.h" +#include "../../pci.h" + +static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val) +{ + struct cdns_pcie *pcie =3D priv; + + if (size =3D=3D 4) + *val =3D cdns_pcie_readl(pcie, where); + else if (size =3D=3D 2) + *val =3D cdns_pcie_readw(pcie, where); + else if (size =3D=3D 1) + *val =3D cdns_pcie_readb(pcie, where); + else + return PCIBIOS_BAD_REGISTER_NUMBER; + + return PCIBIOS_SUCCESSFUL; +} + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_CAP(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST, + cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_capability); + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_EXT_CAP(cdns_pcie_read_cfg, 0, cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); =20 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index a149845d341a..38f7a8cdf7f1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -387,6 +387,16 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline u16 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg) +{ + return readw(pcie->reg_base + reg); +} + +static inline u8 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg) +{ + return readb(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); @@ -556,6 +566,9 @@ static inline void cdns_pcie_ep_disable(struct cdns_pci= e_ep *ep) } #endif =20 +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); =20 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, --=20 2.25.1 From nobody Mon Oct 6 21:02:05 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9EC932F548C; Wed, 16 Jul 2025 16:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752682360; cv=none; b=r+8umwHYefSJIpxn0MXhPxBj8OIs0Xzsj/1cEWWQAohuzpc0X9FC0goFg5pSM6rsiVWQk4hObQI8qgFxcG3EW1FoUZ5GLxuQzblGTJbaN3pP7uGMskSj3f8vUglXNJXmwx9aWll1KqwDF2clVRoBi9xnn/HkVqrPjsJ94LEtgTE= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version: Content-Type; bh=aKqO8ZFw8Cu+RbQvK9ETURYLI9DYzDI2/InISu28Jh4=; b=Z0utB+JaTQaiB2Y4aP1kjvV9fOM5Px33vjnMCcQ/9q454nqE/36/RHpuCatWN6 3InPT/7zFQF+9M2PmBARQSf5dycOMDtS9bJ6GievAVa/OagnR+JXd6bgpLYKczQH 7fcT3CpFMq5MCxpARYTHEWWcUNTYccx9/6ahTmlU4/Af0= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgAnMkhWz3doF6jWAw--.24466S9; Thu, 17 Jul 2025 00:12:13 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v14 7/7] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode Date: Thu, 17 Jul 2025 00:12:03 +0800 Message-Id: <20250716161203.83823-8-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250716161203.83823-1-18255117159@163.com> References: <20250716161203.83823-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgAnMkhWz3doF6jWAw--.24466S9 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1rCrWfWF15ArWUXF18Xwb_yoWxuFW3pF W5ua4SkF40qrW7uFsrA3W5ZrnxtFnIv347Aa92kw15uF129FyUGFyIva43KF1akrs7u3W7 XrWDtrsa93ZxtrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEwvtiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwaMo2h3yadzKwABsa The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam Reviewed-by: Ilpo J=C3=A4rvinen --- Changes since v8 ~ v13: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.c= om - Kconfig add "select PCI_HOST_HELPERS" --- .../pci/controller/cadence/pcie-cadence-ep.c | 38 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 8ab6cf70c18e..4f0d2ee5e513 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -21,12 +21,13 @@ =20 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; =20 if (vfn =3D=3D 0) return fn; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn =3D fn + first_vf_offset + ((vfn - 1) * stride); @@ -38,10 +39,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *ep= c, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u32 reg; + u16 cap; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -227,9 +229,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u= 8 fn, u8 vfn, u8 nr_irqs) struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* @@ -249,9 +252,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u= 8 fn, u8 vfn) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Validate that the MSI feature is actually enabled. */ @@ -272,9 +276,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, = u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -292,9 +297,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, = u8 fn, u8 vfn, { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -380,11 +386,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie= _ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask =3D 0xff; + u8 msi_count, cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -432,14 +438,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u64 pci_addr, pci_addr_mask =3D 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -482,16 +488,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie =3D &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask =3D 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf =3D &ep->epf[fn]; if (vfn > 0) epf =3D &epf->epf[vfn - 1]; @@ -565,7 +571,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs =3D sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -589,12 +597,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cap + PCI_EXP_DEVCAP, value); } } =20 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 38f7a8cdf7f1..f0fdeb3863f1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) =20 -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */ --=20 2.25.1