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([188.193.103.108]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e8293fe7sm1196705266b.123.2025.07.16.08.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:48:14 -0700 (PDT) From: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= To: Frank.li@nxp.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, boerge.struempfel@gmail.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= , kernel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 1/3] MAINTAINERS: Add i.MX8MP Ultra-MACH SBC to ULTRATRONIK BOARD SUPPORT Date: Wed, 16 Jul 2025 17:48:04 +0200 Message-ID: <20250716154808.335138-2-goran.radni@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250716154808.335138-1-goran.radni@gmail.com> References: <20250716154808.335138-1-goran.radni@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The i.MX8MP-based Ultra-MACH SBC is supported by Ultratronik, and its device tree has been added under arch/arm64/boot/dts/freescale/. To ensure proper maintainer coverage and notification of relevant changes, add the imx8mp-ultra-mach-sbc.dts file to the existing ULTRATRONIK BOARD SUPPORT section. This follows the established pattern already used for the STM32MP157C- based Ultra-FLY SBC. Signed-off-by: Goran Ra=C4=91enovi=C4=87 --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 60bba48f5479..0ab09226e0aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25450,6 +25450,7 @@ M: Goran Ra=C4=91enovi=C4=87 M: B=C3=B6rge Str=C3=BCmpfel S: Maintained F: arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts +F: arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts =20 UNICODE SUBSYSTEM M: Gabriel Krisman Bertazi --=20 2.43.0 From nobody Mon Oct 6 20:59:23 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF1BA2F2C54; Wed, 16 Jul 2025 15:48:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752680900; cv=none; b=G1eeBx1MweWsWybEK5FVaylXaWCe+8Sht9wnBj+yEkWWUUWmqgJg6qg/U3nTvW8IqBYK6UOlpxHRS7xy+GNXY/wZv+MMHk3ZoN6BtEHSDukCCumzBDEKedLFMAqE7oj1oFd1SzkdHyG0JznH+wfrEKFhyqZ35awEamP6XI1MI3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752680900; c=relaxed/simple; bh=D9hK6aCg1zp32zCrrbFTJLWW5r7AZGwUreSAc0MrHXA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uLHeCvd92TyuS97/6Vlb1c++s2UNBCCtvcThA3EOuWC8ZKSMN0TJui3pJwV2T92AgbahvznIp9lUyXXXtuVjf+bvG/uFjAxN/QkDYA1iYw9GOTNnpXOt1yhalBSwOdqD/5UUAK/eFIe4R1rZ8LrHjFIJ9BnSXbJXd7HwR7k643w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YCnaHrpM; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YCnaHrpM" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-ae0b2ead33cso12796366b.0; Wed, 16 Jul 2025 08:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752680897; x=1753285697; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sfEbSpxuj6iCO3S7ehFSQfszMAGt5vRbG8XfTrlB69o=; b=YCnaHrpMsL/AOQziD4KA/FnFwoukf9aoZQpytAypTksA+rB4wZve525gO3jej62E7I wTpmmCDa1ec5CM5x3KyPShz/rDtu5N7aozoP/b2PdaSx8i+gE61A9ALy0pMvQcNtFU8k N/nMO4S9fAWMBQmpM/jKyqRR1w3Z4aBwy1dho08o5kFHAF0yPfS6SA2JV76QGk6+MxCd N+n7fNrauicpnnBEY1fD6N2WiTRaRTVY1HmSQB1snvvcMRtbiLCZfHcTs50hTxcvapWn VKZ378OKH6+Y/KtzNGhZmrnt7YnJ734asIB0RQds6Z/5F4ylnGItK31GLmXjXRxhF7Oq NTTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752680897; x=1753285697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sfEbSpxuj6iCO3S7ehFSQfszMAGt5vRbG8XfTrlB69o=; b=AOKaERrwxK6WOWdEfeBJcMZfOimktrbM48C9Sker4Vdd7sCSbR/YMk6wsArKIh/Rhg lUgy8eWIkZXci8PFQUywmw1+6bJlqJ85Y8pIaPPnyFDWHX71F+JvMyHFWeLP8COzs2xj O1FZdkkvZzmM5PDFi3kReh7wR/nei1rBwTCE/vcGriW7fGh304u120JA381VvnL86Ri/ TUzyWZ5LniM2JWyeRYenyW9WdsPOtbddzMwLGNo456OBGoromjjvzfXjY3uJVcAn0nQX B3x7Q6JwkwUTdlzH9ljkEve9cQagbEq5x0akfHJdvPkplpeA/D/i8zRC1MWPi7golPYd gwzQ== X-Forwarded-Encrypted: i=1; AJvYcCXkrHSQviPFtg0Eghc+fOuOZrPtBjHkgxnWDrhKZisG/8464iQLJMDNc4hxEre8t28IM3MR4L3+86Ur@vger.kernel.org, AJvYcCXxX05Imbkg9G50LGIT+fafIQBeiqcZPIapYZia8Btp/4bB7OokeuNuWycrGQBcuEgL4x2NPQDSZv1WqNoM@vger.kernel.org X-Gm-Message-State: AOJu0YzxzHxL7x0n7b8oH5pg+oXSwArZvurbl+JBS30Pm2tf1aOr/Jhc YCaanLyE/pjeLanAPKnrTSQZiyXxMV7o62OThNBu2Gp5/pddOaqTRWY2 X-Gm-Gg: ASbGnctMr1pPEn7g3GhuLNzOcfIz06TyDEJU7DhEw8MH0AVlmMYaTu8EOdCvsbYVUdF d/Qv4F6CmBoEAThVfzIZijWqJYdZPp4B3+V34xp3kk6Oi2PjZIOJ6fSZb8CVlYsdRZ9XRDb9nh+ ZMMSVsWvN+HVa3ZY0E4CVs8oc4jsAuNDabHAnM5YZNI+WHpV641dhZR3qV8UdiqAnFbtUmrkOsi /0cyC7oibxvB1nQ2xtHOVPo6At1zYXnXcosr+GQMeJGU4b3KH2t6Fi3v5XhpOW6qAqdFRnLyfnM XaZLpOcvO1193CRpDxCr6ck1EbOnR34gCOtKy9lpGXfBwdBYUw5WvYY1O5SmQPySVw43WXSp/m4 UEmR/q0hK/P0remkeRCEc6wD96G1dOCm4BTOL X-Google-Smtp-Source: AGHT+IEtMqgd0cERI8zRb+TGkoaqjZkaTKRBSNcMuZ1lo/YTkdU8esv903psbEZ+S5JSVNmNrcYOCQ== X-Received: by 2002:a17:907:c88d:b0:ae0:d409:5f19 with SMTP id a640c23a62f3a-aec4cdfd503mr8257666b.2.1752680896987; Wed, 16 Jul 2025 08:48:16 -0700 (PDT) Received: from wslxew242.. ([188.193.103.108]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e8293fe7sm1196705266b.123.2025.07.16.08.48.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:48:16 -0700 (PDT) From: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= To: Frank.li@nxp.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, boerge.struempfel@gmail.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= , kernel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski Subject: [PATCH v5 2/3] dt-bindings: arm: imx8mp: Add Ultratronik Ultra-MACH SBC Date: Wed, 16 Jul 2025 17:48:05 +0200 Message-ID: <20250716154808.335138-3-goran.radni@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250716154808.335138-1-goran.radni@gmail.com> References: <20250716154808.335138-1-goran.radni@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Document the Ultratronik Ultra-MACH SBC, based on the NXP i.MX8MP SoC. This board is manufactured by Ultratronik GmbH and uses the compatible string "ux,imx8mp-ultra-mach-sbc". Acked-by: Krzysztof Kozlowski Signed-off-by: Goran Ra=C4=91enovi=C4=87 --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index d3b5e6923e41..9cf2ab3b12db 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1101,6 +1101,7 @@ properties: - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climat= e control with 10.1" panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control= with LED frontplate - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate c= ontrol with 7" panel + - ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8M= P based board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Boa= rd - const: fsl,imx8mp =20 --=20 2.43.0 From nobody Mon Oct 6 20:59:23 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A158B2F6F8C; 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([188.193.103.108]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e8293fe7sm1196705266b.123.2025.07.16.08.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:48:19 -0700 (PDT) From: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= To: Frank.li@nxp.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, boerge.struempfel@gmail.com, s.hauer@pengutronix.de, festevam@gmail.com, Pengutronix Kernel Team , =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/3] arm64: dts: imx8mp: Add initial support for Ultratronik imx8mp-ultra-mach-sbc board Date: Wed, 16 Jul 2025 17:48:06 +0200 Message-ID: <20250716154808.335138-4-goran.radni@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250716154808.335138-1-goran.radni@gmail.com> References: <20250716154808.335138-1-goran.radni@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add initial device tree support for the Ultratronik Ultra-MACH SBC based on the NXP i.MX8M Plus SoC with 2GB LPDDR4. The board features: - 1 x USB 2.0 Host - 1 x USB 2.0 via USB-C - Debug UART + 1 x UART + 1 x USART - SD card and eMMC support - 2 x Ethernet (RJ45) - HDMI This initial DTS enables basic board support for booting via SD card or eMMC. Signed-off-by: Goran Ra=C4=91enovi=C4=87 --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-ultra-mach-sbc.dts | 907 ++++++++++++++++++ 2 files changed, 908 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 0b473a23d120..e2f2500238fe 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -229,6 +229,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revc-tian-g0701= 7.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tqma8mpql-mba8mp-ras314.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-ultra-mach-sbc.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw72xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts b/arch= /arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts new file mode 100644 index 000000000000..9ecec1a41878 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts @@ -0,0 +1,907 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Ultratronik + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model =3D "NXP i.MX8MPlus Ultratronik MMI_A53 board"; + compatible =3D "ultratronik,imx8mp-ultra-mach-sbc", "fsl,imx8mp"; + + aliases { + ethernet0 =3D &fec; + ethernet1 =3D &eqos; + rtc0 =3D &hwrtc; + rtc1 =3D &snvs_rtc; + }; + + chosen { + stdout-path =3D &uart2; + }; + + gpio-sbu-mux { + compatible =3D "nxp,cbdtu02043", "gpio-sbu-mux"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sbu_mux>; + select-gpios =3D <&gpio4 20 GPIO_ACTIVE_HIGH>; + enable-gpios =3D <&gpio2 20 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint =3D <&typec_con_ss>; + }; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-0 { + gpios =3D <&gpio4 27 GPIO_ACTIVE_LOW>; /* Wakeup */ + label =3D "Wakeup"; + linux,code =3D ; + pinctrl-0 =3D <&pinctrl_gpio_key_wakeup>; + pinctrl-names =3D "default"; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_leds>; + + led1 { + label =3D "red"; + gpios =3D <&gpio4 24 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + }; + + led2 { + label =3D "green"; + gpios =3D <&gpio4 25 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + }; + + led3 { + label =3D "yellow"; + gpios =3D <&gpio4 26 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + }; + }; + + reg_usba_vbus: regulator-usba-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1>; + regulator-name =3D "usb-A-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2>; +}; + +&A53_1 { + cpu-supply =3D <&buck2>; +}; + +&A53_2 { + cpu-supply =3D <&buck2>; +}; + +&A53_3 { + cpu-supply =3D <&buck2>; +}; + +&ecspi1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + slb9670: tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + reg =3D <0>; + spi-max-frequency =3D <32000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_slb9670>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ecspi2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 8 GPIO_ACTIVE_LOW>, + <&gpio1 9 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + nfc-transceiver@1 { + compatible =3D "st,st95hf"; + reg =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_nfc>; + spi-max-frequency =3D <100000>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <7 IRQ_TYPE_EDGE_FALLING>; + enable-gpio =3D <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <18 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy1>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x2>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&gpio1 { + gpio-line-names =3D + "#TPM_IRQ", "GPIO1", "", "#PMIC_INT", + "SD2_VSEL", "#TOUCH_IRQ", "#NFC_INT_I", "#NFC_INT", + "#SPI2_CS2", "#SPI2_CS3", "#RTS4", "", + "USB_PWR", "GPIO2", "GPIO3", ""; +}; + +&gpio2 { + gpio-line-names =3D + "", "", "", "", "", "", "", "", + "", "", "", "", "#SD2_CD", "", "", "", + "", "", "", "", "#USB-C_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names =3D + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DISP_POW", "GPIO4", + "#", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names =3D + "BKL_POW", "#ETH1_INT", "#TPM_RES", "#PCAP_RES", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "#ETH0_INT", "#USB-C_ALERT", + "#USB-C_SEL", "", "", "", + "LED_RED", "LED_GREEN", "LED_YELLOW", "#WAKEUP", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names =3D + "", "", "", "", "", "", "", "", + "", "#SPI1_CS", "", "", "", "#SPI2_CS1", "", "", + "", "", "", "", "ENA_KAM", "ENA_LED", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi_pvi { + status =3D "okay"; +}; + +&hdmi_tx { + ddc-i2c-bus =3D <&i2c5>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hdmi>; + status =3D "okay"; +}; + +&hdmi_tx_phy { + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9450c"; + reg =3D <0x25>; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 GPIO_ACTIVE_LOW>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8DVNLZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <1050000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + buck4: BUCK4 { /* +3V3 */ + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* +1V8 */ + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* DRAM_1V1 */ + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1P8 */ + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* ENET_2V5 */ + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + crypto@35 { + compatible =3D "atmel,atecc508a"; + reg =3D <0x35>; + }; + + eeprom@50 { + compatible =3D "atmel,24c16"; + reg =3D <0x50>; + pagesize =3D <16>; + }; +}; + +&i2c2 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c2>; + pinctrl-1 =3D <&pinctrl_i2c2_gpio>; + scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + hwrtc: rtc@32 { + compatible =3D "epson,rx8900"; + reg =3D <0x32>; + epson,vdet-disable; + trickle-diode-disable; + }; + + tcpc@52 { + compatible =3D "nxp,ptn5110", "tcpci"; + reg =3D <0x52>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ptn5110>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <19 IRQ_TYPE_LEVEL_LOW>; + + usb_con: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + power-role =3D "dual"; + data-role =3D "dual"; + try-power-role =3D "sink"; + source-pdos =3D ; + sink-pdos =3D ; + op-sink-microwatt =3D <15000000>; + self-powered; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + typec_dr_sw: endpoint { + remote-endpoint =3D <&usb3_drd_sw>; + }; + }; + + port@1 { + reg =3D <1>; + + typec_con_ss: endpoint { + remote-endpoint =3D <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c3>; + pinctrl-1 =3D <&pinctrl_i2c3_gpio>; + scl-gpios =3D <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c5>; + pinctrl-1 =3D <&pinctrl_i2c5_gpio>; + scl-gpios =3D <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&lcdif3 { + status =3D "okay"; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm1>; + status =3D "okay"; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm2>; + status =3D "okay"; +}; + +&snvs_pwrkey { + status =3D "okay"; +}; + +&uart2 { + /* system console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "okay"; +}; + +&uart4 { + /* expansion port serial connection */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status =3D "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint =3D <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + vbus-supply =3D <®_usba_vbus>; + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + snps,hsphy_interface =3D "utmi"; + status =3D "okay"; +}; + +&usdhc2 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates =3D <400000000>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width =3D <4>; + vmmc-supply =3D <®_usdhc2_vmmc>; + vqmmc-supply =3D <&ldo5>; + status =3D "okay"; +}; + +&usdhc3 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates =3D <400000000>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + vmmc-supply =3D <&buck4>; + vqmmc-supply =3D <&buck5>; + bus-width =3D <8>; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* #SPI1_CS */ + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2-cs-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* #SPI2_CS */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* #SPI2_CS2 */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40 /* #SPI2_CS3 */ + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_eqos: eqos-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x0 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x0 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 /* #ETH0_INT */ + >; + }; + + pinctrl_fec: fec-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x0 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* #ETH1_INT */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_gpio_key_wakeup: gpio-key-wakeup-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40 /* #WAKEUP */ + >; + }; + + pinctrl_gpio_leds: gpio-leds-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40 /* LED_RED */ + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40 /* LED_GREEN */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40 /* LED_YELLOW */ + >; + }; + + pinctrl_hdmi: hdmi-grp { + fsl,pins =3D < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + pinctrl_hog: hog-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x40 /* GPIO1 */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40 /* GPIO2 */ + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 /* GPIO3 */ + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40 /* GPIO4 */ + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x40 /* ENA_KAM */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x40 /* ENA_LED */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* #PCAP_RES */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40 /* #RTS4 */ + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c0 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0xc0 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0xc0 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c0 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0xc0 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0xc0 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0xc2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0xc2 + >; + }; + + pinctrl_i2c5: i2c5-grp { + fsl,pins =3D < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400000c4 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400000c4 + >; + }; + + pinctrl_i2c5_gpio: i2c5-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0xc4 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0xc4 + >; + }; + + pinctrl_nfc: nfc-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40 /* NFC_INT_I */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */ + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ + >; + }; + + pinctrl_ptn5110: ptn5110-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* #USB-C_ALERT */ + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 /* EXT_PWM */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: reg-usdhc2-vmmc-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_sbu_mux: sbu-mux-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* #USB-C_SEL */ + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x16 /* #USB-C_EN */ + >; + }; + + pinctrl_slb9670: slb9670-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x40 /* #TPM_IRQ */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40 /* #TPM_RES */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40 + >; + }; + + pinctrl_usb1: usb1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x40 /* USB_PWR */ + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x40 /* #SD3_RESET */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x192 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d2 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x192 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 /* #WDOG */ + >; + }; +}; --=20 2.43.0