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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3bbe6bd8f8sm13912054a12.38.2025.07.16.08.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:20:38 -0700 (PDT) From: Pankaj Patil To: sboyd@kernel.org, mturquette@baylibre.com, andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, taniya.das@oss.qualcomm.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] clk: qcom: Add TCSR clock driver for Glymur Date: Wed, 16 Jul 2025 20:50:13 +0530 Message-Id: <20250716152017.4070029-4-pankaj.patil@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> References: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDEzOCBTYWx0ZWRfXzkU/hSK68OMo nAwm6lfj6t5IX7s+ptTWaCTmZK04/3HMT4FyQoAJ3zglCkk5WpjK61agJ4cTLlw0BIbxoymVGiG aGg+kWPexncS5cwOEBB6XFrzb/lWPMPxq5BQSb390TBpvcEhHjbe5TZb3+dm4gE4DC6917tu+Bs FuyvLy+vnwXUVZOYgdjcKY+Plva2j9aMPXI1rZaMtJXmQdxrZAQbss4dVzyyHselXOW3i9Tjor6 psY1fsRI1eghEOTDhrJneAZXHVFCBIZbQtxMMFFNejCtGI8RRZbTX/a+bSHUF6OL2kmcX6Iut1q u1Ua2qENWqGC6F/PQSaxYKR1NZ6tvni85ebPmEYRsa5ZxbMzKvOlHNf07O6nRYo2UBmNys7nLR1 fKXBDOswuGwS/VzHBJkn1j0w7/UVMfd9e0NXk0N4ejQ343WuxUwUCD6q66Mkmn15+8r+xHW4 X-Proofpoint-GUID: QGQOnMeOXDVJakPtmQTXGlSDlYRQ_CrL X-Authority-Analysis: v=2.4 cv=SeX3duRu c=1 sm=1 tr=0 ts=6877c349 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=Faslhf6HPDYYN2OqSgcA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: QGQOnMeOXDVJakPtmQTXGlSDlYRQ_CrL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_02,2025-07-16_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160138 Content-Type: text/plain; charset="utf-8" From: Taniya Das Add a clock driver for the TCSR clock controller found on Glymur, which provides refclks for PCIE, USB, and UFS. Signed-off-by: Taniya Das Signed-off-by: Pankaj Patil --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-glymur.c | 263 +++++++++++++++++++++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 drivers/clk/qcom/tcsrcc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 36d6e6e1e7f0..051301007aa6 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1304,6 +1304,14 @@ config SM_LPASSCC_6115 Say Y if you want to toggle LPASS-adjacent resets within this clock controller to reset the LPASS subsystem. =20 +config SC_TCSRCC_GLYMUR + tristate "GLYMUR TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the TCSR clock controller on GLYMUR devices. + Say Y if you want to use peripheral devices such as USB/PCIe/EDP. + config SM_TCSRCC_8550 tristate "SM8550 TCSR Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab59434338bb..bf95729678f6 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -162,6 +162,7 @@ obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o +obj-$(CONFIG_SC_TCSRCC_GLYMUR) +=3D tcsrcc-glymur.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) +=3D tcsrcc-sm8650.o obj-$(CONFIG_SM_TCSRCC_8750) +=3D tcsrcc-sm8750.o diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c new file mode 100644 index 000000000000..760d36339b10 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +static struct clk_branch tcsr_edp_clkref_en =3D { + .halt_reg =3D 0x1c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_edp_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_1_clkref_en =3D { + .halt_reg =3D 0x4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_1_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_2_clkref_en =3D { + .halt_reg =3D 0x8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_3_clkref_en =3D { + .halt_reg =3D 0x10, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_3_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_4_clkref_en =3D { + .halt_reg =3D 0x14, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x14, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_4_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_1_clkref_en =3D { + .halt_reg =3D 0x28, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x28, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_1_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_2_clkref_en =3D { + .halt_reg =3D 0x2c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_3_clkref_en =3D { + .halt_reg =3D 0x30, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x30, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_3_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_4_clkref_en =3D { + .halt_reg =3D 0x44, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x44, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_4_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_0_clkref_en =3D { + .halt_reg =3D 0x20, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x20, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb3_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_1_clkref_en =3D { + .halt_reg =3D 0x24, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x24, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb3_1_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb4_1_clkref_en =3D { + .halt_reg =3D 0x0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb4_1_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb4_2_clkref_en =3D { + .halt_reg =3D 0x18, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x18, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb4_2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_glymur_clocks[] =3D { + [TCSR_EDP_CLKREF_EN] =3D &tcsr_edp_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, + [TCSR_PCIE_2_CLKREF_EN] =3D &tcsr_pcie_2_clkref_en.clkr, + [TCSR_PCIE_3_CLKREF_EN] =3D &tcsr_pcie_3_clkref_en.clkr, + [TCSR_PCIE_4_CLKREF_EN] =3D &tcsr_pcie_4_clkref_en.clkr, + [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, + [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, + [TCSR_USB2_3_CLKREF_EN] =3D &tcsr_usb2_3_clkref_en.clkr, + [TCSR_USB2_4_CLKREF_EN] =3D &tcsr_usb2_4_clkref_en.clkr, + [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, + [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, + [TCSR_USB4_1_CLKREF_EN] =3D &tcsr_usb4_1_clkref_en.clkr, + [TCSR_USB4_2_CLKREF_EN] =3D &tcsr_usb4_2_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x44, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc tcsr_cc_glymur_desc =3D { + .config =3D &tcsr_cc_glymur_regmap_config, + .clks =3D tcsr_cc_glymur_clocks, + .num_clks =3D ARRAY_SIZE(tcsr_cc_glymur_clocks), +}; + +static const struct of_device_id tcsr_cc_glymur_match_table[] =3D { + { .compatible =3D "qcom,glymur-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); + +static int tcsr_cc_glymur_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &tcsr_cc_glymur_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(&pdev->dev, &tcsr_cc_glymur_desc, regmap); +} + +static struct platform_driver tcsr_cc_glymur_driver =3D { + .probe =3D tcsr_cc_glymur_probe, + .driver =3D { + .name =3D "tcsrcc-glymur", + .of_match_table =3D tcsr_cc_glymur_match_table, + }, +}; + +static int __init tcsr_cc_glymur_init(void) +{ + return platform_driver_register(&tcsr_cc_glymur_driver); +} +subsys_initcall(tcsr_cc_glymur_init); + +static void __exit tcsr_cc_glymur_exit(void) +{ + platform_driver_unregister(&tcsr_cc_glymur_driver); +} +module_exit(tcsr_cc_glymur_exit); + +MODULE_DESCRIPTION("QTI TCSRCC GLYMUR Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1