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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de42ad9efsm132769455ad.58.2025.07.16.08.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:15:47 -0700 (PDT) From: Pankaj Patil To: djakov@kernel.org, lumag@kernel.org, a39.skl@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, raviteja.laggyshetty@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Glymur SoC Date: Wed, 16 Jul 2025 20:45:34 +0530 Message-Id: <20250716151535.4054172-2-pankaj.patil@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716151535.4054172-1-pankaj.patil@oss.qualcomm.com> References: <20250716151535.4054172-1-pankaj.patil@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 34k12-_lKgXg5KweYdLUYTi59jKFvREW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDEzOCBTYWx0ZWRfX2uVw6QIJ4Jqd OtIUDXDaJL7/dVYOCn7euAiFUCRH1R7gQgAcX4RXuk3j53Ve43b6dKDKweP379Tqhc5YsZRGqJK u6gyQgfO8sBo36fK+AolXV6RRTsuPNQl4tPkP9PhPvvQgDiAhmO8meEkKadYL9H+MVj+V2qxWNE E3cENG4pZkSSbtOWcBqp1891YOTPSvgANbOeUe8bca37JCYHWmOx1iOKGYsrJ4L44ZWdJN+2TY6 dp1Ga+NnJ4CGwCob3EKKrJ+GLyMiR3aIt+NsnBtFFVS6bkmM5GwoCd5Si5xgRri8XYg8TVlcEb6 jXGoVpmgGKQm59l2bxnKcTGqN68b3Wp61KEZmWpSJtDmkn9xD947nTiISxUWM1un4QpacBW1iPb TqokquVN7+ukKgvXeSGKCf+IholsDE+E6HYypNnFQdlJbprvYFyIgF7aIDBj5R62cw9d4Znl X-Authority-Analysis: v=2.4 cv=WqUrMcfv c=1 sm=1 tr=0 ts=6877c225 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=0n2OPg6v9igEIy7wDKMA:9 a=uG9DUKGECoFWVXl0Dc02:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: 34k12-_lKgXg5KweYdLUYTi59jKFvREW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_02,2025-07-16_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160138 Content-Type: text/plain; charset="utf-8" From: Raviteja Laggyshetty Document the RPMh Network-On-Chip Interconnect in Glymur platform. Signed-off-by: Raviteja Laggyshetty Signed-off-by: Pankaj Patil Reviewed-by: Rob Herring (Arm) --- .../interconnect/qcom,glymur-rpmh.yaml | 84 +++++++ .../interconnect/qcom,glymur-rpmh.h | 205 ++++++++++++++++++ 2 files changed, 289 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,gly= mur-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,glymur-rpmh.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpm= h.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.ya= ml new file mode 100644 index 000000000000..bcf6a708143b --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR + +maintainers: + - Raviteja Laggyshetty + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h + +properties: + compatible: + enum: + - qcom,glymur-aggre1-noc + - qcom,glymur-aggre2-noc + - qcom,glymur-aggre3-noc + - qcom,glymur-aggre4-noc + - qcom,glymur-clk-virt + - qcom,glymur-cnoc-cfg + - qcom,glymur-cnoc-main + - qcom,glymur-hscnoc + - qcom,glymur-lpass-ag-noc + - qcom,glymur-lpass-lpiaon-noc + - qcom,glymur-lpass-lpicx-noc + - qcom,glymur-mc-virt + - qcom,glymur-mmss-noc + - qcom,glymur-nsinoc + - qcom,glymur-nsp-noc + - qcom,glymur-oobm-ss-noc + - qcom,glymur-pcie-east-anoc + - qcom,glymur-pcie-east-slv-noc + - qcom,glymur-pcie-west-anoc + - qcom,glymur-pcie-west-slv-noc + - qcom,glymur-system-noc + + reg: + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-clk-virt + - qcom,glymur-mc-virt + then: + properties: + reg: false + else: + required: + - reg + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-0 { + compatible =3D "qcom,glymur-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,glymur-aggre1-noc"; + reg =3D <0x016e0000 0x14400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; diff --git a/include/dt-bindings/interconnect/qcom,glymur-rpmh.h b/include/= dt-bindings/interconnect/qcom,glymur-rpmh.h new file mode 100644 index 000000000000..6993a686da55 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,glymur-rpmh.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H + +#define MASTER_CRYPTO 0 +#define MASTER_SOCCP_PROC 1 +#define MASTER_QDSS_ETR 2 +#define MASTER_QDSS_ETR_1 3 +#define SLAVE_A1NOC_SNOC 4 + +#define MASTER_UFS_MEM 0 +#define MASTER_USB3_2 1 +#define MASTER_USB4_2 2 +#define SLAVE_A2NOC_SNOC 3 + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_1 2 +#define MASTER_QUP_2 3 +#define MASTER_SP 4 +#define MASTER_SDCC_2 5 +#define MASTER_SDCC_4 6 +#define MASTER_USB2 7 +#define MASTER_USB3_MP 8 +#define SLAVE_A3NOC_SNOC 9 + +#define MASTER_USB3_0 0 +#define MASTER_USB3_1 1 +#define MASTER_USB4_0 2 +#define MASTER_USB4_1 3 +#define SLAVE_A4NOC_HSCNOC 4 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_AHB2PHY_2 3 +#define SLAVE_AHB2PHY_3 4 +#define SLAVE_AV1_ENC_CFG 5 +#define SLAVE_CAMERA_CFG 6 +#define SLAVE_CLK_CTL 7 +#define SLAVE_CRYPTO_0_CFG 8 +#define SLAVE_DISPLAY_CFG 9 +#define SLAVE_GFX3D_CFG 10 +#define SLAVE_IMEM_CFG 11 +#define SLAVE_PCIE_0_CFG 12 +#define SLAVE_PCIE_1_CFG 13 +#define SLAVE_PCIE_2_CFG 14 +#define SLAVE_PCIE_3A_CFG 15 +#define SLAVE_PCIE_3B_CFG 16 +#define SLAVE_PCIE_4_CFG 17 +#define SLAVE_PCIE_5_CFG 18 +#define SLAVE_PCIE_6_CFG 19 +#define SLAVE_PCIE_RSCC 20 +#define SLAVE_PDM 21 +#define SLAVE_PRNG 22 +#define SLAVE_QDSS_CFG 23 +#define SLAVE_QSPI_0 24 +#define SLAVE_QUP_0 25 +#define SLAVE_QUP_1 26 +#define SLAVE_QUP_2 27 +#define SLAVE_SDCC_2 28 +#define SLAVE_SDCC_4 29 +#define SLAVE_SMMUV3_CFG 30 +#define SLAVE_TCSR 31 +#define SLAVE_TLMM 32 +#define SLAVE_UFS_MEM_CFG 33 +#define SLAVE_USB2 34 +#define SLAVE_USB3_0 35 +#define SLAVE_USB3_1 36 +#define SLAVE_USB3_2 37 +#define SLAVE_USB3_MP 38 +#define SLAVE_USB4_0 39 +#define SLAVE_USB4_1 40 +#define SLAVE_USB4_2 41 +#define SLAVE_VENUS_CFG 42 +#define SLAVE_CNOC_PCIE_SLAVE_EAST_CFG 43 +#define SLAVE_CNOC_PCIE_SLAVE_WEST_CFG 44 +#define SLAVE_LPASS_QTB_CFG 45 +#define SLAVE_CNOC_MNOC_CFG 46 +#define SLAVE_NSP_QTB_CFG 47 +#define SLAVE_PCIE_EAST_ANOC_CFG 48 +#define SLAVE_PCIE_WEST_ANOC_CFG 49 +#define SLAVE_QDSS_STM 50 +#define SLAVE_TCU 51 + +#define MASTER_HSCNOC_CNOC 0 +#define SLAVE_AOSS 1 +#define SLAVE_IPC_ROUTER_CFG 2 +#define SLAVE_SOCCP 3 +#define SLAVE_TME_CFG 4 +#define SLAVE_APPSS 5 +#define SLAVE_CNOC_CFG 6 +#define SLAVE_BOOT_IMEM 7 +#define SLAVE_IMEM 8 + +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_AGGRE_NOC_EAST 4 +#define MASTER_GFX3D 5 +#define MASTER_LPASS_GEM_NOC 6 +#define MASTER_MNOC_HF_MEM_NOC 7 +#define MASTER_MNOC_SF_MEM_NOC 8 +#define MASTER_COMPUTE_NOC 9 +#define MASTER_PCIE_EAST 10 +#define MASTER_PCIE_WEST 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define MASTER_WLAN_Q6 13 +#define MASTER_GIC 14 +#define SLAVE_HSCNOC_CNOC 15 +#define SLAVE_LLCC 16 +#define SLAVE_PCIE_EAST 17 +#define SLAVE_PCIE_WEST 18 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_AV1_ENC 0 +#define MASTER_CAMNOC_HF 1 +#define MASTER_CAMNOC_ICP 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_EVA 4 +#define MASTER_MDP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO 7 +#define MASTER_VIDEO_CV_PROC 8 +#define MASTER_VIDEO_V_PROC 9 +#define MASTER_CNOC_MNOC_CFG 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 + +#define MASTER_CPUCP 0 +#define SLAVE_NSINOC_SYSTEM_NOC 1 +#define SLAVE_SERVICE_NSINOC 2 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_NSP0_HSC_NOC 1 + +#define MASTER_OOBMSS_SP_PROC 0 +#define SLAVE_OOBMSS_SNOC 1 + +#define MASTER_PCIE_EAST_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define MASTER_PCIE_5 3 +#define SLAVE_PCIE_EAST_MEM_NOC 4 +#define SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC 5 + +#define MASTER_HSCNOC_PCIE_EAST 0 +#define MASTER_CNOC_PCIE_EAST_SLAVE_CFG 1 +#define SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG 2 +#define SLAVE_SERVICE_PCIE_EAST 3 +#define SLAVE_PCIE_0 4 +#define SLAVE_PCIE_1 5 +#define SLAVE_PCIE_5 6 + +#define MASTER_PCIE_WEST_ANOC_CFG 0 +#define MASTER_PCIE_2 1 +#define MASTER_PCIE_3A 2 +#define MASTER_PCIE_3B 3 +#define MASTER_PCIE_4 4 +#define MASTER_PCIE_6 5 +#define SLAVE_PCIE_WEST_MEM_NOC 6 +#define SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC 7 + +#define MASTER_HSCNOC_PCIE_WEST 0 +#define MASTER_CNOC_PCIE_WEST_SLAVE_CFG 1 +#define SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG 2 +#define SLAVE_SERVICE_PCIE_WEST 3 +#define SLAVE_PCIE_2 4 +#define SLAVE_PCIE_3A 5 +#define SLAVE_PCIE_3B 6 +#define SLAVE_PCIE_4 7 +#define SLAVE_PCIE_6 8 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de42ad9efsm132769455ad.58.2025.07.16.08.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:15:51 -0700 (PDT) From: Pankaj Patil To: djakov@kernel.org, lumag@kernel.org, a39.skl@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, raviteja.laggyshetty@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] interconnect: qcom: add glymur interconnect provider driver Date: Wed, 16 Jul 2025 20:45:35 +0530 Message-Id: <20250716151535.4054172-3-pankaj.patil@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716151535.4054172-1-pankaj.patil@oss.qualcomm.com> References: <20250716151535.4054172-1-pankaj.patil@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=dKimmPZb c=1 sm=1 tr=0 ts=6877c22b cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=7Y5ZrCSegFD1MsWmRDAA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: TyJtUD4D4up2XApCao17K_eH_8zMArdG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDEzOCBTYWx0ZWRfXy2FIqNTlLvyU SrcH8qic4y4ssTuC9d+rN4WofKd9nljDIyOcbkZcIQly+03cH0iD+ypvn5fuvWmABRCIcLYn81Z zOJAce75m9SSBOc7EMmSFu5DTN8ZzEfybJGkE/yBQ31jT/vqViiY8BGsLVfMzIxeBf9XPu2Q6MS W5c+xh0aoEzOyJrMxrUlGggYSSNRAEV9pjPz72tzWUJzwE5y3+LXWd17QYIRCaQZTFAGfa4T9RH ZBFrUuetxtq2u7uvI1xffTDzL92+aKmfbAGHy7Av1yMYKlxKxJoYHTUC3mQQcmall7dBYV5ZNjE cvNjMP21C5TNkY09bcapDAITyb85aI/1qtQjkjwnHkb56ecqmTgZV0XbJ8oT9+++CsGawAHi5fp x9cAl/JN15GBv7tZabQ9q59341XKUenKa/BDqfwqmvc3kG6iuZPsKG9tw7PKMXes92G32dUq X-Proofpoint-ORIG-GUID: TyJtUD4D4up2XApCao17K_eH_8zMArdG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_02,2025-07-16_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1011 mlxlogscore=999 mlxscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160138 Content-Type: text/plain; charset="utf-8" From: Raviteja Laggyshetty Add driver for the Qualcomm interconnect buses found in glymur based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Signed-off-by: Raviteja Laggyshetty Signed-off-by: Pankaj Patil --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/glymur.c | 2259 ++++++++++++++++++++++++++++ drivers/interconnect/qcom/glymur.h | 185 +++ 4 files changed, 2455 insertions(+) create mode 100644 drivers/interconnect/qcom/glymur.c create mode 100644 drivers/interconnect/qcom/glymur.h diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 1219f4f23d40..18234110d4b3 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -8,6 +8,15 @@ config INTERCONNECT_QCOM config INTERCONNECT_QCOM_BCM_VOTER tristate =20 +config INTERCONNECT_QCOM_GLYMUR + tristate "Qualcomm GLYMUR interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on glymur-based + platforms. + config INTERCONNECT_QCOM_MSM8909 tristate "Qualcomm MSM8909 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 7887b1e8d69b..e205f923f85a 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) +=3D interconnect_qcom.o =20 interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o +qnoc-glymur-objs :=3D glymur.o qnoc-msm8909-objs :=3D msm8909.o qnoc-msm8916-objs :=3D msm8916.o qnoc-msm8937-objs :=3D msm8937.o @@ -45,6 +46,7 @@ qnoc-x1e80100-objs :=3D x1e80100.o icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clocks.o =20 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o +obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) +=3D qnoc-glymur.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) +=3D qnoc-msm8937.o diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c new file mode 100644 index 000000000000..f4aa1b085b47 --- /dev/null +++ b/drivers/interconnect/qcom/glymur.c @@ -0,0 +1,2259 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "glymur.h" + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D GLYMUR_MASTER_CRYPTO, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_soccp =3D { + .name =3D "qxm_soccp", + .id =3D GLYMUR_MASTER_SOCCP_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .id =3D GLYMUR_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .id =3D GLYMUR_MASTER_QDSS_ETR_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D GLYMUR_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_2 =3D { + .name =3D "xm_usb3_2", + .id =3D GLYMUR_MASTER_USB3_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb4_2 =3D { + .name =3D "xm_usb4_2", + .id =3D GLYMUR_MASTER_USB4_2, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D GLYMUR_MASTER_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D GLYMUR_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D GLYMUR_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D GLYMUR_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_sp =3D { + .name =3D "qxm_sp", + .id =3D GLYMUR_MASTER_SP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D GLYMUR_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D GLYMUR_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb2_0 =3D { + .name =3D "xm_usb2_0", + .id =3D GLYMUR_MASTER_USB2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_mp =3D { + .name =3D "xm_usb3_mp", + .id =3D GLYMUR_MASTER_USB3_MP, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A3NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D GLYMUR_MASTER_USB3_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A4NOC_HSCNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D GLYMUR_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A4NOC_HSCNOC }, +}; + +static struct qcom_icc_node xm_usb4_0 =3D { + .name =3D "xm_usb4_0", + .id =3D GLYMUR_MASTER_USB4_0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A4NOC_HSCNOC }, +}; + +static struct qcom_icc_node xm_usb4_1 =3D { + .name =3D "xm_usb4_1", + .id =3D GLYMUR_MASTER_USB4_1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_A4NOC_HSCNOC }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .id =3D GLYMUR_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .id =3D GLYMUR_MASTER_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master =3D { + .name =3D "qup2_core_master", + .id =3D GLYMUR_MASTER_QUP_CORE_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qsm_cfg =3D { + .name =3D "qsm_cfg", + .id =3D GLYMUR_MASTER_CNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 51, + .links =3D { GLYMUR_SLAVE_AHB2PHY_SOUTH, GLYMUR_SLAVE_AHB2PHY_NORTH, + GLYMUR_SLAVE_AHB2PHY_2, GLYMUR_SLAVE_AHB2PHY_3, + GLYMUR_SLAVE_AV1_ENC_CFG, GLYMUR_SLAVE_CAMERA_CFG, + GLYMUR_SLAVE_CLK_CTL, GLYMUR_SLAVE_CRYPTO_0_CFG, + GLYMUR_SLAVE_DISPLAY_CFG, GLYMUR_SLAVE_GFX3D_CFG, + GLYMUR_SLAVE_IMEM_CFG, GLYMUR_SLAVE_PCIE_0_CFG, + GLYMUR_SLAVE_PCIE_1_CFG, GLYMUR_SLAVE_PCIE_2_CFG, + GLYMUR_SLAVE_PCIE_3A_CFG, GLYMUR_SLAVE_PCIE_3B_CFG, + GLYMUR_SLAVE_PCIE_4_CFG, GLYMUR_SLAVE_PCIE_5_CFG, + GLYMUR_SLAVE_PCIE_6_CFG, GLYMUR_SLAVE_PCIE_RSCC, + GLYMUR_SLAVE_PDM, GLYMUR_SLAVE_PRNG, + GLYMUR_SLAVE_QDSS_CFG, GLYMUR_SLAVE_QSPI_0, + GLYMUR_SLAVE_QUP_0, GLYMUR_SLAVE_QUP_1, + GLYMUR_SLAVE_QUP_2, GLYMUR_SLAVE_SDCC_2, + GLYMUR_SLAVE_SDCC_4, GLYMUR_SLAVE_SMMUV3_CFG, + GLYMUR_SLAVE_TCSR, GLYMUR_SLAVE_TLMM, + GLYMUR_SLAVE_UFS_MEM_CFG, GLYMUR_SLAVE_USB2, + GLYMUR_SLAVE_USB3_0, GLYMUR_SLAVE_USB3_1, + GLYMUR_SLAVE_USB3_2, GLYMUR_SLAVE_USB3_MP, + GLYMUR_SLAVE_USB4_0, GLYMUR_SLAVE_USB4_1, + GLYMUR_SLAVE_USB4_2, GLYMUR_SLAVE_VENUS_CFG, + GLYMUR_SLAVE_CNOC_PCIE_SLAVE_EAST_CFG, + GLYMUR_SLAVE_CNOC_PCIE_SLAVE_WEST_CFG, + GLYMUR_SLAVE_LPASS_QTB_CFG, GLYMUR_SLAVE_CNOC_MNOC_CFG, + GLYMUR_SLAVE_NSP_QTB_CFG, GLYMUR_SLAVE_PCIE_EAST_ANOC_CFG, + GLYMUR_SLAVE_PCIE_WEST_ANOC_CFG, GLYMUR_SLAVE_QDSS_STM, + GLYMUR_SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_hscnoc_cnoc =3D { + .name =3D "qnm_hscnoc_cnoc", + .id =3D GLYMUR_MASTER_HSCNOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 8, + .links =3D { GLYMUR_SLAVE_AOSS, GLYMUR_SLAVE_IPC_ROUTER_CFG, + GLYMUR_SLAVE_SOCCP, GLYMUR_SLAVE_TME_CFG, + GLYMUR_SLAVE_APPSS, GLYMUR_SLAVE_CNOC_CFG, + GLYMUR_SLAVE_BOOT_IMEM, GLYMUR_SLAVE_IMEM }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .id =3D GLYMUR_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC }, +}; + +static struct qcom_icc_node alm_pcie_qtc =3D { + .name =3D "alm_pcie_qtc", + .id =3D GLYMUR_MASTER_PCIE_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .id =3D GLYMUR_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .id =3D GLYMUR_MASTER_APPSS_PROC, + .channels =3D 6, + .buswidth =3D 32, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_aggre_noc_east =3D { + .name =3D "qnm_aggre_noc_east", + .id =3D GLYMUR_MASTER_AGGRE_NOC_EAST, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D GLYMUR_MASTER_GFX3D, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_lpass =3D { + .name =3D "qnm_lpass", + .id =3D GLYMUR_MASTER_LPASS_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D GLYMUR_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D GLYMUR_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_nsp_noc =3D { + .name =3D "qnm_nsp_noc", + .id =3D GLYMUR_MASTER_COMPUTE_NOC, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_pcie_east =3D { + .name =3D "qnm_pcie_east", + .id =3D GLYMUR_MASTER_PCIE_EAST, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_pcie_west =3D { + .name =3D "qnm_pcie_west", + .id =3D GLYMUR_MASTER_PCIE_WEST, + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D GLYMUR_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node qxm_wlan_q6 =3D { + .name =3D "qxm_wlan_q6", + .id =3D GLYMUR_MASTER_WLAN_Q6, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 4, + .links =3D { GLYMUR_SLAVE_HSCNOC_CNOC, GLYMUR_SLAVE_LLCC, + GLYMUR_SLAVE_PCIE_EAST, GLYMUR_SLAVE_PCIE_WEST }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D GLYMUR_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc =3D { + .name =3D "qnm_lpiaon_noc", + .id =3D GLYMUR_MASTER_LPIAON_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_LPASS_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc =3D { + .name =3D "qnm_lpass_lpinoc", + .id =3D GLYMUR_MASTER_LPASS_LPINOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { + .name =3D "qnm_lpinoc_dsp_qns4m", + .id =3D GLYMUR_MASTER_LPASS_PROC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_LPICX_NOC_LPIAON_NOC }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D GLYMUR_MASTER_LLCC, + .channels =3D 12, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_av1_enc =3D { + .name =3D "qnm_av1_enc", + .id =3D GLYMUR_MASTER_AV1_ENC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .id =3D GLYMUR_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .id =3D GLYMUR_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .id =3D GLYMUR_MASTER_CAMNOC_SF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_eva =3D { + .name =3D "qnm_eva", + .id =3D GLYMUR_MASTER_EVA, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp =3D { + .name =3D "qnm_mdp", + .id =3D GLYMUR_MASTER_MDP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_vapss_hcp =3D { + .name =3D "qnm_vapss_hcp", + .id =3D GLYMUR_MASTER_CDSP_HCP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video =3D { + .name =3D "qnm_video", + .id =3D GLYMUR_MASTER_VIDEO, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu =3D { + .name =3D "qnm_video_cv_cpu", + .id =3D GLYMUR_MASTER_VIDEO_CV_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_v_cpu =3D { + .name =3D "qnm_video_v_cpu", + .id =3D GLYMUR_MASTER_VIDEO_V_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qsm_mnoc_cfg =3D { + .name =3D "qsm_mnoc_cfg", + .id =3D GLYMUR_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node xm_cpucp =3D { + .name =3D "xm_cpucp", + .id =3D GLYMUR_MASTER_CPUCP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_NSINOC_SYSTEM_NOC, GLYMUR_SLAVE_SERVICE_NSINOC = }, +}; + +static struct qcom_icc_node qnm_nsp =3D { + .name =3D "qnm_nsp", + .id =3D GLYMUR_MASTER_CDSP_PROC, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_NSP0_HSC_NOC }, +}; + +static struct qcom_icc_node xm_mem_sp =3D { + .name =3D "xm_mem_sp", + .id =3D GLYMUR_MASTER_OOBMSS_SP_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_OOBMSS_SNOC }, +}; + +static struct qcom_icc_node qsm_pcie_east_anoc_cfg =3D { + .name =3D "qsm_pcie_east_anoc_cfg", + .id =3D GLYMUR_MASTER_PCIE_EAST_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC }, +}; + +static struct qcom_icc_node xm_pcie_0 =3D { + .name =3D "xm_pcie_0", + .id =3D GLYMUR_MASTER_PCIE_0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_EAST_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie_1 =3D { + .name =3D "xm_pcie_1", + .id =3D GLYMUR_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_EAST_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie_5 =3D { + .name =3D "xm_pcie_5", + .id =3D GLYMUR_MASTER_PCIE_5, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_EAST_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie_east =3D { + .name =3D "qnm_hscnoc_pcie_east", + .id =3D GLYMUR_MASTER_HSCNOC_PCIE_EAST, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { GLYMUR_SLAVE_PCIE_0, GLYMUR_SLAVE_PCIE_1, + GLYMUR_SLAVE_PCIE_5 }, +}; + +static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg =3D { + .name =3D "qsm_cnoc_pcie_east_slave_cfg", + .id =3D GLYMUR_MASTER_CNOC_PCIE_EAST_SLAVE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG, GLYMUR_SLAVE_SERVI= CE_PCIE_EAST }, +}; + +static struct qcom_icc_node qsm_pcie_west_anoc_cfg =3D { + .name =3D "qsm_pcie_west_anoc_cfg", + .id =3D GLYMUR_MASTER_PCIE_WEST_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC }, +}; + +static struct qcom_icc_node xm_pcie_2 =3D { + .name =3D "xm_pcie_2", + .id =3D GLYMUR_MASTER_PCIE_2, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_WEST_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie_3a =3D { + .name =3D "xm_pcie_3a", + .id =3D GLYMUR_MASTER_PCIE_3A, + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_WEST_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie_3b =3D { + .name =3D "xm_pcie_3b", + .id =3D GLYMUR_MASTER_PCIE_3B, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_WEST_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie_4 =3D { + .name =3D "xm_pcie_4", + .id =3D GLYMUR_MASTER_PCIE_4, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_WEST_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie_6 =3D { + .name =3D "xm_pcie_6", + .id =3D GLYMUR_MASTER_PCIE_6, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_PCIE_WEST_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie_west =3D { + .name =3D "qnm_hscnoc_pcie_west", + .id =3D GLYMUR_MASTER_HSCNOC_PCIE_WEST, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 5, + .links =3D { GLYMUR_SLAVE_PCIE_2, GLYMUR_SLAVE_PCIE_3A, + GLYMUR_SLAVE_PCIE_3B, GLYMUR_SLAVE_PCIE_4, + GLYMUR_SLAVE_PCIE_6 }, +}; + +static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg =3D { + .name =3D "qsm_cnoc_pcie_west_slave_cfg", + .id =3D GLYMUR_MASTER_CNOC_PCIE_WEST_SLAVE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { GLYMUR_SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG, GLYMUR_SLAVE_SERVI= CE_PCIE_WEST }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D GLYMUR_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D GLYMUR_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre3_noc =3D { + .name =3D "qnm_aggre3_noc", + .id =3D GLYMUR_MASTER_A3NOC_SNOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_nsi_noc =3D { + .name =3D "qnm_nsi_noc", + .id =3D GLYMUR_MASTER_NSINOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_oobmss =3D { + .name =3D "qnm_oobmss", + .id =3D GLYMUR_MASTER_OOBMSS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D GLYMUR_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D GLYMUR_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_a3noc_snoc =3D { + .name =3D "qns_a3noc_snoc", + .id =3D GLYMUR_SLAVE_A3NOC_SNOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_A3NOC_SNOC }, +}; + +static struct qcom_icc_node qns_a4noc_hscnoc =3D { + .name =3D "qns_a4noc_hscnoc", + .id =3D GLYMUR_SLAVE_A4NOC_HSCNOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_AGGRE_NOC_EAST }, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .id =3D GLYMUR_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .id =3D GLYMUR_SLAVE_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qup2_core_slave =3D { + .name =3D "qup2_core_slave", + .id =3D GLYMUR_SLAVE_QUP_CORE_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D GLYMUR_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .id =3D GLYMUR_SLAVE_AHB2PHY_NORTH, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .id =3D GLYMUR_SLAVE_AHB2PHY_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2phy3 =3D { + .name =3D "qhs_ahb2phy3", + .id =3D GLYMUR_SLAVE_AHB2PHY_3, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_av1_enc_cfg =3D { + .name =3D "qhs_av1_enc_cfg", + .id =3D GLYMUR_SLAVE_AV1_ENC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D GLYMUR_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D GLYMUR_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D GLYMUR_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D GLYMUR_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D GLYMUR_SLAVE_GFX3D_CFG, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D GLYMUR_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D GLYMUR_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D GLYMUR_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie2_cfg =3D { + .name =3D "qhs_pcie2_cfg", + .id =3D GLYMUR_SLAVE_PCIE_2_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie3a_cfg =3D { + .name =3D "qhs_pcie3a_cfg", + .id =3D GLYMUR_SLAVE_PCIE_3A_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie3b_cfg =3D { + .name =3D "qhs_pcie3b_cfg", + .id =3D GLYMUR_SLAVE_PCIE_3B_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie4_cfg =3D { + .name =3D "qhs_pcie4_cfg", + .id =3D GLYMUR_SLAVE_PCIE_4_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie5_cfg =3D { + .name =3D "qhs_pcie5_cfg", + .id =3D GLYMUR_SLAVE_PCIE_5_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie6_cfg =3D { + .name =3D "qhs_pcie6_cfg", + .id =3D GLYMUR_SLAVE_PCIE_6_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie_rscc =3D { + .name =3D "qhs_pcie_rscc", + .id =3D GLYMUR_SLAVE_PCIE_RSCC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D GLYMUR_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D GLYMUR_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D GLYMUR_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D GLYMUR_SLAVE_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D GLYMUR_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D GLYMUR_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .id =3D GLYMUR_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D GLYMUR_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D GLYMUR_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_smmuv3_cfg =3D { + .name =3D "qhs_smmuv3_cfg", + .id =3D GLYMUR_SLAVE_SMMUV3_CFG, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D GLYMUR_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D GLYMUR_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D GLYMUR_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb2_0_cfg =3D { + .name =3D "qhs_usb2_0_cfg", + .id =3D GLYMUR_SLAVE_USB2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3_0_cfg =3D { + .name =3D "qhs_usb3_0_cfg", + .id =3D GLYMUR_SLAVE_USB3_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3_1_cfg =3D { + .name =3D "qhs_usb3_1_cfg", + .id =3D GLYMUR_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3_2_cfg =3D { + .name =3D "qhs_usb3_2_cfg", + .id =3D GLYMUR_SLAVE_USB3_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3_mp_cfg =3D { + .name =3D "qhs_usb3_mp_cfg", + .id =3D GLYMUR_SLAVE_USB3_MP, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb4_0_cfg =3D { + .name =3D "qhs_usb4_0_cfg", + .id =3D GLYMUR_SLAVE_USB4_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb4_1_cfg =3D { + .name =3D "qhs_usb4_1_cfg", + .id =3D GLYMUR_SLAVE_USB4_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb4_2_cfg =3D { + .name =3D "qhs_usb4_2_cfg", + .id =3D GLYMUR_SLAVE_USB4_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D GLYMUR_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg =3D { + .name =3D "qss_cnoc_pcie_slave_east_cfg", + .id =3D GLYMUR_SLAVE_CNOC_PCIE_SLAVE_EAST_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_CNOC_PCIE_EAST_SLAVE_CFG }, +}; + +static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg =3D { + .name =3D "qss_cnoc_pcie_slave_west_cfg", + .id =3D GLYMUR_SLAVE_CNOC_PCIE_SLAVE_WEST_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_CNOC_PCIE_WEST_SLAVE_CFG }, +}; + +static struct qcom_icc_node qss_lpass_qtb_cfg =3D { + .name =3D "qss_lpass_qtb_cfg", + .id =3D GLYMUR_SLAVE_LPASS_QTB_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_mnoc_cfg =3D { + .name =3D "qss_mnoc_cfg", + .id =3D GLYMUR_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qss_nsp_qtb_cfg =3D { + .name =3D "qss_nsp_qtb_cfg", + .id =3D GLYMUR_SLAVE_NSP_QTB_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_pcie_east_anoc_cfg =3D { + .name =3D "qss_pcie_east_anoc_cfg", + .id =3D GLYMUR_SLAVE_PCIE_EAST_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_PCIE_EAST_ANOC_CFG }, +}; + +static struct qcom_icc_node qss_pcie_west_anoc_cfg =3D { + .name =3D "qss_pcie_west_anoc_cfg", + .id =3D GLYMUR_SLAVE_PCIE_WEST_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_PCIE_WEST_ANOC_CFG }, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D GLYMUR_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D GLYMUR_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D GLYMUR_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .id =3D GLYMUR_SLAVE_IPC_ROUTER_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_soccp =3D { + .name =3D "qhs_soccp", + .id =3D GLYMUR_SLAVE_SOCCP, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .id =3D GLYMUR_SLAVE_TME_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_apss =3D { + .name =3D "qns_apss", + .id =3D GLYMUR_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .id =3D GLYMUR_SLAVE_CNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_CNOC_CFG }, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .id =3D GLYMUR_SLAVE_BOOT_IMEM, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D GLYMUR_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_hscnoc_cnoc =3D { + .name =3D "qns_hscnoc_cnoc", + .id =3D GLYMUR_SLAVE_HSCNOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_HSCNOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D GLYMUR_SLAVE_LLCC, + .channels =3D 12, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie_east =3D { + .name =3D "qns_pcie_east", + .id =3D GLYMUR_SLAVE_PCIE_EAST, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_HSCNOC_PCIE_EAST }, +}; + +static struct qcom_icc_node qns_pcie_west =3D { + .name =3D "qns_pcie_west", + .id =3D GLYMUR_SLAVE_PCIE_WEST, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_HSCNOC_PCIE_WEST }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { + .name =3D "qns_lpass_ag_noc_gemnoc", + .id =3D GLYMUR_SLAVE_LPASS_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_LPASS_GEM_NOC }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc =3D { + .name =3D "qns_lpass_aggnoc", + .id =3D GLYMUR_SLAVE_LPIAON_NOC_LPASS_AG_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_LPIAON_NOC }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc =3D { + .name =3D "qns_lpi_aon_noc", + .id =3D GLYMUR_SLAVE_LPICX_NOC_LPIAON_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_LPASS_LPINOC }, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D GLYMUR_SLAVE_EBI1, + .channels =3D 8, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D GLYMUR_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D GLYMUR_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D GLYMUR_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_system_noc =3D { + .name =3D "qns_system_noc", + .id =3D GLYMUR_SLAVE_NSINOC_SYSTEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_NSINOC_SNOC }, +}; + +static struct qcom_icc_node srvc_nsinoc =3D { + .name =3D "srvc_nsinoc", + .id =3D GLYMUR_SLAVE_SERVICE_NSINOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_nsp_hscnoc =3D { + .name =3D "qns_nsp_hscnoc", + .id =3D GLYMUR_SLAVE_NSP0_HSC_NOC, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qns_oobmss_snoc =3D { + .name =3D "qns_oobmss_snoc", + .id =3D GLYMUR_SLAVE_OOBMSS_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_OOBMSS }, +}; + +static struct qcom_icc_node qns_pcie_east_mem_noc =3D { + .name =3D "qns_pcie_east_mem_noc", + .id =3D GLYMUR_SLAVE_PCIE_EAST_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_PCIE_EAST }, +}; + +static struct qcom_icc_node srvc_pcie_east_aggre_noc =3D { + .name =3D "srvc_pcie_east_aggre_noc", + .id =3D GLYMUR_SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_hscnoc_pcie_east_ms_mpu_cfg =3D { + .name =3D "qhs_hscnoc_pcie_east_ms_mpu_cfg", + .id =3D GLYMUR_SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_pcie_east =3D { + .name =3D "srvc_pcie_east", + .id =3D GLYMUR_SLAVE_SERVICE_PCIE_EAST, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D GLYMUR_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D GLYMUR_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_5 =3D { + .name =3D "xs_pcie_5", + .id =3D GLYMUR_SLAVE_PCIE_5, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_pcie_west_mem_noc =3D { + .name =3D "qns_pcie_west_mem_noc", + .id =3D GLYMUR_SLAVE_PCIE_WEST_MEM_NOC, + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_PCIE_WEST }, +}; + +static struct qcom_icc_node srvc_pcie_west_aggre_noc =3D { + .name =3D "srvc_pcie_west_aggre_noc", + .id =3D GLYMUR_SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_hscnoc_pcie_west_ms_mpu_cfg =3D { + .name =3D "qhs_hscnoc_pcie_west_ms_mpu_cfg", + .id =3D GLYMUR_SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_pcie_west =3D { + .name =3D "srvc_pcie_west", + .id =3D GLYMUR_SLAVE_SERVICE_PCIE_WEST, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_2 =3D { + .name =3D "xs_pcie_2", + .id =3D GLYMUR_SLAVE_PCIE_2, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_3a =3D { + .name =3D "xs_pcie_3a", + .id =3D GLYMUR_SLAVE_PCIE_3A, + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_3b =3D { + .name =3D "xs_pcie_3b", + .id =3D GLYMUR_SLAVE_PCIE_3B, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_4 =3D { + .name =3D "xs_pcie_4", + .id =3D GLYMUR_SLAVE_PCIE_4, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_6 =3D { + .name =3D "xs_pcie_6", + .id =3D GLYMUR_SLAVE_PCIE_6, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D GLYMUR_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .links =3D { GLYMUR_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D BIT(0), + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .enable_mask =3D BIT(0), + .num_nodes =3D 60, + .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_ahb2phy2, + &qhs_ahb2phy3, &qhs_av1_enc_cfg, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, &qhs_pcie5_cfg, + &qhs_pcie6_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, + &qss_pcie_west_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg, &qnm_hscnoc_cnoc, + &qhs_aoss, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 1, + .nodes =3D { &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp, &qns_nsp_hscnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 =3D { + .name =3D "LP0", + .num_nodes =3D 2, + .nodes =3D { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D BIT(0), + .num_nodes =3D 11, + .nodes =3D { &qnm_av1_enc, &qnm_camnoc_hf, + &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_eva, &qnm_mdp, + &qnm_vapss_hcp, &qnm_video, + &qnm_video_cv_cpu, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 =3D { + .name =3D "QUP2", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D BIT(0), + .num_nodes =3D 18, + .nodes =3D { &alm_gpu_tcu, &alm_pcie_qtc, + &alm_sys_tcu, &chm_apps, + &qnm_aggre_noc_east, &qnm_gpu, + &qnm_lpass, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_noc, + &qnm_pcie_east, &qnm_pcie_west, + &qnm_snoc_sf, &qxm_wlan_q6, + &xm_gic, &qns_hscnoc_cnoc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D BIT(0), + .num_nodes =3D 1, + .nodes =3D { &qnm_oobmss }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre3_noc }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .num_nodes =3D 1, + .nodes =3D { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .num_nodes =3D 4, + .nodes =3D { &qns_pcie_east_mem_noc, &qnm_hscnoc_pcie_east, + &qns_pcie_west_mem_noc, &qnm_hscnoc_pcie_west }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_SOCCP_PROC] =3D &qxm_soccp, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc glymur_aggre1_noc =3D { + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), + .bcms =3D aggre1_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB3_2] =3D &xm_usb3_2, + [MASTER_USB4_2] =3D &xm_usb4_2, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc glymur_aggre2_noc =3D { + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), +}; + +static struct qcom_icc_node * const aggre3_noc_nodes[] =3D { + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_QUP_2] =3D &qhm_qup2, + [MASTER_SP] =3D &qxm_sp, + [MASTER_SDCC_2] =3D &xm_sdc2, + [MASTER_SDCC_4] =3D &xm_sdc4, + [MASTER_USB2] =3D &xm_usb2_0, + [MASTER_USB3_MP] =3D &xm_usb3_mp, + [SLAVE_A3NOC_SNOC] =3D &qns_a3noc_snoc, +}; + +static const struct qcom_icc_desc glymur_aggre3_noc =3D { + .nodes =3D aggre3_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre3_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre4_noc_bcms[] =3D { + &bcm_sn5, +}; + +static struct qcom_icc_node * const aggre4_noc_nodes[] =3D { + [MASTER_USB3_0] =3D &xm_usb3_0, + [MASTER_USB3_1] =3D &xm_usb3_1, + [MASTER_USB4_0] =3D &xm_usb4_0, + [MASTER_USB4_1] =3D &xm_usb4_1, + [SLAVE_A4NOC_HSCNOC] =3D &qns_a4noc_hscnoc, +}; + +static const struct qcom_icc_desc glymur_aggre4_noc =3D { + .nodes =3D aggre4_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre4_noc_nodes), + .bcms =3D aggre4_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre4_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [MASTER_QUP_CORE_2] =3D &qup2_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, + [SLAVE_QUP_CORE_2] =3D &qup2_core_slave, +}; + +static const struct qcom_icc_desc glymur_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] =3D &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] =3D &qhs_ahb2phy3, + [SLAVE_AV1_ENC_CFG] =3D &qhs_av1_enc_cfg, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie1_cfg, + [SLAVE_PCIE_2_CFG] =3D &qhs_pcie2_cfg, + [SLAVE_PCIE_3A_CFG] =3D &qhs_pcie3a_cfg, + [SLAVE_PCIE_3B_CFG] =3D &qhs_pcie3b_cfg, + [SLAVE_PCIE_4_CFG] =3D &qhs_pcie4_cfg, + [SLAVE_PCIE_5_CFG] =3D &qhs_pcie5_cfg, + [SLAVE_PCIE_6_CFG] =3D &qhs_pcie6_cfg, + [SLAVE_PCIE_RSCC] =3D &qhs_pcie_rscc, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_SMMUV3_CFG] =3D &qhs_smmuv3_cfg, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB2] =3D &qhs_usb2_0_cfg, + [SLAVE_USB3_0] =3D &qhs_usb3_0_cfg, + [SLAVE_USB3_1] =3D &qhs_usb3_1_cfg, + [SLAVE_USB3_2] =3D &qhs_usb3_2_cfg, + [SLAVE_USB3_MP] =3D &qhs_usb3_mp_cfg, + [SLAVE_USB4_0] =3D &qhs_usb4_0_cfg, + [SLAVE_USB4_1] =3D &qhs_usb4_1_cfg, + [SLAVE_USB4_2] =3D &qhs_usb4_2_cfg, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] =3D &qss_cnoc_pcie_slave_east_cfg, + [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] =3D &qss_cnoc_pcie_slave_west_cfg, + [SLAVE_LPASS_QTB_CFG] =3D &qss_lpass_qtb_cfg, + [SLAVE_CNOC_MNOC_CFG] =3D &qss_mnoc_cfg, + [SLAVE_NSP_QTB_CFG] =3D &qss_nsp_qtb_cfg, + [SLAVE_PCIE_EAST_ANOC_CFG] =3D &qss_pcie_east_anoc_cfg, + [SLAVE_PCIE_WEST_ANOC_CFG] =3D &qss_pcie_west_anoc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc glymur_cnoc_cfg =3D { + .nodes =3D cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_HSCNOC_CNOC] =3D &qnm_hscnoc_cnoc, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_SOCCP] =3D &qhs_soccp, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_APPSS] =3D &qns_apss, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_BOOT_IMEM] =3D &qxs_boot_imem, + [SLAVE_IMEM] =3D &qxs_imem, +}; + +static const struct qcom_icc_desc glymur_cnoc_main =3D { + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const hscnoc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const hscnoc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_PCIE_TCU] =3D &alm_pcie_qtc, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_AGGRE_NOC_EAST] =3D &qnm_aggre_noc_east, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_noc, + [MASTER_PCIE_EAST] =3D &qnm_pcie_east, + [MASTER_PCIE_WEST] =3D &qnm_pcie_west, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_WLAN_Q6] =3D &qxm_wlan_q6, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_HSCNOC_CNOC] =3D &qns_hscnoc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_PCIE_EAST] =3D &qns_pcie_east, + [SLAVE_PCIE_WEST] =3D &qns_pcie_west, +}; + +static const struct qcom_icc_desc glymur_hscnoc =3D { + .nodes =3D hscnoc_nodes, + .num_nodes =3D ARRAY_SIZE(hscnoc_nodes), + .bcms =3D hscnoc_bcms, + .num_bcms =3D ARRAY_SIZE(hscnoc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { + [MASTER_LPIAON_NOC] =3D &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, +}; + +static const struct qcom_icc_desc glymur_lpass_ag_noc =3D { + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] =3D { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] =3D { + [MASTER_LPASS_LPINOC] =3D &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] =3D &qns_lpass_aggnoc, +}; + +static const struct qcom_icc_desc glymur_lpass_lpiaon_noc =3D { + .nodes =3D lpass_lpiaon_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms =3D lpass_lpiaon_noc_bcms, + .num_bcms =3D ARRAY_SIZE(lpass_lpiaon_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] =3D { + [MASTER_LPASS_PROC] =3D &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] =3D &qns_lpi_aon_noc, +}; + +static const struct qcom_icc_desc glymur_lpass_lpicx_noc =3D { + .nodes =3D lpass_lpicx_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc glymur_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_AV1_ENC] =3D &qnm_av1_enc, + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] =3D &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_EVA] =3D &qnm_eva, + [MASTER_MDP] =3D &qnm_mdp, + [MASTER_CDSP_HCP] =3D &qnm_vapss_hcp, + [MASTER_VIDEO] =3D &qnm_video, + [MASTER_VIDEO_CV_PROC] =3D &qnm_video_cv_cpu, + [MASTER_VIDEO_V_PROC] =3D &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_CFG] =3D &qsm_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, +}; + +static const struct qcom_icc_desc glymur_mmss_noc =3D { + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_node * const nsinoc_nodes[] =3D { + [MASTER_CPUCP] =3D &xm_cpucp, + [SLAVE_NSINOC_SYSTEM_NOC] =3D &qns_system_noc, + [SLAVE_SERVICE_NSINOC] =3D &srvc_nsinoc, +}; + +static const struct qcom_icc_desc glymur_nsinoc =3D { + .nodes =3D nsinoc_nodes, + .num_nodes =3D ARRAY_SIZE(nsinoc_nodes), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] =3D { + [MASTER_CDSP_PROC] =3D &qnm_nsp, + [SLAVE_NSP0_HSC_NOC] =3D &qns_nsp_hscnoc, +}; + +static const struct qcom_icc_desc glymur_nsp_noc =3D { + .nodes =3D nsp_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), + .bcms =3D nsp_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_node * const oobm_ss_noc_nodes[] =3D { + [MASTER_OOBMSS_SP_PROC] =3D &xm_mem_sp, + [SLAVE_OOBMSS_SNOC] =3D &qns_oobmss_snoc, +}; + +static const struct qcom_icc_desc glymur_oobm_ss_noc =3D { + .nodes =3D oobm_ss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(oobm_ss_noc_nodes), +}; + +static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_east_anoc_nodes[] =3D { + [MASTER_PCIE_EAST_ANOC_CFG] =3D &qsm_pcie_east_anoc_cfg, + [MASTER_PCIE_0] =3D &xm_pcie_0, + [MASTER_PCIE_1] =3D &xm_pcie_1, + [MASTER_PCIE_5] =3D &xm_pcie_5, + [SLAVE_PCIE_EAST_MEM_NOC] =3D &qns_pcie_east_mem_noc, + [SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC] =3D &srvc_pcie_east_aggre_noc, +}; + +static const struct qcom_icc_desc glymur_pcie_east_anoc =3D { + .nodes =3D pcie_east_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_east_anoc_nodes), + .bcms =3D pcie_east_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_east_anoc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_east_slv_noc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_east_slv_noc_nodes[] =3D { + [MASTER_HSCNOC_PCIE_EAST] =3D &qnm_hscnoc_pcie_east, + [MASTER_CNOC_PCIE_EAST_SLAVE_CFG] =3D &qsm_cnoc_pcie_east_slave_cfg, + [SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_east_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_EAST] =3D &srvc_pcie_east, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, + [SLAVE_PCIE_5] =3D &xs_pcie_5, +}; + +static const struct qcom_icc_desc glymur_pcie_east_slv_noc =3D { + .nodes =3D pcie_east_slv_noc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_east_slv_noc_nodes), + .bcms =3D pcie_east_slv_noc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_east_slv_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_west_anoc_nodes[] =3D { + [MASTER_PCIE_WEST_ANOC_CFG] =3D &qsm_pcie_west_anoc_cfg, + [MASTER_PCIE_2] =3D &xm_pcie_2, + [MASTER_PCIE_3A] =3D &xm_pcie_3a, + [MASTER_PCIE_3B] =3D &xm_pcie_3b, + [MASTER_PCIE_4] =3D &xm_pcie_4, + [MASTER_PCIE_6] =3D &xm_pcie_6, + [SLAVE_PCIE_WEST_MEM_NOC] =3D &qns_pcie_west_mem_noc, + [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] =3D &srvc_pcie_west_aggre_noc, +}; + +static const struct qcom_icc_desc glymur_pcie_west_anoc =3D { + .nodes =3D pcie_west_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_west_anoc_nodes), + .bcms =3D pcie_west_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_west_anoc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] =3D { + [MASTER_HSCNOC_PCIE_WEST] =3D &qnm_hscnoc_pcie_west, + [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] =3D &qsm_cnoc_pcie_west_slave_cfg, + [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_west_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_WEST] =3D &srvc_pcie_west, + [SLAVE_PCIE_2] =3D &xs_pcie_2, + [SLAVE_PCIE_3A] =3D &xs_pcie_3a, + [SLAVE_PCIE_3B] =3D &xs_pcie_3b, + [SLAVE_PCIE_4] =3D &xs_pcie_4, + [SLAVE_PCIE_6] =3D &xs_pcie_6, +}; + +static const struct qcom_icc_desc glymur_pcie_west_slv_noc =3D { + .nodes =3D pcie_west_slv_noc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_west_slv_noc_nodes), + .bcms =3D pcie_west_slv_noc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_west_slv_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_A3NOC_SNOC] =3D &qnm_aggre3_noc, + [MASTER_NSINOC_SNOC] =3D &qnm_nsi_noc, + [MASTER_OOBMSS] =3D &qnm_oobmss, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, +}; + +static const struct qcom_icc_desc glymur_system_noc =3D { + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,glymur-aggre1-noc", + .data =3D &glymur_aggre1_noc}, + { .compatible =3D "qcom,glymur-aggre2-noc", + .data =3D &glymur_aggre2_noc}, + { .compatible =3D "qcom,glymur-aggre3-noc", + .data =3D &glymur_aggre3_noc}, + { .compatible =3D "qcom,glymur-aggre4-noc", + .data =3D &glymur_aggre4_noc}, + { .compatible =3D "qcom,glymur-clk-virt", + .data =3D &glymur_clk_virt}, + { .compatible =3D "qcom,glymur-cnoc-cfg", + .data =3D &glymur_cnoc_cfg}, + { .compatible =3D "qcom,glymur-cnoc-main", + .data =3D &glymur_cnoc_main}, + { .compatible =3D "qcom,glymur-hscnoc", + .data =3D &glymur_hscnoc}, + { .compatible =3D "qcom,glymur-lpass-ag-noc", + .data =3D &glymur_lpass_ag_noc}, + { .compatible =3D "qcom,glymur-lpass-lpiaon-noc", + .data =3D &glymur_lpass_lpiaon_noc}, + { .compatible =3D "qcom,glymur-lpass-lpicx-noc", + .data =3D &glymur_lpass_lpicx_noc}, + { .compatible =3D "qcom,glymur-mc-virt", + .data =3D &glymur_mc_virt}, + { .compatible =3D "qcom,glymur-mmss-noc", + .data =3D &glymur_mmss_noc}, + { .compatible =3D "qcom,glymur-nsinoc", + .data =3D &glymur_nsinoc}, + { .compatible =3D "qcom,glymur-nsp-noc", + .data =3D &glymur_nsp_noc}, + { .compatible =3D "qcom,glymur-oobm-ss-noc", + .data =3D &glymur_oobm_ss_noc}, + { .compatible =3D "qcom,glymur-pcie-east-anoc", + .data =3D &glymur_pcie_east_anoc}, + { .compatible =3D "qcom,glymur-pcie-east-slv-noc", + .data =3D &glymur_pcie_east_slv_noc}, + { .compatible =3D "qcom,glymur-pcie-west-anoc", + .data =3D &glymur_pcie_west_anoc}, + { .compatible =3D "qcom,glymur-pcie-west-slv-noc", + .data =3D &glymur_pcie_west_slv_noc}, + { .compatible =3D "qcom,glymur-system-noc", + .data =3D &glymur_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-glymur", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("GLYMUR NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/glymur.h b/drivers/interconnect/qcom= /glymur.h new file mode 100644 index 000000000000..cf0ec91775ce --- /dev/null +++ b/drivers/interconnect/qcom/glymur.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_GLYMUR_H +#define __DRIVERS_INTERCONNECT_QCOM_GLYMUR_H + +#define GLYMUR_MASTER_GPU_TCU 0 +#define GLYMUR_MASTER_PCIE_TCU 1 +#define GLYMUR_MASTER_SYS_TCU 2 +#define GLYMUR_MASTER_APPSS_PROC 3 +#define GLYMUR_MASTER_LLCC 4 +#define GLYMUR_MASTER_QSPI_0 5 +#define GLYMUR_MASTER_QUP_0 6 +#define GLYMUR_MASTER_QUP_1 7 +#define GLYMUR_MASTER_QUP_2 8 +#define GLYMUR_MASTER_A1NOC_SNOC 9 +#define GLYMUR_MASTER_A2NOC_SNOC 10 +#define GLYMUR_MASTER_A3NOC_SNOC 11 +#define GLYMUR_MASTER_AGGRE_NOC_EAST 12 +#define GLYMUR_MASTER_AV1_ENC 13 +#define GLYMUR_MASTER_CAMNOC_HF 14 +#define GLYMUR_MASTER_CAMNOC_ICP 15 +#define GLYMUR_MASTER_CAMNOC_SF 16 +#define GLYMUR_MASTER_EVA 17 +#define GLYMUR_MASTER_GFX3D 18 +#define GLYMUR_MASTER_HSCNOC_CNOC 19 +#define GLYMUR_MASTER_HSCNOC_PCIE_EAST 20 +#define GLYMUR_MASTER_HSCNOC_PCIE_WEST 21 +#define GLYMUR_MASTER_LPASS_GEM_NOC 22 +#define GLYMUR_MASTER_LPASS_LPINOC 23 +#define GLYMUR_MASTER_LPIAON_NOC 24 +#define GLYMUR_MASTER_LPASS_PROC 25 +#define GLYMUR_MASTER_MDP 26 +#define GLYMUR_MASTER_MNOC_HF_MEM_NOC 27 +#define GLYMUR_MASTER_MNOC_SF_MEM_NOC 28 +#define GLYMUR_MASTER_NSINOC_SNOC 29 +#define GLYMUR_MASTER_CDSP_PROC 30 +#define GLYMUR_MASTER_COMPUTE_NOC 31 +#define GLYMUR_MASTER_OOBMSS 32 +#define GLYMUR_MASTER_PCIE_EAST 33 +#define GLYMUR_MASTER_PCIE_WEST 34 +#define GLYMUR_MASTER_SNOC_SF_MEM_NOC 35 +#define GLYMUR_MASTER_CDSP_HCP 36 +#define GLYMUR_MASTER_VIDEO 37 +#define GLYMUR_MASTER_VIDEO_CV_PROC 38 +#define GLYMUR_MASTER_VIDEO_V_PROC 39 +#define GLYMUR_MASTER_CNOC_CFG 40 +#define GLYMUR_MASTER_CNOC_PCIE_EAST_SLAVE_CFG 41 +#define GLYMUR_MASTER_CNOC_PCIE_WEST_SLAVE_CFG 42 +#define GLYMUR_MASTER_CNOC_MNOC_CFG 43 +#define GLYMUR_MASTER_PCIE_EAST_ANOC_CFG 44 +#define GLYMUR_MASTER_PCIE_WEST_ANOC_CFG 45 +#define GLYMUR_MASTER_QUP_CORE_0 46 +#define GLYMUR_MASTER_QUP_CORE_1 47 +#define GLYMUR_MASTER_QUP_CORE_2 48 +#define GLYMUR_MASTER_CRYPTO 49 +#define GLYMUR_MASTER_SOCCP_PROC 50 +#define GLYMUR_MASTER_SP 51 +#define GLYMUR_MASTER_WLAN_Q6 52 +#define GLYMUR_MASTER_CPUCP 53 +#define GLYMUR_MASTER_GIC 54 +#define GLYMUR_MASTER_OOBMSS_SP_PROC 55 +#define GLYMUR_MASTER_PCIE_0 56 +#define GLYMUR_MASTER_PCIE_1 57 +#define GLYMUR_MASTER_PCIE_2 58 +#define GLYMUR_MASTER_PCIE_3A 59 +#define GLYMUR_MASTER_PCIE_3B 60 +#define GLYMUR_MASTER_PCIE_4 61 +#define GLYMUR_MASTER_PCIE_5 62 +#define GLYMUR_MASTER_PCIE_6 63 +#define GLYMUR_MASTER_QDSS_ETR 64 +#define GLYMUR_MASTER_QDSS_ETR_1 65 +#define GLYMUR_MASTER_SDCC_2 66 +#define GLYMUR_MASTER_SDCC_4 67 +#define GLYMUR_MASTER_UFS_MEM 68 +#define GLYMUR_MASTER_USB2 69 +#define GLYMUR_MASTER_USB3_0 70 +#define GLYMUR_MASTER_USB3_1 71 +#define GLYMUR_MASTER_USB3_2 72 +#define GLYMUR_MASTER_USB3_MP 73 +#define GLYMUR_MASTER_USB4_0 74 +#define GLYMUR_MASTER_USB4_1 75 +#define GLYMUR_MASTER_USB4_2 76 +#define GLYMUR_SLAVE_EBI1 77 +#define GLYMUR_SLAVE_AHB2PHY_SOUTH 78 +#define GLYMUR_SLAVE_AHB2PHY_NORTH 79 +#define GLYMUR_SLAVE_AHB2PHY_2 80 +#define GLYMUR_SLAVE_AHB2PHY_3 81 +#define GLYMUR_SLAVE_AOSS 82 +#define GLYMUR_SLAVE_AV1_ENC_CFG 83 +#define GLYMUR_SLAVE_CAMERA_CFG 84 +#define GLYMUR_SLAVE_CLK_CTL 85 +#define GLYMUR_SLAVE_CRYPTO_0_CFG 86 +#define GLYMUR_SLAVE_DISPLAY_CFG 87 +#define GLYMUR_SLAVE_GFX3D_CFG 88 +#define GLYMUR_SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG 89 +#define GLYMUR_SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG 90 +#define GLYMUR_SLAVE_IMEM_CFG 91 +#define GLYMUR_SLAVE_IPC_ROUTER_CFG 92 +#define GLYMUR_SLAVE_PCIE_0_CFG 93 +#define GLYMUR_SLAVE_PCIE_1_CFG 94 +#define GLYMUR_SLAVE_PCIE_2_CFG 95 +#define GLYMUR_SLAVE_PCIE_3A_CFG 96 +#define GLYMUR_SLAVE_PCIE_3B_CFG 97 +#define GLYMUR_SLAVE_PCIE_4_CFG 98 +#define GLYMUR_SLAVE_PCIE_5_CFG 99 +#define GLYMUR_SLAVE_PCIE_6_CFG 100 +#define GLYMUR_SLAVE_PCIE_RSCC 101 +#define GLYMUR_SLAVE_PDM 102 +#define GLYMUR_SLAVE_PRNG 103 +#define GLYMUR_SLAVE_QDSS_CFG 104 +#define GLYMUR_SLAVE_QSPI_0 105 +#define GLYMUR_SLAVE_QUP_0 106 +#define GLYMUR_SLAVE_QUP_1 107 +#define GLYMUR_SLAVE_QUP_2 108 +#define GLYMUR_SLAVE_SDCC_2 109 +#define GLYMUR_SLAVE_SDCC_4 110 +#define GLYMUR_SLAVE_SMMUV3_CFG 111 +#define GLYMUR_SLAVE_SOCCP 112 +#define GLYMUR_SLAVE_TCSR 113 +#define GLYMUR_SLAVE_TLMM 114 +#define GLYMUR_SLAVE_TME_CFG 115 +#define GLYMUR_SLAVE_UFS_MEM_CFG 116 +#define GLYMUR_SLAVE_USB2 117 +#define GLYMUR_SLAVE_USB3_0 118 +#define GLYMUR_SLAVE_USB3_1 119 +#define GLYMUR_SLAVE_USB3_2 120 +#define GLYMUR_SLAVE_USB3_MP 121 +#define GLYMUR_SLAVE_USB4_0 122 +#define GLYMUR_SLAVE_USB4_1 123 +#define GLYMUR_SLAVE_USB4_2 124 +#define GLYMUR_SLAVE_VENUS_CFG 125 +#define GLYMUR_SLAVE_A1NOC_SNOC 126 +#define GLYMUR_SLAVE_A2NOC_SNOC 127 +#define GLYMUR_SLAVE_A3NOC_SNOC 128 +#define GLYMUR_SLAVE_A4NOC_HSCNOC 129 +#define GLYMUR_SLAVE_APPSS 130 +#define GLYMUR_SLAVE_SNOC_GEM_NOC_SF 131 +#define GLYMUR_SLAVE_HSCNOC_CNOC 132 +#define GLYMUR_SLAVE_LLCC 133 +#define GLYMUR_SLAVE_LPASS_GEM_NOC 134 +#define GLYMUR_SLAVE_LPIAON_NOC_LPASS_AG_NOC 135 +#define GLYMUR_SLAVE_LPICX_NOC_LPIAON_NOC 136 +#define GLYMUR_SLAVE_MNOC_HF_MEM_NOC 137 +#define GLYMUR_SLAVE_MNOC_SF_MEM_NOC 138 +#define GLYMUR_SLAVE_NSP0_HSC_NOC 139 +#define GLYMUR_SLAVE_OOBMSS_SNOC 140 +#define GLYMUR_SLAVE_PCIE_EAST 141 +#define GLYMUR_SLAVE_PCIE_EAST_MEM_NOC 142 +#define GLYMUR_SLAVE_PCIE_WEST 143 +#define GLYMUR_SLAVE_PCIE_WEST_MEM_NOC 144 +#define GLYMUR_SLAVE_NSINOC_SYSTEM_NOC 145 +#define GLYMUR_SLAVE_CNOC_CFG 146 +#define GLYMUR_SLAVE_CNOC_PCIE_SLAVE_EAST_CFG 147 +#define GLYMUR_SLAVE_CNOC_PCIE_SLAVE_WEST_CFG 148 +#define GLYMUR_SLAVE_LPASS_QTB_CFG 149 +#define GLYMUR_SLAVE_CNOC_MNOC_CFG 150 +#define GLYMUR_SLAVE_NSP_QTB_CFG 151 +#define GLYMUR_SLAVE_PCIE_EAST_ANOC_CFG 152 +#define GLYMUR_SLAVE_PCIE_WEST_ANOC_CFG 153 +#define GLYMUR_SLAVE_QUP_CORE_0 154 +#define GLYMUR_SLAVE_QUP_CORE_1 155 +#define GLYMUR_SLAVE_QUP_CORE_2 156 +#define GLYMUR_SLAVE_BOOT_IMEM 157 +#define GLYMUR_SLAVE_IMEM 158 +#define GLYMUR_SLAVE_SERVICE_MNOC 159 +#define GLYMUR_SLAVE_SERVICE_NSINOC 160 +#define GLYMUR_SLAVE_SERVICE_PCIE_EAST 161 +#define GLYMUR_SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC 162 +#define GLYMUR_SLAVE_SERVICE_PCIE_WEST 163 +#define GLYMUR_SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC 164 +#define GLYMUR_SLAVE_PCIE_0 165 +#define GLYMUR_SLAVE_PCIE_1 166 +#define GLYMUR_SLAVE_PCIE_2 167 +#define GLYMUR_SLAVE_PCIE_3A 168 +#define GLYMUR_SLAVE_PCIE_3B 169 +#define GLYMUR_SLAVE_PCIE_4 170 +#define GLYMUR_SLAVE_PCIE_5 171 +#define GLYMUR_SLAVE_PCIE_6 172 +#define GLYMUR_SLAVE_QDSS_STM 173 +#define GLYMUR_SLAVE_TCU 174 + +#endif --=20 2.34.1