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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3bbe6f56a9sm13713112a12.59.2025.07.16.08.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:08:42 -0700 (PDT) From: Pankaj Patil To: andersson@kernel.org, linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add Glymur pinctrl bindings Date: Wed, 16 Jul 2025 20:38:21 +0530 Message-Id: <20250716150822.4039250-2-pankaj.patil@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716150822.4039250-1-pankaj.patil@oss.qualcomm.com> References: <20250716150822.4039250-1-pankaj.patil@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: PZaud_5M7QtpPZ2hwvhsSgzJEjEyjjeI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDEzNiBTYWx0ZWRfX23XImjodvloL 3LMbtdm1evkmf7LSTFPaiYLXRaJ3SrsGoQksOkYrYTeH7g8/Bpts/8W1t/pP6zGLSbE2a2IdurY 9KG3EWccCy+SP/XeZ5gjazBRsFJf8bBKOHgR0vHVzeva0RezgmP5gCIBiuF0+sB54UhxUe+c8BL DRhlMshIn9N9J3iS+4DGrtdfVdOnb/fW+MLurmzJWA+1jC1pwciPvHXcfxrXFmv/3Gytyh0eE1A tB7txbv9u8qa+24polaykhR1W9b4cVtHiySdongw+uIKcdt80lpbwiRGdWhJ0TkVCe01zkRpljy 4ClSlJhVd154jGQf64vlVzBNeXpXMYonEq1kK3Idx/gLULKG+Qluqb1ttTU4Sx77kU118ZecyPv jI46xpSIDiq8o/NW9KbgcJYkSIpkcR/OybY5dIICfUfdA8yUO0AUVEDTzfepOvmaz1+hiE7E X-Authority-Analysis: v=2.4 cv=WqUrMcfv c=1 sm=1 tr=0 ts=6877c07c cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=u--hiq7dTte3EtGYD-cA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: PZaud_5M7QtpPZ2hwvhsSgzJEjEyjjeI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_02,2025-07-16_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160136 Content-Type: text/plain; charset="utf-8" Add DeviceTree binding for Glymur SoC TLMM block Signed-off-by: Pankaj Patil --- .../bindings/pinctrl/qcom,glymur-tlmm.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,glymur-t= lmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yam= l b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml new file mode 100644 index 000000000000..d767a6f5b5b5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Glymur TLMM block + +maintainers: + - Bjorn Andersson + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,glymur-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 119 + + gpio-line-names: + maxItems: 238 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-glymur-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-glymur-tlmm-state" + additionalProperties: false + +$defs: + qcom-glymur-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, RESOUT_GPIO_N, aoss_cti, asc_cci, atest_char, atest_= usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4, cam_mclk, c= ci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, cmu_rng, cri_trng, dbg_out_clk, dd= r_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi, edp= 0_hot, edp0_lcd, + edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en, eusb2_ac_en, eu= sb3_ac_en, eusb5_ac_en, + eusb6_ac_en, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2c= 0_s_scl, i2c0_s_sda, + i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws= , ibi_i3c, jitter_bist, + mdp_vsync_out, mdp_vsync_e, mdp_vsync_p, mdp_vsync_s, pcie= 3a_clk, pcie3a_rst_n, + pcie3b_clk, pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_re= q_n, phase_flag, + pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_ros= c, qdss_cti, qdss_gpio, + qspi, qup0_se0, qup0_se1, qup0_se2, qup0_se3_l0, qup0_se3,= qup0_se4, qup0_se5, + qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3= , qup1_se4, qup1_se5, + qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3= , qup2_se4, qup2_se5, + qup2_se6, qup2_se7, qup3_se0, qup3_se1, sd_write_protect, = sdc4_clk, + sdc4_cmd, sdc4_data, smb_acok_n, sys_throttle, tb_trig_sdc= 2, tb_trig_sdc4, + tmess_prng, tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps= , usb0_sbrx, usb0_sbtx, + usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx, usb1_= sbtx, usb1_tmu, usb2_dp, + usb2_phy_ps, usb2_sbrx, usb2_sbtx, usb2_tmu, vsense_trigge= r_mirnat, wcn_sw, + wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible =3D "qcom,glymur-tlmm"; + reg =3D <0 0x0f100000 0 0xf00000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 249>; + wakeup-parent =3D <&pdc>; + gpio-reserved-ranges =3D <4 4>, <10 2>, <33 3>, <44 4>; + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins =3D "gpio86"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio87"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + }; + }; +... --=20 2.34.1