From nobody Tue Oct 7 02:15:49 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BEC5F2F3C2F; Wed, 16 Jul 2025 10:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752660354; cv=none; b=HK26EHPMb3e0JPKcc7o71v0omxfNYQ6bX34E3aPWztmdw9B2F+c6ZSjr0aaHnpAATBPHcCznkDNtOvxjR9reLWKj22NWUoEPlhVvgdVjCTXLDq7C56pS+IsXinzoRhN89v1SWkpNQmQ1KAS6xiFjyov7cxnunxVGt3cblZ1aJg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752660354; c=relaxed/simple; bh=TlFF/wWOnyBUBw2sRYOnF2RANPrGvlRG2sNYPUnSxe0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UeotbHtuICE+EbG8RhepWJ7Q6PgJRsUO3lFKL9dTDjHxm1REgXNX7vLUpEe3fcOW98Y0CHxkv9BK7QEWSYHDlnYyEeClZEzg/museiI4Ly7vbq02pRWrlCrxVinEMmlPahU7BXt1S3QzDo9cDyBOb1YdXzOiAA4KK2aJgty1wIM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=lHtS3x/K; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="lHtS3x/K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=Pf 96EL1fdLyOPgckgwexr7VHAXtwv685XpN6hfJsmNc=; b=lHtS3x/Kc95+Jei4n2 d5KAele+qQIiFpsFIE37B7SildtLfC/HXjlJQ9TLCsNDrA8yMTz2Tw1tDh+eJgqR 0Tg5VAC7tnnBHhID4W1695mWeA+UIjUdQk35Zf9zQWcxb18wgEfrZJupZUBgtf3p qF3ZAQWLbpgA7S1xflwyeJa2U= Received: from ProDesk.. (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wAH0s46eXdoG0BuFQ--.1985S9; Wed, 16 Jul 2025 18:05:07 +0800 (CST) From: Andy Yan To: dmitry.baryshkov@oss.qualcomm.com, heiko@sntech.de Cc: hjc@rock-chips.com, mripard@kernel.org, naoki@radxa.com, stephen@radxa.com, cristian.ciocaltea@collabora.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, yubing.zhang@rock-chips.com, krzk+dt@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, robh@kernel.org, sebastian.reichel@collabora.com, Andy Yan Subject: [PATCH v5 07/10] arm64: dts: rockchip: Add DP0 for rk3588 Date: Wed, 16 Jul 2025 18:04:34 +0800 Message-ID: <20250716100440.816351-8-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250716100440.816351-1-andyshrk@163.com> References: <20250716100440.816351-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAH0s46eXdoG0BuFQ--.1985S9 X-Coremail-Antispam: 1Uf129KBjvJXoW7AFyxJryUuw43JrWfGry5CFg_yoW8XFW5p3 ZrCrZ3WrW8uF12q39xKw1ktrZ5Aan5CFZYkrnrK340kF1Sqr9rKryfKrnxA34qqr47XwsF vFs3try8KFsrAaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07j8a9-UUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEgWMXmh3cPPqbgABsc Content-Type: text/plain; charset="utf-8" From: Andy Yan The DP0 is compliant with the DisplayPort Specification Version 1.4, and share the USBDP combo PHY0 with USB 3.1 HOST0 controller. Signed-off-by: Andy Yan --- (no changes since v1) arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 51f11b9c414aa..4a54389c89d75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1536,6 +1536,36 @@ dsi1_out: port@1 { }; }; =20 + dp0: dp@fde50000 { + compatible =3D "rockchip,rk3588-dp"; + reg =3D <0x0 0xfde50000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names =3D "apb", "aux", "hdcp", "i2s", "spdif"; + assigned-clocks =3D <&cru CLK_AUX16M_0>; + assigned-clock-rates =3D <16000000>; + resets =3D <&cru SRST_DP0>; + phys =3D <&usbdp_phy0 PHY_TYPE_DP>; + power-domains =3D <&power RK3588_PD_VO0>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp0_in: port@0 { + reg =3D <0>; + }; + + dp0_out: port@1 { + reg =3D <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible =3D "rockchip,rk3588-dw-hdmi-qp"; reg =3D <0x0 0xfde80000 0x0 0x20000>; --=20 2.43.0