From nobody Tue Oct 7 00:22:41 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 773132E36E1; Wed, 16 Jul 2025 06:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752645685; cv=none; b=pPg+0hNbE0SJRVOndfYpFhilQy3mglmNjwkoHYo2ouPlCpK62C8B/mlPUWO0ToRFCAu1DdbWQevyWZXGa/UvVWr7vkGvxpri+LdtptTOmVAU2wy6tqO93ILvtStYxQQFKKePbq8hIbDAyUsZDe/fjhU1X5/Ri7HxrI5QKJQTJ1w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752645685; c=relaxed/simple; bh=1fCStZX3mt915rvbulJ87SbYb7H/Cy4thel9HGPGw/g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c5JHeRvXBGvcBnmivgYY582HyMt7Fe/Nr9Y3Jp48TP1PZ545N/TZW7XA8QO86AWbSwvQHGsHFeB1JLI5wNQ9C+oI7/UbCFLzhU3t5yeALpZ1ie6+r2fWgzVJT4EplaQUT0OtLsWuPfELhpMXyIIs7c+uhwqNEY2Zc4ov2BPIr9E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=URcwswEW; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="URcwswEW" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 56G61IHg2432886; Wed, 16 Jul 2025 01:01:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1752645678; bh=7w+S7GFgr0YHVfJ4iWbaw2/Qd8QSI91jR74dH7GPb4k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=URcwswEWjv26/eP3Olbh3S8QLQYD5n0qd4TthfHjwA+BZFHqeLX1rhmC5v/5rOydm 40onyYOED1q7NgRL8pEiVEl5GWfIj6QGx0eEmxQs54NLH5BKIPBUfXFJg9jq2ikesd bpjNN7HzPLGsAzksLJq8V0jQl4merqvv7JpoP39Y= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 56G61HUD622808 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 16 Jul 2025 01:01:18 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 16 Jul 2025 01:01:17 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 16 Jul 2025 01:01:17 -0500 Received: from localhost (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [172.24.227.166]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 56G61GRe3832848; Wed, 16 Jul 2025 01:01:17 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , , Subject: [PATCH v3 1/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: add DSI & DSI PHY Date: Wed, 16 Jul 2025 11:31:08 +0530 Message-ID: <20250716060114.52122-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716060114.52122-1-j-choudhary@ti.com> References: <20250716060114.52122-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 7c5b0c69897d..79d97d46b4c6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2522,6 +2522,45 @@ watchdog18: watchdog@2550000 { status =3D "reserved"; }; =20 + dphy_tx0: phy@4480000 { + compatible =3D "ti,j721e-dphy"; + reg =3D <0x00 0x04480000 0x00 0x00001000>; + clocks =3D <&k3_clks 402 20>, <&k3_clks 402 3>; + clock-names =3D "psm", "pll_ref"; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 402 3>; + assigned-clock-parents =3D <&k3_clks 402 4>; + assigned-clock-rates =3D <19200000>; + status =3D "disabled"; + }; + + dsi0: dsi@4800000 { + compatible =3D "ti,j721e-dsi"; + reg =3D <0x00 0x04800000 0x00 0x00100000>, + <0x00 0x04710000 0x00 0x00000100>; + clocks =3D <&k3_clks 215 2>, <&k3_clks 215 5>; + clock-names =3D "dsi_p_clk", "dsi_sys_clk"; + power-domains =3D <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + interrupts =3D ; + phys =3D <&dphy_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + + dsi0_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + mhdp: bridge@a000000 { compatible =3D "ti,j721e-mhdp8546"; reg =3D <0x0 0xa000000 0x0 0x30a00>, --=20 2.34.1 From nobody Tue Oct 7 00:22:41 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C068246BA7; Wed, 16 Jul 2025 06:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 16 Jul 2025 01:01:19 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 16 Jul 2025 01:01:19 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 16 Jul 2025 01:01:19 -0500 Received: from localhost (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [172.24.227.166]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 56G61IoZ4147917; Wed, 16 Jul 2025 01:01:19 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , , Subject: [PATCH v3 2/7] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable DisplayPort-1 Date: Wed, 16 Jul 2025 11:31:09 +0530 Message-ID: <20250716060114.52122-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716060114.52122-1-j-choudhary@ti.com> References: <20250716060114.52122-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Enable DSI display for J784S4 EVM. Add DT node for DSI-to-eDP bridge. The DSI to eDP bridge is SN65DSI86 on the board. Add the endpoint nodes to describe connection from: DSS =3D> DSI =3D> SN65DSI86 bridge =3D> DisplayPort-1 Set status for all required nodes for display as 'okay'. Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 121 +++++++++++++++++- 1 file changed, 120 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index fa656b7b13a1..7b2d8d140c33 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -301,6 +301,52 @@ codec_audio: sound { clock-names =3D "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", "cpb-codec-scki", "cpb-codec-scki-48000"; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <19200000>; + }; + + dp1_pwr_3v3: regulator-dp1-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp1-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp1: connector-dp1 { + compatible =3D "dp-connector"; + label =3D "DP1"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint =3D <&dp1_out>; + }; + }; + }; }; =20 &wkup_gpio0 { @@ -1340,12 +1386,26 @@ &mhdp { }; =20 &dss_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* DP */ - port { + port@0 { + reg =3D <0>; + dpi0_out: endpoint { remote-endpoint =3D <&dp0_in>; }; }; + + /* DSI */ + port@2 { + reg =3D <2>; + + dpi2_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; }; =20 &main_i2c4 { @@ -1360,6 +1420,65 @@ exp4: gpio@20 { gpio-controller; #gpio-cells =3D <2>; }; + + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible =3D "ti,sn65dsi86"; + reg =3D <0x2c>; + clock-names =3D "refclk"; + clocks =3D <&edp1_refclk>; + enable-gpios =3D <&exp4 2 GPIO_ACTIVE_HIGH>; + vpll-supply =3D <&vsys_io_1v8>; + vccio-supply =3D <&vsys_io_1v8>; + vcca-supply =3D <&vsys_io_1v2>; + vcc-supply =3D <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dp1_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dp1_out: endpoint { + remote-endpoint =3D <&dp1_connector_in>; + }; + }; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg =3D <0>; + + dsi0_out: endpoint { + remote-endpoint =3D <&dp1_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi0_in: endpoint { + remote-endpoint =3D <&dpi2_out>; + }; + }; +}; + +&dphy_tx0 { + status =3D "okay"; +}; + +&dsi0 { + status =3D "okay"; }; =20 &dp0_ports { --=20 2.34.1 From nobody Tue Oct 7 00:22:41 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 204492E8E04; Wed, 16 Jul 2025 06:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752645688; cv=none; b=dlEZ0S4JfVdXXwadWNUYs6QK9vA3PwiLjhzxjj7CBQySfhF10MxUd51XNIGo47IcCudPqwrSL/3Vs5/l3lOm+UhaKCrxDEX4dQk4xIzbHugvSjyljJAugA99Xiex+7hnA8QbmMN3EL33IxHNcfNbcUd7NtDLiZWVJYnl8VSh47c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752645688; c=relaxed/simple; bh=zQt8S3CLXfWkf+M5qQ6BLGEDAWOk6LiBrYHizyFAKFA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Wed, 16 Jul 2025 01:01:20 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , , Subject: [PATCH v3 3/7] arm64: dts: ti: k3-j721s2-main: add DSI & DSI PHY Date: Wed, 16 Jul 2025 11:31:10 +0530 Message-ID: <20250716060114.52122-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716060114.52122-1-j-choudhary@ti.com> References: <20250716060114.52122-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Rahul T R Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by: Rahul T R [j-choudhary@ti.com: disable dsi and dphy nodes, rename dphy node] Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 62f45377a2c9..c31d7f3eab28 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1795,6 +1795,45 @@ main_spi7: spi@2170000 { status =3D "disabled"; }; =20 + dphy_tx0: phy@4480000 { + compatible =3D "ti,j721e-dphy"; + reg =3D <0x00 0x04480000 0x00 0x00001000>; + clocks =3D <&k3_clks 363 8>, <&k3_clks 363 14>; + clock-names =3D "psm", "pll_ref"; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 363 14>; + assigned-clock-parents =3D <&k3_clks 363 15>; + assigned-clock-rates =3D <19200000>; + status =3D "disabled"; + }; + + dsi0: dsi@4800000 { + compatible =3D "ti,j721e-dsi"; + reg =3D <0x00 0x04800000 0x00 0x00100000>, + <0x00 0x04710000 0x00 0x00000100>; + clocks =3D <&k3_clks 154 4>, <&k3_clks 154 1>; + clock-names =3D "dsi_p_clk", "dsi_sys_clk"; + power-domains =3D <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + interrupts =3D ; + phys =3D <&dphy_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + + dsi0_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + dss: dss@4a00000 { compatible =3D "ti,j721e-dss"; reg =3D <0x00 0x04a00000 0x00 0x10000>, /* common_m */ --=20 2.34.1 From nobody Tue Oct 7 00:22:41 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B43852EA48C; Wed, 16 Jul 2025 06:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add dt node for main_i2c4 instance along with required pinmuxing. Also add the gpio expander 'exp4' required by display connector. Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- .../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e2fc1288ed07..793d50344fad 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -148,6 +148,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MC= ASP2_AXR1.I2C3_SDA */ >; }; =20 + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */ + >; + }; + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ @@ -370,6 +377,23 @@ exp2: gpio@22 { }; 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charset="utf-8" From: Rahul T R Add DT nodes for DSI to eDP bridge. The DSI to eDP bridge used is SN65DSI86 on SOM. Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 51 ++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 54fc5c4f8c3f..194f34cb08d2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -152,6 +152,30 @@ transceiver0: can-phy0 { #phy-cells =3D <0>; max-bitrate =3D <5000000>; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; 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charset="utf-8" Enable DSI display for J721S2 EVM. Add the endpoint nodes to describe connection from: DSS =3D> DSI Bridge =3D> DSI to eDP bridge =3D> DisplayPort-1 Set status for all required nodes for DisplayPort-1 as 'okay'. Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- .../dts/ti/k3-j721s2-common-proc-board.dts | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 793d50344fad..9e43dcff8ef2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -93,6 +93,28 @@ vdd_sd_dv: gpio-regulator-TLV71033 { <3300000 0x1>; }; =20 + dp1_pwr_3v3: regulator-dp1-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp1-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + }; + + dp1: connector-dp1 { + compatible =3D "dp-connector"; + label =3D "DP1"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint =3D <&dp1_out>; + }; + }; + }; + transceiver1: can-phy1 { compatible =3D "ti,tcan1043"; #phy-cells =3D <0>; @@ -563,3 +585,74 @@ &main_mcan5 { pinctrl-0 =3D <&main_mcan5_pins_default>; phys =3D <&transceiver4>; }; + +&dss { + /* + * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2. + * These clock assignments are chosen to enable the following outputs: + * VP0 - DisplayPort SST + * VP2 - DSI + */ + status =3D "okay"; + assigned-clocks =3D <&k3_clks 158 2>, + <&k3_clks 158 14>; + assigned-clock-parents =3D <&k3_clks 158 3>, + <&k3_clks 158 16>; +}; + +&dss_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + dpi2_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg =3D <0>; + + dsi0_out: endpoint { + remote-endpoint =3D <&dp1_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi0_in: endpoint { + remote-endpoint =3D <&dpi2_out>; + }; + }; +}; + +&dsi_edp_bridge_ports { + port@0 { + reg =3D <0>; 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Wed, 16 Jul 2025 01:01:28 -0500 Received: from localhost (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [172.24.227.166]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 56G61RAb3833131; Wed, 16 Jul 2025 01:01:28 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , , Subject: [PATCH v3 7/7] arm64: dts: ti: k3-am68-sk: Enable DSI on DisplayPort-0 Date: Wed, 16 Jul 2025 11:31:14 +0530 Message-ID: <20250716060114.52122-8-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716060114.52122-1-j-choudhary@ti.com> References: <20250716060114.52122-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Enable DSI support for AM68-SK platform. Add DT node for DSI2eDP bridge. The DSI to eDP bridge is sn65dsi86 on the board. Add the endpoint nodes to describe connection from: DSS =3D> DSI =3D> SN65DSI86 bridge =3D> DisplayPort-0 Set status for all required nodes for DisplayPort-0 as 'okay'. Signed-off-by: Jayesh Choudhary Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Tested-by: Harikrishna Shenoy --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index e84c504c87d2..cf42a001b2ef 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -135,6 +135,34 @@ transceiver4: can-phy3 { max-bitrate =3D <5000000>; }; =20 + edp0_refclk: clock-edp0-refclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <19200000>; + }; + + dp0_pwr_3v3: regulator-dp0-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp0-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */ + enable-active-high; + }; + + dp0: dp0-connector { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&dp0_out>; + }; + }; + }; + connector-hdmi { compatible =3D "hdmi-connector"; label =3D "hdmi"; @@ -615,6 +643,39 @@ exp2: gpio@20 { gpio-line-names =3D "HDMI_PDn","HDMI_LS_OE", "DP0_3V3_EN","eDP_ENABLE"; }; + + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible =3D "ti,sn65dsi86"; + reg =3D <0x2c>; + clock-names =3D "refclk"; + clocks =3D <&edp0_refclk>; + enable-gpios =3D <&exp2 3 GPIO_ACTIVE_HIGH>; + vpll-supply =3D <&vsys_io_1v8>; + vccio-supply =3D <&vsys_io_1v8>; + vcca-supply =3D <&vsys_io_1v2>; + vcc-supply =3D <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dp0_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dp0_out: endpoint { + remote-endpoint =3D <&dp0_connector_in>; + }; + }; + }; + }; }; =20 &main_sdhci1 { @@ -711,6 +772,15 @@ dpi_out0: endpoint { remote-endpoint =3D <&tfp410_in>; }; }; + + /* DSI */ + port@2 { + reg =3D <2>; + + dpi0_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; }; =20 &serdes_ln_ctrl { @@ -768,3 +838,30 @@ &usb0 { phys =3D <&serdes0_usb_link>; phy-names =3D "cdns3,usb3-phy"; }; + +&dphy_tx0 { + status =3D "okay"; +}; + +&dsi0 { + status =3D "okay"; +}; + +&dsi0_ports { + + port@0 { + reg =3D <0>; + + dsi0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi0_in: endpoint { + remote-endpoint =3D <&dpi0_out>; + }; + }; +}; --=20 2.34.1