From nobody Tue Oct 7 01:58:31 2025 Received: from mta-64-226.siemens.flowmailer.net (mta-64-226.siemens.flowmailer.net [185.136.64.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEDED2E7BA9 for ; Wed, 16 Jul 2025 05:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752644439; cv=none; b=DODfdrH66G+zQ4a82fHWRYxMNEeDHd+efG99aaocX0dObRSaqUqXoasYZluNd7SI/NImK+amLguHrC17tVjn/xNQQHPZXcQ+FqbdIjaQmx14NEUV8YlcFtxC6NiQBj2xcgBRLv0kqV9HqBDmOC41wm8srJyj0MYnIKjxbEKGsxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752644439; c=relaxed/simple; bh=dS3Vq/AtXU+TxZP7QmUzQG/h1E9LjY5aHSbcuNRJ2HM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hKgk64Ld1lZw7pHba0cJbhisrT+Q1THD1leIdvOnFIdiBoakLshEy+bfNAWsWzGOPxdF2EZEvjASK+EPVF8jPTmafAvku+W5JhaSh0BITfkhzlFYpVox3HL9bu1QrcgCNRUcqFQ1eWRD3Q0j8c5YNyQcrSuZTKCqmZOJSWRToOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b=RAigvxSt; arc=none smtp.client-ip=185.136.64.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=huaqian.li@siemens.com header.b="RAigvxSt" Received: by mta-64-226.siemens.flowmailer.net with ESMTPSA id 20250716054035df2d35022dc0e16ba1 for ; Wed, 16 Jul 2025 07:40:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=huaqian.li@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=SCQPF5NJaTXFf43IS370UO0r+J/hStgHdQgUeUn8d7s=; b=RAigvxStEMe7GjHWiTDFnEEu81/Tx6Wb2zcSV16tuBIVDuQJykY6wtuU5xNnpgJCzXW4I5 4DW9rx8L36ujZw1U8ryTK91X23lRO+PhKDU8gZoaAa7IqzvyNTqCvYFJCZ+L9slEfoSNZVBi HW3keAsWK1seATHlNW/zCX66M6Tj6i5H9Gzo+Kvr2m8ugXW4WnbJoL0qhMjXNvpRVMX+7NQx +vt7uh7xjTubrTs771mkQ2BWb5FAzVtado3FGMvCWR6CLtd4L0TAXvfxcQINY8uInXw4udjV K7973wZv6PYl6m78bFSXHu6P7Qqentff/7FBsDn8Awt0WWNJ22E0yr4w==; From: huaqian.li@siemens.com To: s-vadapalli@ti.com Cc: baocheng.su@siemens.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, diogo.ivo@siemens.com, helgaas@kernel.org, huaqian.li@siemens.com, jan.kiszka@siemens.com, kristo@kernel.org, krzk+dt@kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, nm@ti.com, robh@kernel.org, ssantosh@kernel.org, vigneshr@ti.com, Krzysztof Kozlowski Subject: [PATCH v9 (RESEND) 2/7] dt-bindings: PCI: ti,am65: Extend for use with PVU Date: Wed, 16 Jul 2025 13:39:45 +0800 Message-Id: <20250716053950.199079-3-huaqian.li@siemens.com> In-Reply-To: <20250716053950.199079-1-huaqian.li@siemens.com> References: <20250716053950.199079-1-huaqian.li@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-959203:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka Reviewed-by: Krzysztof Kozlowski Signed-off-by: Li Hua Qian --- .../bindings/pci/ti,am65-pci-host.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/= Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..98f6c7f1b1a6 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,14 +20,18 @@ properties: - ti,keystone-pcie =20 reg: - maxItems: 4 + minItems: 4 + maxItems: 6 =20 reg-names: + minItems: 4 items: - const: app - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp =20 interrupts: maxItems: 1 @@ -69,6 +73,15 @@ properties: items: pattern: '^pcie-phy[0-1]$' =20 + memory-region: + maxItems: 1 + description: | + phandle to a restricted DMA pool to be used for all devices behind + this controller. The regions should be defined according to + reserved-memory/shared-dma-pool.yaml. + Note that enforcement via the PVU will only be available to + ti,am654-pcie-rc devices. + required: - compatible - reg @@ -89,6 +102,13 @@ then: - power-domains - msi-map - num-viewport +else: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 =20 unevaluatedProperties: false =20 @@ -104,8 +124,10 @@ examples: reg =3D <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names =3D "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names =3D "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp= "; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.34.1