From nobody Tue Oct 7 02:15:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EB3B2F3659; Wed, 16 Jul 2025 10:16:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752660989; cv=none; b=YpqtUMlNQrQwKk9DnEnkejRenfIY0S15IDZpuUC1fzmQG5JJdLPSSgkxCZPDYWG6brCYQwlNkFH6e14PXWJMoQp5QfHNE2fSpjiYL5HMJFwenVWRF6MAH2d4Nk698G0ogckiqf0XzPXeb3mV5pPvNn2hESJO/uvTpIgoQ9KRVT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752660989; c=relaxed/simple; bh=35Mo+w8oB0B/3w9W8xrfBo14YDoWpf2e6pF4USTJjps=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lBfHAX1LEmYajz5loLzjNoU4u/CdQx9tg8bOH6a2oLqG8xlqoBEOFE4oI9/ynAjBMEF28Vc2XevkztyDdNBpDt62eKyag86Sn//JCAoG/RjqPpvq2ztMVZ5Eskh0J4IleW7pLIvpmvO+XkCkTbGhhOqdmaECQT6TYAlKGjObxyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ULFGQzyG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ULFGQzyG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D1CDC4CEF1; Wed, 16 Jul 2025 10:16:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752660988; bh=35Mo+w8oB0B/3w9W8xrfBo14YDoWpf2e6pF4USTJjps=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ULFGQzyGo7T4AhJ8KlSUlDWbGUaKPHjq4gV+664M2rC7gP27HLbYbIfEJyjrRFwLp KA3KWq5SddSKh2lFPc2wPbrYGqZIcSFoxF4rZ7/+olbYeb02Hb1Jv9XXn0CdH6nTfX /q/pAjkrw86ud+ZBOSp+m938+euYTWGqhpyMzghLmQkMxgFh1J1jIYRq6f1Wg6htlU fNTskg5gll359TKI0dliVGoP6nf5AEW0LFzzFiUHC+jzlgdXdbGv+10OZq8a2kUKau fZrpnuy6o2PrDBS9Y0T2dfmIBCqwWyA8L8pw52xe4EoUCY5LQTpXu0HEz8iwttA2UA wMojtv94j5bUA== From: Konrad Dybcio Date: Wed, 16 Jul 2025 12:16:07 +0200 Subject: [PATCH v2 1/4] arm64: dts: qcom: Remove sdm845-cheza boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-topic-goodnight_cheza-v2-1-6fa8d3261813@oss.qualcomm.com> References: <20250716-topic-goodnight_cheza-v2-0-6fa8d3261813@oss.qualcomm.com> In-Reply-To: <20250716-topic-goodnight_cheza-v2-0-6fa8d3261813@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752660979; l=48259; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=GwP9fmo19qXnBXYghqgonE+MT4ATcwolOxe96iJdnS4=; b=hunX8h4mk/5pVpmGER6zILY+42YMrPc2nFxbN0U4CJq8pFUjjHIf4ZeQVAFez7L9/eTTFUcJ+ /fdgE/3xe9/BIPjpk4fZlI5b/dt5sleGMZN4xkC4p5pVhinODztEtY+ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Cheza was a prototype board, used mainly by the ChromeOS folks, whose former efforts on making linux-arm-msm better we greatly appreciate. There are close to zero known-working devices at this point in time (see the link below) and it was never productized. Remove it to ease maintenance burden. Link: https://lore.kernel.org/linux-arm-msm/5567e441-055d-443a-b117-ec16b53= dc059@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio Reviewed-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/Makefile | 3 - arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts | 238 ----- arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts | 238 ----- arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts | 174 ---- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 1330 ----------------------= ---- 5 files changed, 1983 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4bfa926b6a0850c3c459bcba28129c559d50a7cf..67546d46dfacd1517c5bf67710a= 40cc40048b3cd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -231,9 +231,6 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm670-google-sargo.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-cheza-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-cheza-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c.dtb =20 sdm845-db845c-navigation-mezzanine-dtbs :=3D sdm845-db845c.dtb sdm845-db84= 5c-navigation-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts b/arch/arm64/boot= /dts/qcom/sdm845-cheza-r1.dts deleted file mode 100644 index bd7c25bb8d35b191aac2997b4e4c9e637384aa79..000000000000000000000000000= 0000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model =3D "Google Cheza (rev1)"; - compatible =3D "google,cheza-rev1", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt =3D <3500000>; - regulator-max-microvolt =3D <3500000>; - - vin-supply =3D <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt =3D <3500000>; - regulator-max-microvolt =3D <3500000>; - - vin-supply =3D <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmwa= re - * that limits them to 3.0, and trying to run at 3.3V with that old firmwa= re - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt =3D <3008000>; - regulator-max-microvolt =3D <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt =3D <3008000>; - regulator-max-microvolt =3D <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt =3D <3500000>; - regulator-max-microvolt =3D <3500000>; - vin-supply =3D <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names =3D "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "", - "PEN_RST_L", - "PEN_IRQ_L", - "", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts b/arch/arm64/boot= /dts/qcom/sdm845-cheza-r2.dts deleted file mode 100644 index 2b7230594ecbc18b3bb37b929fa91ff4a888bf84..000000000000000000000000000= 0000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model =3D "Google Cheza (rev2)"; - compatible =3D "google,cheza-rev2", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt =3D <3500000>; - regulator-max-microvolt =3D <3500000>; - - vin-supply =3D <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt =3D <3500000>; - regulator-max-microvolt =3D <3500000>; - - vin-supply =3D <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmwa= re - * that limits them to 3.0, and trying to run at 3.3V with that old firmwa= re - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt =3D <3008000>; - regulator-max-microvolt =3D <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt =3D <3008000>; - regulator-max-microvolt =3D <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt =3D <3500000>; - regulator-max-microvolt =3D <3500000>; - vin-supply =3D <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names =3D "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts b/arch/arm64/boot= /dts/qcom/sdm845-cheza-r3.dts deleted file mode 100644 index 1ba67be08f81ade184bc49ca3c1dde743c22c8cb..000000000000000000000000000= 0000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model =3D "Google Cheza (rev3+)"; - compatible =3D "google,cheza", "qcom,sdm845"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names =3D "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID0", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID2", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID1", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID0", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID1", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - /* - * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics - * call it BIOS_FLASH_WP_R_L. - */ - "AP_FLASH_WP_L", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID0", - "AP_RAM_ID1", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi deleted file mode 100644 index b7e514f81f92810b39d128483d10d29878aad431..000000000000000000000000000= 0000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ /dev/null @@ -1,1330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza device tree source (common between revisions) - * - * Copyright 2018 Google LLC. - */ - -#include -#include -#include "sdm845.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm8005.dtsi" -#include "pm8998.dtsi" - -/ { - aliases { - bluetooth0 =3D &bluetooth; - serial1 =3D &uart6; - serial0 =3D &uart9; - wifi0 =3D &wifi; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - backlight: backlight { - compatible =3D "pwm-backlight"; - pwms =3D <&cros_ec_pwm 0>; - enable-gpios =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; - power-supply =3D <&ppvar_sys>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ap_edp_bklten>; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "src_vph_pwr"; - - /* EC turns on with switchcap_on_l; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply =3D <&ppvar_sys>; - }; - - pp5000_a: pp5000-a-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "pp5000_a"; - - /* EC turns on with en_pp5000_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - - vin-supply =3D <&ppvar_sys>; - }; - - src_vreg_bob: src-vreg-bob-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "src_vreg_bob"; - - /* EC turns on with vbob_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt =3D <3600000>; - regulator-max-microvolt =3D <3600000>; - - vin-supply =3D <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "pp3300_dx_edp"; - - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 43 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&en_pp3300_dx_edp>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - src_pp1800_s4a: pm8998-smps4 { - compatible =3D "regulator-fixed"; - regulator-name =3D "src_pp1800_s4a"; - - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply =3D <&src_vph_pwr>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio-keys { - compatible =3D "gpio-keys"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pen_eject_odl>; - - switch-pen-insert { - label =3D "Pen Insert"; - /* Insert =3D low, eject =3D high */ - gpios =3D <&tlmm 119 GPIO_ACTIVE_LOW>; - linux,code =3D ; - linux,input-type =3D ; - wakeup-source; - }; - }; - - panel: panel { - compatible =3D "innolux,p120zdg-bf1"; - power-supply =3D <&pp3300_dx_edp>; - backlight =3D <&backlight>; - no-hpd; - - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint =3D <&sn65dsi86_out>; - }; - }; - }; -}; - -&cpufreq_hw { - /delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */ -}; - -&psci { - /delete-node/ power-domain-cpu0; - /delete-node/ power-domain-cpu1; - /delete-node/ power-domain-cpu2; - /delete-node/ power-domain-cpu3; - /delete-node/ power-domain-cpu4; - /delete-node/ power-domain-cpu5; - /delete-node/ power-domain-cpu6; - /delete-node/ power-domain-cpu7; - /delete-node/ power-domain-cluster; -}; - -&cpus { - /delete-node/ domain-idle-states; -}; - -&cpu_idle_states { - little_cpu_sleep_0: cpu-sleep-0-0 { - compatible =3D "arm,idle-state"; - idle-state-name =3D "little-power-down"; - arm,psci-suspend-param =3D <0x40000003>; - entry-latency-us =3D <350>; - exit-latency-us =3D <461>; - min-residency-us =3D <1890>; - local-timer-stop; - }; - - little_cpu_sleep_1: cpu-sleep-0-1 { - compatible =3D "arm,idle-state"; - idle-state-name =3D "little-rail-power-down"; - arm,psci-suspend-param =3D <0x40000004>; - entry-latency-us =3D <360>; - exit-latency-us =3D <531>; - min-residency-us =3D <3934>; - local-timer-stop; - }; - - big_cpu_sleep_0: cpu-sleep-1-0 { - compatible =3D "arm,idle-state"; - idle-state-name =3D "big-power-down"; - arm,psci-suspend-param =3D <0x40000003>; - entry-latency-us =3D <264>; - exit-latency-us =3D <621>; - min-residency-us =3D <952>; - local-timer-stop; - }; - - big_cpu_sleep_1: cpu-sleep-1-1 { - compatible =3D "arm,idle-state"; - idle-state-name =3D "big-rail-power-down"; - arm,psci-suspend-param =3D <0x40000004>; - entry-latency-us =3D <702>; - exit-latency-us =3D <1061>; - min-residency-us =3D <4488>; - local-timer-stop; - }; - - cluster_sleep_0: cluster-sleep-0 { - compatible =3D "arm,idle-state"; - idle-state-name =3D "cluster-power-down"; - arm,psci-suspend-param =3D <0x400000F4>; - entry-latency-us =3D <3263>; - exit-latency-us =3D <6562>; - min-residency-us =3D <9987>; - local-timer-stop; - }; -}; - -&cpu0 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu1 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu2 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu3 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu4 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu5 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu6 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu7 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states =3D <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&lmh_cluster0 { - status =3D "disabled"; -}; - -&lmh_cluster1 { - status =3D "disabled"; -}; - -/* - * Reserved memory changes - * - * Putting this all together (out of order with the rest of the file) to k= eep - * all modifications to the memory map (from sdm845.dtsi) in one place. - */ - -/* - * Our mpss_region is 8MB bigger than the default one and that conflicts - * with venus_mem and cdsp_mem. - * - * For venus_mem we'll delete and re-create at a different address. - * - * cdsp_mem isn't used on cheza right now so we won't bother re-creating i= t; but - * that also means we need to delete cdsp_pas. - */ -/delete-node/ &venus_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &cdsp_pas; -/delete-node/ &gpu_mem; - -/* Increase the size from 120 MB to 128 MB */ -&mpss_region { - reg =3D <0 0x8e000000 0 0x8000000>; -}; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg =3D <0 0x88f00000 0 0x800000>; -}; - -/ { - reserved-memory { - venus_mem: memory@96000000 { - reg =3D <0 0x96000000 0 0x500000>; - no-map; - }; - }; -}; - -&qspi { - status =3D "okay"; - pinctrl-names =3D "default", "sleep"; - pinctrl-0 =3D <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; - pinctrl-1 =3D <&qspi_sleep>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - - /* - * In theory chip supports up to 104 MHz and controller up - * to 80 MHz, but above 25 MHz wasn't reliable so we'll use - * that for now. b:117440651 - */ - spi-max-frequency =3D <25000000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - }; -}; - - -&apps_rsc { - /delete-property/ power-domains; - - regulators-0 { - compatible =3D "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id =3D "a"; - - vdd-s1-supply =3D <&src_vph_pwr>; - vdd-s2-supply =3D <&src_vph_pwr>; - vdd-s3-supply =3D <&src_vph_pwr>; - vdd-s4-supply =3D <&src_vph_pwr>; - vdd-s5-supply =3D <&src_vph_pwr>; - vdd-s6-supply =3D <&src_vph_pwr>; - vdd-s7-supply =3D <&src_vph_pwr>; - vdd-s8-supply =3D <&src_vph_pwr>; - vdd-s9-supply =3D <&src_vph_pwr>; - vdd-s10-supply =3D <&src_vph_pwr>; - vdd-s11-supply =3D <&src_vph_pwr>; - vdd-s12-supply =3D <&src_vph_pwr>; - vdd-s13-supply =3D <&src_vph_pwr>; - vdd-l1-l27-supply =3D <&src_pp1025_s7a>; - vdd-l2-l8-l17-supply =3D <&src_pp1350_s3a>; - vdd-l3-l11-supply =3D <&src_pp1025_s7a>; - vdd-l4-l5-supply =3D <&src_pp1025_s7a>; - vdd-l6-supply =3D <&src_vph_pwr>; - vdd-l7-l12-l14-l15-supply =3D <&src_pp2040_s5a>; - vdd-l9-supply =3D <&src_pp2040_s5a>; - vdd-l10-l23-l25-supply =3D <&src_vreg_bob>; - vdd-l13-l19-l21-supply =3D <&src_vreg_bob>; - vdd-l16-l28-supply =3D <&src_vreg_bob>; - vdd-l18-l22-supply =3D <&src_vreg_bob>; - vdd-l20-l24-supply =3D <&src_vreg_bob>; - vdd-l26-supply =3D <&src_pp1350_s3a>; - vin-lvs-1-2-supply =3D <&src_pp1800_s4a>; - - src_pp1125_s2a: smps2 { - regulator-min-microvolt =3D <1100000>; - regulator-max-microvolt =3D <1100000>; - }; - - src_pp1350_s3a: smps3 { - regulator-min-microvolt =3D <1352000>; - regulator-max-microvolt =3D <1352000>; - }; - - src_pp2040_s5a: smps5 { - regulator-min-microvolt =3D <1904000>; - regulator-max-microvolt =3D <2040000>; - }; - - src_pp1025_s7a: smps7 { - regulator-min-microvolt =3D <900000>; - regulator-max-microvolt =3D <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - src_pp875_l1a: ldo1 { - regulator-min-microvolt =3D <880000>; - regulator-max-microvolt =3D <880000>; - regulator-initial-mode =3D ; - }; - - vddpx_10: - src_pp1200_l2a: ldo2 { - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - - /* TODO: why??? */ - regulator-always-on; - }; - - pp1000_l3a_sdr845: ldo3 { - regulator-min-microvolt =3D <1000000>; - regulator-max-microvolt =3D <1000000>; - regulator-initial-mode =3D ; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - src_pp800_l5a: ldo5 { - regulator-min-microvolt =3D <800000>; - regulator-max-microvolt =3D <800000>; - regulator-initial-mode =3D ; - }; - - vddpx_13: - src_pp1800_l6a: ldo6 { - regulator-min-microvolt =3D <1856000>; - regulator-max-microvolt =3D <1856000>; - regulator-initial-mode =3D ; - }; - - pp1800_l7a_wcn3990: ldo7 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - src_pp1200_l8a: ldo8 { - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1248000>; - regulator-initial-mode =3D ; - }; - - pp1800_dx_pen: - src_pp1800_l9a: ldo9 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - src_pp1800_l10a: ldo10 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - pp1000_l11a_sdr845: ldo11 { - regulator-min-microvolt =3D <1000000>; - regulator-max-microvolt =3D <1048000>; - regulator-initial-mode =3D ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - src_pp1800_l12a: ldo12 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vddpx_2: - src_pp2950_l13a: ldo13 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <2960000>; - regulator-initial-mode =3D ; - }; - - src_pp1800_l14a: ldo14 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - src_pp1800_l15a: ldo15 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - pp2700_l16a: ldo16 { - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2704000>; - regulator-initial-mode =3D ; - }; - - src_pp1300_l17a: ldo17 { - regulator-min-microvolt =3D <1304000>; - regulator-max-microvolt =3D <1304000>; - regulator-initial-mode =3D ; - }; - - pp2700_l18a: ldo18 { - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2960000>; - regulator-initial-mode =3D ; - }; - - /* - * NOTE: this rail should have been called - * src_pp3300_l19a in the schematic - */ - src_pp3000_l19a: ldo19 { - regulator-min-microvolt =3D <3304000>; - regulator-max-microvolt =3D <3304000>; - - regulator-initial-mode =3D ; - }; - - src_pp2950_l20a: ldo20 { - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2960000>; - regulator-initial-mode =3D ; - }; - - src_pp2950_l21a: ldo21 { - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2960000>; - regulator-initial-mode =3D ; - }; - - pp3300_hub: - src_pp3300_l22a: ldo22 { - regulator-min-microvolt =3D <3304000>; - regulator-max-microvolt =3D <3304000>; - regulator-initial-mode =3D ; - /* - * HACK: Should add a usb hub node and driver - * to turn this on and off at suspend/resume time - */ - regulator-boot-on; - regulator-always-on; - }; - - pp3300_l23a_ch1_wcn3990: ldo23 { - regulator-min-microvolt =3D <3000000>; - regulator-max-microvolt =3D <3312000>; - regulator-initial-mode =3D ; - }; - - vdda_qusb_hs0_3p1: - src_pp3075_l24a: ldo24 { - regulator-min-microvolt =3D <3088000>; - regulator-max-microvolt =3D <3088000>; - regulator-initial-mode =3D ; - }; - - pp3300_l25a_ch0_wcn3990: ldo25 { - regulator-min-microvolt =3D <3304000>; - regulator-max-microvolt =3D <3304000>; - regulator-initial-mode =3D ; - }; - - pp1200_hub: - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - src_pp1200_l26a: ldo26 { - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - pp3300_dx_pen: - src_pp3300_l28a: ldo28 { - regulator-min-microvolt =3D <3304000>; - regulator-max-microvolt =3D <3304000>; - regulator-initial-mode =3D ; - }; - - src_pp1800_lvs1: lvs1 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - }; - - src_pp1800_lvs2: lvs2 { - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - }; - }; - - regulators-1 { - compatible =3D "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id =3D "c"; - - vdd-s1-supply =3D <&src_vph_pwr>; - vdd-s2-supply =3D <&src_vph_pwr>; - vdd-s3-supply =3D <&src_vph_pwr>; - vdd-s4-supply =3D <&src_vph_pwr>; - - src_pp600_s3c: smps3 { - regulator-min-microvolt =3D <600000>; - regulator-max-microvolt =3D <600000>; - }; - }; -}; - -edp_brij_i2c: &i2c3 { - status =3D "okay"; - clock-frequency =3D <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible =3D "ti,sn65dsi86"; - reg =3D <0x2d>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&edp_brij_en &edp_brij_irq>; - - interrupt-parent =3D <&tlmm>; - interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios =3D <&tlmm 102 GPIO_ACTIVE_HIGH>; - - vpll-supply =3D <&src_pp1800_s4a>; - vccio-supply =3D <&src_pp1800_s4a>; - vcca-supply =3D <&src_pp1200_l2a>; - vcc-supply =3D <&src_pp1200_l2a>; - - clocks =3D <&rpmhcc RPMH_LN_BB_CLK2>; - clock-names =3D "refclk"; - - no-hpd; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - sn65dsi86_in: endpoint { - remote-endpoint =3D <&mdss_dsi0_out>; - }; - }; - - port@1 { - reg =3D <1>; - sn65dsi86_out: endpoint { - remote-endpoint =3D <&panel_in_edp>; - }; - }; - }; - }; -}; - -ap_pen_1v8: &i2c11 { - status =3D "okay"; - clock-frequency =3D <400000>; - - digitizer@9 { - compatible =3D "wacom,w9013", "hid-over-i2c"; - reg =3D <0x9>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; - - vdd-supply =3D <&pp3300_dx_pen>; - vddl-supply =3D <&pp1800_dx_pen>; - post-power-on-delay-ms =3D <100>; - - interrupt-parent =3D <&tlmm>; - interrupts =3D <24 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr =3D <0x1>; - }; -}; - -amp_i2c: &i2c12 { - status =3D "okay"; - clock-frequency =3D <400000>; -}; - -ap_ts_i2c: &i2c14 { - status =3D "okay"; - clock-frequency =3D <400000>; - - touchscreen@10 { - compatible =3D "elan,ekth3500"; - reg =3D <0x10>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts_int_l &ts_reset_l>; - - interrupt-parent =3D <&tlmm>; - interrupts =3D <125 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply =3D <&src_pp3300_l28a>; - - reset-gpios =3D <&tlmm 118 GPIO_ACTIVE_LOW>; - }; -}; - -&gpu { - status =3D "okay"; -}; - -&ipa { - qcom,gsi-loader =3D "modem"; - status =3D "okay"; -}; - -&lpasscc { - status =3D "okay"; -}; - -&mdss { - status =3D "okay"; -}; - -&mdss_dsi0 { - status =3D "okay"; - vdda-supply =3D <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint =3D <&sn65dsi86_in>; - data-lanes =3D <0 1 2 3>; - }; - }; - }; -}; - -&mdss_dsi0_phy { - status =3D "okay"; - vdds-supply =3D <&vdda_mipi_dsi0_pll>; -}; - -/* - * Cheza fw does not properly program the GPU aperture to allow the - * GPU to update the SMMU pagetables for context switches. Work - * around this by dropping the "qcom,adreno-smmu" compat string. - */ -&adreno_smmu { - compatible =3D "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; -}; - -&mss_pil { - status =3D "okay"; - - iommus =3D <&apps_smmu 0x781 0x0>, - <&apps_smmu 0x724 0x3>; -}; - -&pm8998_pwrkey { - status =3D "disabled"; -}; - -&qupv3_id_0 { - status =3D "okay"; - iommus =3D <&apps_smmu 0x0 0x3>; -}; - -&qupv3_id_1 { - status =3D "okay"; - iommus =3D <&apps_smmu 0x6c0 0x3>; -}; - -&sdhc_2 { - status =3D "okay"; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; - - vmmc-supply =3D <&src_pp2950_l21a>; - vqmmc-supply =3D <&vddpx_2>; - - cd-gpios =3D <&tlmm 44 GPIO_ACTIVE_LOW>; -}; - -&spi0 { - status =3D "okay"; -}; - -&spi5 { - status =3D "okay"; - - tpm@0 { - compatible =3D "google,cr50"; - reg =3D <0>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&h1_ap_int_odl>; - spi-max-frequency =3D <800000>; - interrupt-parent =3D <&tlmm>; - interrupts =3D <129 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&spi10 { - status =3D "okay"; - - cros_ec: ec@0 { - compatible =3D "google,cros-ec-spi"; - reg =3D <0>; - interrupt-parent =3D <&tlmm>; - interrupts =3D <122 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ec_ap_int_l>; - spi-max-frequency =3D <3000000>; - wakeup-source; - - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; - #pwm-cells =3D <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible =3D "google,cros-ec-i2c-tunnel"; - google,remote-bus =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -#include -#include - -&uart6 { - status =3D "okay"; - - pinctrl-0 =3D <&qup_uart6_4pin>; - - bluetooth: bluetooth { - compatible =3D "qcom,wcn3990-bt"; - vddio-supply =3D <&src_pp1800_s4a>; - vddxo-supply =3D <&pp1800_l7a_wcn3990>; - vddrf-supply =3D <&src_pp1300_l17a>; - vddch0-supply =3D <&pp3300_l25a_ch0_wcn3990>; - max-speed =3D <3200000>; - }; -}; - -&uart9 { - status =3D "okay"; -}; - -&ufs_mem_hc { - status =3D "okay"; - - reset-gpios =3D <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply =3D <&src_pp2950_l20a>; - vcc-max-microamp =3D <600000>; -}; - -&ufs_mem_phy { - status =3D "okay"; - - vdda-phy-supply =3D <&vdda_ufs1_core>; - vdda-pll-supply =3D <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status =3D "okay"; - - /* We'll use this as USB 2.0 only */ - qcom,select-utmi-as-pipe-clk; -}; - -&usb_1_dwc3 { - /* - * The hardware design intends this port to be hooked up in peripheral - * mode, so we'll hardcode it here. Some details: - * - SDM845 expects only a single Type C connector so it has only one - * native Type C port but cheza has two Type C connectors. - * - The only source of DP is the single native Type C port. - * - On cheza we want to be able to hook DP up to _either_ of the - * two Type C connectors and want to be able to achieve 4 lanes of DP. - * - When you configure a Type C port for 4 lanes of DP you lose USB3. - * - In order to make everything work, the native Type C port is always - * configured as 4-lanes DP so it's always available. - * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then - * sent to the two Type C connectors. - * - The extra USB2 lines from the native Type C port are always - * setup as "peripheral" so that we can mux them over to one connector - * or the other if someone needs the connector configured as a gadget - * (but they only get USB2 speeds). - * - * All the hardware muxes would allow us to hook things up in different - * ways to some potential benefit for static configurations (you could - * achieve extra USB2 bandwidth by using two different ports for the - * two connectors or possibly even get USB3 peripheral mode), but in - * each case you end up forcing to disconnect/reconnect an in-use - * USB session in some cases depending on what you hotplug into the - * other connector. Thus hardcoding this as peripheral makes sense. - */ - dr_mode =3D "peripheral"; - - /* - * We always need the high speed pins as 4-lanes DP in case someone - * hotplugs a DP peripheral. Thus limit this port to a max of high - * speed. - */ - maximum-speed =3D "high-speed"; - - /* - * We don't need the usb3-phy since we run in highspeed mode always, so - * re-define these properties removing the superspeed USB PHY reference. - */ - phys =3D <&usb_1_hsphy>; - phy-names =3D "usb2-phy"; -}; - -&usb_1_hsphy { - status =3D "okay"; - - vdd-supply =3D <&vdda_usb1_ss_core>; - vdda-pll-supply =3D <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply =3D <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value =3D <8>; - qcom,hstx-trim-value =3D ; - qcom,preemphasis-level =3D ; - qcom,preemphasis-width =3D ; -}; - -&usb_2 { - status =3D "okay"; -}; - -&usb_2_dwc3 { - /* We have this hooked up to a hub and we always use in host mode */ - dr_mode =3D "host"; -}; - -&usb_2_hsphy { - status =3D "okay"; - - vdd-supply =3D <&vdda_usb2_ss_core>; - vdda-pll-supply =3D <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply =3D <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value =3D <8>; - qcom,hstx-trim-value =3D ; -}; - -&usb_2_qmpphy { - status =3D "okay"; - - vdda-phy-supply =3D <&vdda_usb2_ss_1p2>; - vdda-pll-supply =3D <&vdda_usb2_ss_core>; -}; - -&wifi { - status =3D "okay"; - - vdd-0.8-cx-mx-supply =3D <&src_pp800_l5a >; - vdd-1.8-xo-supply =3D <&pp1800_l7a_wcn3990>; - vdd-1.3-rfa-supply =3D <&src_pp1300_l17a>; - vdd-3.3-ch0-supply =3D <&pp3300_l25a_ch0_wcn3990>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qspi_cs0 { - bias-disable; /* External pullup */ -}; - -&qspi_clk { - bias-disable; /* Rely on Cr50 internal pulldown */ -}; - -&qspi_data0 { - bias-disable; /* Rely on Cr50 internal pulldown */ -}; - -&qspi_data1 { - bias-pull-down; -}; - -&qup_i2c3_default { - drive-strength =3D <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c11_default { - drive-strength =3D <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c12_default { - drive-strength =3D <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c14_default { - drive-strength =3D <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_spi0_default { - drive-strength =3D <2>; - bias-disable; -}; - -&qup_spi5_default { - drive-strength =3D <2>; - bias-disable; -}; - -&qup_spi10_default { - drive-strength =3D <2>; - bias-disable; -}; - -&qup_uart9_rx { - drive-strength =3D <2>; - bias-pull-up; -}; - -&qup_uart9_tx { - drive-strength =3D <2>; - bias-disable; -}; - -/* PINCTRL - board-specific pinctrl */ -&pm8005_gpios { - gpio-line-names =3D "", - "", - "SLB", - ""; -}; - -&pm8998_adc { - channel@4d { - reg =3D ; - label =3D "sdm_temp"; - }; - - channel@4e { - reg =3D ; - label =3D "quiet_temp"; - }; - - channel@4f { - reg =3D ; - label =3D "lte_temp_1"; - }; - - channel@50 { - reg =3D ; - label =3D "lte_temp_2"; - }; - - channel@51 { - reg =3D ; - label =3D "charger_temp"; - }; -}; - -&pm8998_gpios { - gpio-line-names =3D "", - "", - "SW_CTRL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "CFG_OPT1", - "WCSS_PWR_REQ", - "", - "CFG_OPT2", - "SLB"; -}; - -&tlmm { - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names =3D "default", "sleep"; - pinctrl-0 =3D <&bios_flash_wp_r_l>, - <&ap_suspend_l_deassert>; - - pinctrl-1 =3D <&bios_flash_wp_r_l>, - <&ap_suspend_l_assert>; - - /* - * Hogs prevent usermode from changing the value. A GPIO can be both - * here and in the pinctrl section. - */ - ap-suspend-l-hog { - gpio-hog; - gpios =3D <126 GPIO_ACTIVE_LOW>; - output-low; - }; - - ap_edp_bklten: ap-edp-bklten-state { - pins =3D "gpio37"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - bios_flash_wp_r_l: bios-flash-wp-r-l-state { - pins =3D "gpio128"; - function =3D "gpio"; - bias-disable; - }; - - ec_ap_int_l: ec-ap-int-l-state { - pins =3D "gpio122"; - function =3D "gpio"; - bias-pull-up; - }; - - edp_brij_en: edp-brij-en-state { - pins =3D "gpio102"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - edp_brij_irq: edp-brij-irq-state { - pins =3D "gpio10"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-down; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp-state { - pins =3D "gpio43"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - h1_ap_int_odl: h1-ap-int-odl-state { - pins =3D "gpio129"; - function =3D "gpio"; - bias-pull-up; - }; - - pen_eject_odl: pen-eject-odl-state { - pins =3D "gpio119"; - function =3D "gpio"; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l-state { - pins =3D "gpio24"; - function =3D "gpio"; - - /* Has external pullup */ - bias-disable; - }; - - pen_pdct_l: pen-pdct-l-state { - pins =3D "gpio63"; - function =3D "gpio"; - - /* Has external pullup */ - bias-disable; - }; - - pen_rst_l: pen-rst-l-state { - pins =3D "gpio23"; - function =3D "gpio"; - bias-disable; - drive-strength =3D <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; - - qspi_sleep: qspi-sleep-state { - pins =3D "gpio90", "gpio91", "gpio92", "gpio95"; - - /* - * When we're not actively transferring we want pins as GPIOs - * with output disabled so that the quad SPI IP block stops - * driving them. We rely on the normal pulls configured in - * the active state and don't redefine them here. Also note - * that we don't need the reverse (output-enable) in the - * normal mode since the "output-enable" only matters for - * GPIO function. - */ - function =3D "gpio"; - output-disable; - }; - - sdc2_clk: sdc2-clk-state { - pins =3D "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength =3D <16>; - }; - - sdc2_cmd: sdc2-cmd-state { - pins =3D "sdc2_cmd"; - bias-pull-up; - drive-strength =3D <16>; - }; - - sdc2_data: sdc2-data-state { - pins =3D "sdc2_data"; - bias-pull-up; - drive-strength =3D <16>; - }; - - sd_cd_odl: sd-cd-odl-state { - pins =3D "gpio44"; - function =3D "gpio"; - bias-pull-up; - }; - - ts_int_l: ts-int-l-state { - pins =3D "gpio125"; - function =3D "gpio"; - bias-pull-up; - }; - - ts_reset_l: ts-reset-l-state { - pins =3D "gpio118"; - function =3D "gpio"; - bias-disable; - drive-strength =3D <2>; - }; - - ap_suspend_l_assert: ap-suspend-l-assert-state { - pins =3D "gpio126"; - function =3D "gpio"; - bias-disable; - drive-strength =3D <2>; - output-low; - }; - - ap_suspend_l_deassert: ap-suspend-l-deassert-state { - pins =3D "gpio126"; - function =3D "gpio"; - bias-disable; - drive-strength =3D <2>; - output-high; - }; -}; - -&venus { - status =3D "okay"; - - video-firmware { - iommus =3D <&apps_smmu 0x10b2 0x0>; - }; -}; --=20 2.50.1