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Wed, 16 Jul 2025 11:25:38 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 16 Jul 2025 19:25:10 +0800 Subject: [PATCH v3 1/9] dt-bindings: mips: loongson: Add LS1B-DEMO and CQ-T300B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-1-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=1139; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=BeFER/OTjUaBJU4oGgkzvKA9dNM7aAK4NJf5Ys8zrbg=; b=6NcprzyhHtqouLOk+dmcRREh3edSDZAcjjBl2aMyHDjb9/mrxGkh8j+6ktAKFqM1XO8mV5tnh 4pXNBMzYFGsBf/Wq3+LlQy+c7NVgPC1kxfbjklAk69d3hGjDc51WCPM X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Document two Loongson-1 boards: - loongson,ls1b-demo: a board based on Loongson-1B - loongson,cq-t300b: a board based on Loongson-1C Acked-by: Krzysztof Kozlowski Signed-off-by: Keguang Zhang --- Documentation/devicetree/bindings/mips/loongson/devices.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b= /Documentation/devicetree/bindings/mips/loongson/devices.yaml index 099e40e1482d..ca66bc49c2d6 100644 --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -40,6 +40,7 @@ properties: - description: LS1B based boards items: - enum: + - loongson,ls1b-demo - loongson,lsgz-1b-dev - const: loongson,ls1b =20 @@ -47,6 +48,7 @@ properties: items: - enum: - loongmasses,smartloong-1c + - loongson,cq-t300b - const: loongson,ls1c =20 additionalProperties: true --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56BED263C90; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-2-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=12519; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=5MqJxPmRjh3ik9Nyz+/0iY/ygphCzapZIygNanhDkRI=; b=Uz5R7T15aiqnx5jSGYnmTV4t/uHhjUQqOSghKJQvvWdF7sKBrDEHcJTLB7czzXwFV3gNofLZa dcWXPfl7vKOAWs1XcWVFx8l8lj7ROOcAQizTq+VAt8W4kYnPJLho4Us X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Add a device tree for LS1B-DEMO board, supporting CPU, clock, INTC, UART, Ethernet, GPIO, USB host, RTC, watchdog, DMA, NAND, and AC97. Signed-off-by: Keguang Zhang --- MAINTAINERS | 1 + arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/loongson/Makefile | 2 + arch/mips/boot/dts/loongson/loongson1.dtsi | 136 +++++++++++++++++++ arch/mips/boot/dts/loongson/loongson1b.dtsi | 198 ++++++++++++++++++++++++= ++++ arch/mips/boot/dts/loongson/ls1b-demo.dts | 125 ++++++++++++++++++ 6 files changed, 463 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c3f7fbd0d67a..0089ebca31cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16683,6 +16683,7 @@ M: Keguang Zhang L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml +F: arch/mips/boot/dts/loongson/loongson1* F: arch/mips/include/asm/mach-loongson32/ F: arch/mips/loongson32/ F: drivers/*/*loongson1* diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 7375c6ced82b..6d9dbe945541 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) +=3D img subdir-$(CONFIG_MACH_INGENIC) +=3D ingenic subdir-$(CONFIG_LANTIQ) +=3D lantiq subdir-$(CONFIG_MACH_LOONGSON64) +=3D loongson +subdir-$(CONFIG_MACH_LOONGSON32) +=3D loongson subdir-$(CONFIG_SOC_VCOREIII) +=3D mscc subdir-$(CONFIG_MIPS_MALTA) +=3D mti subdir-$(CONFIG_LEGACY_BOARD_SEAD3) +=3D mti diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loon= gson/Makefile index 5e3ab984d70f..88b87c94c545 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -5,3 +5,5 @@ dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64c_4core_rs780e= .dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64c_8core_rs780e.dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64g_4core_ls7a.dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64v_4core_virtio.dtb + +dtb-$(CONFIG_MACH_LOONGSON32) +=3D ls1b-demo.dtb diff --git a/arch/mips/boot/dts/loongson/loongson1.dtsi b/arch/mips/boot/dt= s/loongson/loongson1.dtsi new file mode 100644 index 000000000000..5ba5a5d131ba --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson1.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; + +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + xtal: clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "xtal"; + #clock-cells =3D <0>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + reg =3D <0>; + device_type =3D "cpu"; + clocks =3D <&clkc LS1X_CLKID_CPU>; + #clock-cells =3D <1>; + }; + }; + + cpu_intc: interrupt-controller { + compatible =3D "mti,cpu-interrupt-controller"; + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + }; + + soc: bus@1fd00000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x1fd00000 0x130000>; + + intc0: interrupt-controller@1040 { + compatible =3D "loongson,ls1x-intc"; + reg =3D <0x1040 0x18>; + interrupt-controller; + interrupt-parent =3D <&cpu_intc>; + interrupts =3D <2>; + #interrupt-cells =3D <2>; + }; + + intc1: interrupt-controller@1058 { + compatible =3D "loongson,ls1x-intc"; + reg =3D <0x1058 0x18>; + interrupt-controller; + interrupt-parent =3D <&cpu_intc>; + interrupts =3D <3>; + #interrupt-cells =3D <2>; + }; + + intc2: interrupt-controller@1070 { + compatible =3D "loongson,ls1x-intc"; + reg =3D <0x1070 0x18>; + interrupt-controller; + interrupt-parent =3D <&cpu_intc>; + interrupts =3D <4>; + #interrupt-cells =3D <2>; + }; + + intc3: interrupt-controller@1088 { + compatible =3D "loongson,ls1x-intc"; + reg =3D <0x1088 0x18>; + interrupt-controller; + interrupt-parent =3D <&cpu_intc>; + interrupts =3D <5>; + #interrupt-cells =3D <2>; + }; + + gpio0: gpio@10c0 { + compatible =3D "loongson,ls1x-gpio"; + reg =3D <0x10c0 0x4>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio1: gpio@10c4 { + compatible =3D "loongson,ls1x-gpio"; + reg =3D <0x10c4 0x4>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + + apb: bus@1fe40000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x1fe40000 0xc0000>; + + uart0: serial@0 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x8>; + clocks =3D <&clkc LS1X_CLKID_APB>; + interrupt-parent =3D <&intc0>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + uart1: serial@4000 { + compatible =3D "ns16550a"; + reg =3D <0x4000 0x8>; + clocks =3D <&clkc LS1X_CLKID_APB>; + interrupt-parent =3D <&intc0>; + status =3D "disabled"; + }; + + uart2: serial@8000 { + compatible =3D "ns16550a"; + reg =3D <0x8000 0x8>; + clocks =3D <&clkc LS1X_CLKID_APB>; + interrupt-parent =3D <&intc0>; + status =3D "disabled"; + }; + + uart3: serial@c000 { + compatible =3D "ns16550a"; + reg =3D <0xc000 0x8>; + clocks =3D <&clkc LS1X_CLKID_APB>; + interrupt-parent =3D <&intc0>; + status =3D "disabled"; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson1b.dtsi b/arch/mips/boot/d= ts/loongson/loongson1b.dtsi new file mode 100644 index 000000000000..776d272b0f43 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson1b.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; +#include "loongson1.dtsi" + +/ { + cpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-44000000 { + opp-hz =3D /bits/ 64 <44000000>; + }; + opp-47142000 { + opp-hz =3D /bits/ 64 <47142000>; + }; + opp-50769000 { + opp-hz =3D /bits/ 64 <50769000>; + }; + opp-55000000 { + opp-hz =3D /bits/ 64 <55000000>; + }; + opp-60000000 { + opp-hz =3D /bits/ 64 <60000000>; + }; + opp-66000000 { + opp-hz =3D /bits/ 64 <66000000>; + }; + opp-73333000 { + opp-hz =3D /bits/ 64 <73333000>; + }; + opp-82500000 { + opp-hz =3D /bits/ 64 <82500000>; + }; + opp-94285000 { + opp-hz =3D /bits/ 64 <94285000>; + }; + opp-110000000 { + opp-hz =3D /bits/ 64 <110000000>; + }; + opp-132000000 { + opp-hz =3D /bits/ 64 <132000000>; + }; + opp-165000000 { + opp-hz =3D /bits/ 64 <165000000>; + }; + opp-220000000 { + opp-hz =3D /bits/ 64 <220000000>; + }; + }; + + clkc: clock-controller@1fe78030 { + compatible =3D "loongson,ls1b-clk"; + reg =3D <0x1fe78030 0x8>; + clocks =3D <&xtal>; + #clock-cells =3D <1>; + }; +}; + +&soc { + syscon: syscon@420 { + compatible =3D "loongson,ls1b-syscon", "syscon"; + reg =3D <0x420 0x8>; + }; + + dma: dma-controller@1160 { + compatible =3D "loongson,ls1b-apbdma"; + reg =3D <0x1160 0x4>; + interrupt-parent =3D <&intc0>; + interrupts =3D <13 IRQ_TYPE_EDGE_RISING>, + <14 IRQ_TYPE_EDGE_RISING>, + <15 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "ch0", "ch1", "ch2"; + #dma-cells =3D <1>; + }; + + ehci: usb@100000 { + compatible =3D "generic-ehci"; + reg =3D <0x100000 0x100>; + interrupt-parent =3D <&intc1>; + interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + ohci: usb@108000 { + compatible =3D "generic-ohci"; + reg =3D <0x108000 0x100>; + interrupt-parent =3D <&intc1>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + gmac0: ethernet@110000 { + compatible =3D "loongson,ls1b-gmac", "snps,dwmac-3.50a"; + reg =3D <0x110000 0x10000>; + clocks =3D <&clkc LS1X_CLKID_AHB>; + clock-names =3D "stmmaceth"; + interrupt-parent =3D <&intc1>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + loongson,ls1-syscon =3D <&syscon>; + snps,pbl =3D <1>; + status =3D "disabled"; + }; + + gmac1: ethernet@120000 { + compatible =3D "loongson,ls1b-gmac", "snps,dwmac-3.50a"; + reg =3D <0x120000 0x10000>; + clocks =3D <&clkc LS1X_CLKID_AHB>; + clock-names =3D "stmmaceth"; + interrupt-parent =3D <&intc1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + loongson,ls1-syscon =3D <&syscon>; + snps,pbl =3D <1>; + status =3D "disabled"; + }; +}; + +&apb { + clocksource: timer@1c030 { + compatible =3D "loongson,ls1b-pwmtimer"; + reg =3D <0x1c030 0x10>; + clocks =3D <&clkc LS1X_CLKID_APB>; + interrupt-parent =3D <&intc0>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@1c060 { + compatible =3D "loongson,ls1b-wdt"; + reg =3D <0x1c060 0xc>; + clocks =3D <&clkc LS1X_CLKID_APB>; + status =3D "disabled"; + }; + + rtc: rtc@24000 { + compatible =3D "loongson,ls1b-rtc"; + reg =3D <0x24000 0x78>; + interrupt-parent =3D <&intc0>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + ac97: audio-controller@34000 { + compatible =3D "loongson,ls1b-ac97"; + reg =3D <0x34000 0x60>, <0x32420 0x4>, <0x34c4c 0x4>; + reg-names =3D "ac97", "audio-tx", "audio-rx"; + dmas =3D <&dma 1>, <&dma 2>; + dma-names =3D "tx", "rx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + nand: nand-controller@38000 { + compatible =3D "loongson,ls1b-nand-controller"; + reg =3D <0x38000 0x24>, <0x38040 0x4>; + reg-names =3D "nand", "nand-dma"; + dmas =3D <&dma 0>; + dma-names =3D "rxtx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + nand@0 { + reg =3D <0>; + label =3D "ls1x-nand"; + nand-use-soft-ecc-engine; + nand-ecc-algo =3D "hamming"; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&gpio0 { + ngpios =3D <31>; +}; + +&gpio1 { + ngpios =3D <30>; +}; + +&uart1 { + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart2 { + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart3 { + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/mips/boot/dts/loongson/ls1b-demo.dts b/arch/mips/boot/dts= /loongson/ls1b-demo.dts new file mode 100644 index 000000000000..13f8b102e100 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls1b-demo.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; + +#include + +#include "loongson1b.dtsi" + +/ { + compatible =3D "loongson,ls1b-demo", "loongson,ls1b"; + model =3D "LS1B-DEMO Board"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x10000000>; + }; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:38400n8"; + }; + + codec: audio-codec { + compatible =3D "realtek,alc203"; + #sound-dai-cells =3D <0>; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "ls1b-alc203"; + simple-audio-card,format =3D "ac97"; + simple-audio-card,widgets =3D + "Speaker", "Line Out Jack", + "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + simple-audio-card,routing =3D + "Line Out Jack", "TX", + "Headphone Jack", "TX", + "RX", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai =3D <&ac97>; + }; + + simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&xtal { + clock-frequency =3D <33000000>; +}; + +&gmac0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: ethernet-phy@0 { + reg =3D <0x0>; + }; + }; +}; + +&nand { + status =3D "okay"; + + nand@0 { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "kernel"; + reg =3D <0x0 0x1000000>; + }; + + partition@1000000 { + label =3D "rootfs"; + reg =3D <0x1000000 0x7000000>; + }; + }; + }; +}; + +&ac97 { + status =3D "okay"; +}; + +&ehci { + status =3D "okay"; +}; + +&ohci { + status =3D "okay"; +}; + +&rtc { + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56B87233156; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; cv=none; b=DDb4UegcKHRagZq6K8iLigqN1agnRSdWjqCvO9GWKBA2AIoVUeZ5BSpKcPcX5l0nNa/CVgTRPMZiHvetwUPCiWKQhcLx+9R5d1i+1vCgeOpCN1Bd4VTU1f/aBZdNB9wqqzQH87UdszEoThIORjVYJohp7kuUWjvtrhjD30WtKJU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; c=relaxed/simple; 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Wed, 16 Jul 2025 11:25:39 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 16 Jul 2025 19:25:12 +0800 Subject: [PATCH v3 3/9] MIPS: dts: loongson: Add LSGZ_1B_DEV board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-3-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=3677; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=wiZSXAnq9LUP/A9neq7bwgyCPMfuISQkRA8LZhDIlis=; b=LUQkl6mMHSbYnWSEY3s159jXGQVN/nkwUUysrqvOVNFEtx4tuMpRkeAqKRIGSr/XP2E2AxaRF X+dpF5yKCFXBBjbCAgErjVIB+n4pDF83r3JmYhXjrGWHRNMI6rRWA0F X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Add a device tree for LSGZ_1B_DEV board. Signed-off-by: Keguang Zhang --- arch/mips/boot/dts/loongson/Makefile | 1 + arch/mips/boot/dts/loongson/lsgz_1b_dev.dts | 162 ++++++++++++++++++++++++= ++++ 2 files changed, 163 insertions(+) diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loon= gson/Makefile index 88b87c94c545..1130efa12768 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64g_4core_ls7a.d= tb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64v_4core_virtio.dtb =20 dtb-$(CONFIG_MACH_LOONGSON32) +=3D ls1b-demo.dtb +dtb-$(CONFIG_MACH_LOONGSON32) +=3D lsgz_1b_dev.dtb diff --git a/arch/mips/boot/dts/loongson/lsgz_1b_dev.dts b/arch/mips/boot/d= ts/loongson/lsgz_1b_dev.dts new file mode 100644 index 000000000000..94ec151c0a94 --- /dev/null +++ b/arch/mips/boot/dts/loongson/lsgz_1b_dev.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; + +#include + +#include "loongson1b.dtsi" + +/ { + compatible =3D "loongson,lsgz-1b-dev", "loongson,ls1b"; + model =3D "LSGZ_1B_DEV Board"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x4000000>; + }; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + serial0 =3D &uart2; + serial1 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led9 { + label =3D "led9"; + gpios =3D <&gpio1 6 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led6 { + label =3D "led6"; + gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "nand-disk"; + }; + }; + + codec: audio-codec { + compatible =3D "realtek,alc203"; + #sound-dai-cells =3D <0>; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "ls1b-alc655"; + simple-audio-card,format =3D "ac97"; + simple-audio-card,widgets =3D + "Speaker", "Line Out Jack", + "Line", "Line In Jack", + "Microphone", "Microphone Jack"; + simple-audio-card,routing =3D + "Line Out Jack", "TX", + "RX", "Line In Jack", + "RX", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai =3D <&ac97>; + }; + + simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&xtal { + clock-frequency =3D <33000000>; +}; + +&gmac0 { + phy-handle =3D <&phy0>; + phy-mode =3D "mii"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg =3D <0x0>; + }; + }; +}; + +&gmac1 { + phy-handle =3D <&phy1>; + phy-mode =3D "mii"; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy1: ethernet-phy@0 { + reg =3D <0x0>; + }; + }; +}; + +&nand { + status =3D "okay"; + + nand@0 { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "kernel"; + reg =3D <0x0 0x1000000>; + }; + + partition@1000000 { + label =3D "rootfs"; + reg =3D <0x1000000 0x7000000>; + }; + }; + }; +}; + +&ac97 { + status =3D "okay"; +}; + +&ehci { + status =3D "okay"; +}; + +&ohci { + status =3D "okay"; +}; + +&rtc { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70E262F2C70; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; cv=none; b=Z5JQ7LPtIbTmmu9MbmRxHeJKJUYTkTxXKQioVM97TNH/lei25fdZU/M6mUZAFAohOwD4mn9qBKVsfGFfMbTEs82+GUV5+8mabDmtFGb2ooRr9rGaB8x/94ZB6K2pXrArmGjGHPFVYk/BmzgvYJcy3i8Zc/aDIexvaJFpiIYOdTQ= ARC-Message-Signature: i=1; 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b=Q1xC2W685gHQ2LpJ3DrmgLU5YHh8pnRuBn1PPdLF0bFm7uBYz6AI270qAH1jJD669 lSTacbicET6lzu94LMPh4QAcf5VBnFj/B+tvSrNZgP7E/S1KHDHDLcbZPhd55cuLnC HdmZVxZCgf0A/HefGCYHiHaWKbQj4/fKRlphHg1j1Y5stsddE85Hjz7OBxB6yUPOMU mSfKqbiFMlgyI4DPeHaWXMCUjuynxc0wecr6OYCpFPOLaqExn4MpJFX9QZ2f1xZP80 qs4THQSpn9LEobvmPYKhqczp/a8JvvwvQO72+QuCNJJhVe0Kp69iqEs/LsPqUYbiLS DeiJapKs9r80w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1646FC83F36; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 16 Jul 2025 19:25:13 +0800 Subject: [PATCH v3 4/9] MIPS: dts: loongson: Add Smartloong-1C board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-4-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=6198; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=8k4NI0ImdMzubiiidq5o64B1uZ6t3883T78WhKntQoM=; b=9pz1M1MZPhg//wLZGLTgnuvISVqBE2o4ua8T8UsjvfFDXOfjTxD0kBAeu9EStCkKaCQiPaMgk qreAQArdxfCApjSBk7zTls+9m4yDKqgFeyuFFe2rRM+AXVAqzvBE+0d X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Add a device tree for Smartloong-1C board, supporting CPU, clock, INTC, UART, Ethernet, GPIO, USB host, RTC, watchdog, DMA, and NAND. Signed-off-by: Keguang Zhang --- arch/mips/boot/dts/loongson/Makefile | 1 + arch/mips/boot/dts/loongson/loongson1c.dtsi | 141 ++++++++++++++++++++++= ++++ arch/mips/boot/dts/loongson/smartloong-1c.dts | 110 ++++++++++++++++++++ 3 files changed, 252 insertions(+) diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loon= gson/Makefile index 1130efa12768..de4570380c3e 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -8,3 +8,4 @@ dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64v_4core_virtio= .dtb =20 dtb-$(CONFIG_MACH_LOONGSON32) +=3D ls1b-demo.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D lsgz_1b_dev.dtb +dtb-$(CONFIG_MACH_LOONGSON32) +=3D smartloong-1c.dtb diff --git a/arch/mips/boot/dts/loongson/loongson1c.dtsi b/arch/mips/boot/d= ts/loongson/loongson1c.dtsi new file mode 100644 index 000000000000..5e80c6a657af --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson1c.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; +#include "loongson1.dtsi" + +/ { + clkc: clock-controller@1fe78030 { + compatible =3D "loongson,ls1c-clk"; + reg =3D <0x1fe78030 0x8>; + clocks =3D <&xtal>; + #clock-cells =3D <1>; + }; +}; + +&soc { + syscon: syscon@420 { + compatible =3D "loongson,ls1c-syscon", "syscon"; + reg =3D <0x420 0x8>; + }; + + intc4: interrupt-controller@10a0 { + compatible =3D "loongson,ls1x-intc"; + reg =3D <0x10a0 0x18>; + interrupt-controller; + interrupt-parent =3D <&cpu_intc>; + interrupts =3D <6>; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@10c8 { + compatible =3D "loongson,ls1x-gpio"; + reg =3D <0x10c8 0x4>; + gpio-controller; + ngpios =3D <32>; + #gpio-cells =3D <2>; + }; + + gpio3: gpio@10cc { + compatible =3D "loongson,ls1x-gpio"; + reg =3D <0x10cc 0x4>; + gpio-controller; + ngpios =3D <32>; + #gpio-cells =3D <2>; + }; + + dma: dma-controller@1160 { + compatible =3D "loongson,ls1c-apbdma", "loongson,ls1b-apbdma"; + reg =3D <0x1160 0x4>; + interrupt-parent =3D <&intc0>; + interrupts =3D <13 IRQ_TYPE_EDGE_RISING>, + <14 IRQ_TYPE_EDGE_RISING>, + <15 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "ch0", "ch1", "ch2"; + #dma-cells =3D <1>; + }; + + emac: ethernet@110000 { + compatible =3D "loongson,ls1c-emac", "snps,dwmac-3.50a"; + reg =3D <0x110000 0x10000>; + clocks =3D <&clkc LS1X_CLKID_AHB>; + clock-names =3D "stmmaceth"; + interrupt-parent =3D <&intc1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + loongson,ls1-syscon =3D <&syscon>; + snps,pbl =3D <1>; + status =3D "disabled"; + }; + + ehci: usb@120000 { + compatible =3D "generic-ehci"; + reg =3D <0x120000 0x100>; + interrupt-parent =3D <&intc1>; + interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + ohci: usb@128000 { + compatible =3D "generic-ohci"; + reg =3D <0x128000 0x100>; + interrupt-parent =3D <&intc1>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; +}; + +&apb { + watchdog: watchdog@1c060 { + compatible =3D "loongson,ls1c-wdt"; + reg =3D <0x1c060 0xc>; + clocks =3D <&clkc LS1X_CLKID_APB>; + status =3D "disabled"; + }; + + rtc: rtc@24000 { + compatible =3D "loongson,ls1c-rtc"; + reg =3D <0x24000 0x78>; + status =3D "disabled"; + }; + + nand: nand-controller@38000 { + compatible =3D "loongson,ls1c-nand-controller"; + reg =3D <0x38000 0x24>, <0x38040 0x4>; + reg-names =3D "nand", "nand-dma"; + dmas =3D <&dma 0>; + dma-names =3D "rxtx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + nand@0 { + reg =3D <0>; + label =3D "ls1x-nand"; + nand-use-soft-ecc-engine; + nand-ecc-algo =3D "hamming"; + }; + }; +}; + +&gpio0 { + ngpios =3D <32>; +}; + +&gpio1 { + ngpios =3D <32>; +}; + +&uart1 { + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart2 { + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart3 { + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/mips/boot/dts/loongson/smartloong-1c.dts b/arch/mips/boot= /dts/loongson/smartloong-1c.dts new file mode 100644 index 000000000000..e6c6c2f00c42 --- /dev/null +++ b/arch/mips/boot/dts/loongson/smartloong-1c.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; + +#include + +#include "loongson1c.dtsi" + +/ { + compatible =3D "loongmasses,smartloong-1c", "loongson,ls1c"; + model =3D "Smartloong-1C Board"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x4000000>; + }; + + aliases { + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + serial0 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led0 { + label =3D "led0"; + gpios =3D <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led1 { + label =3D "led1"; + gpios =3D <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "nand-disk"; + }; + }; +}; + +&xtal { + clock-frequency =3D <24000000>; +}; + +&emac { + phy-handle =3D <&phy0>; + phy-mode =3D "rmii"; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: ethernet-phy@13 { + reg =3D <0x13>; + }; + }; +}; + +&nand { + status =3D "okay"; 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a=ed25519-sha256; t=1752665136; l=2858; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=XttapQaz5tbqpiYUJ3NCDcmUjVIV/5rxCCiXN6plXoU=; b=3FcqK53IOcHkSeCcRK5D7QswnYAyrHfUyM/W4DqaGTMaRfgTZoSsfscsHBt2gXFirZXrDkeLU AY7TSZ+VMxpCwPkzCInQuBthXhKgTBclawyaC6HS6GF+7VqBNVtzC7O X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Add a device tree for CQ-T300B board. Signed-off-by: Keguang Zhang --- arch/mips/boot/dts/loongson/Makefile | 1 + arch/mips/boot/dts/loongson/cq-t300b.dts | 110 +++++++++++++++++++++++++++= ++++ 2 files changed, 111 insertions(+) diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loon= gson/Makefile index de4570380c3e..e8f76e7ac303 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64c_8core_rs780e= .dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64g_4core_ls7a.dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64v_4core_virtio.dtb =20 +dtb-$(CONFIG_MACH_LOONGSON32) +=3D cq-t300b.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D ls1b-demo.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D lsgz_1b_dev.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D smartloong-1c.dtb diff --git a/arch/mips/boot/dts/loongson/cq-t300b.dts b/arch/mips/boot/dts/= loongson/cq-t300b.dts new file mode 100644 index 000000000000..5244fab2496d --- /dev/null +++ b/arch/mips/boot/dts/loongson/cq-t300b.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2025 Keguang Zhang + */ + +/dts-v1/; + +#include + +#include "loongson1c.dtsi" + +/ { + compatible =3D "loongson,cq-t300b", "loongson,ls1c"; + model =3D "CQ-T300B Board"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x8000000>; + }; + + aliases { + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + serial0 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led0 { + label =3D "led0"; + gpios =3D <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led1 { + label =3D "led1"; + gpios =3D <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "nand-disk"; + }; + }; +}; + +&xtal { + clock-frequency =3D <24000000>; +}; + +&emac { + phy-handle =3D <&phy0>; + phy-mode =3D "rmii"; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: ethernet-phy@13 { + reg =3D <0x13>; + }; + }; +}; + +&nand { + status =3D "okay"; + + nand@0 { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "kernel"; + reg =3D <0x0 0x1000000>; + }; + + partition@1000000 { + label =3D "rootfs"; + reg =3D <0x1000000 0x3f000000>; + }; + }; + }; +}; + +&ehci { + status =3D "okay"; +}; + +&ohci { + status =3D "okay"; +}; + +&rtc { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DDD62F3C26; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; cv=none; b=PHsjsGUjZ4jWs8Rjw62o7ju9IbViuZZsNehsRwSiJ0zEddyEhu853TVrQ2/fjkyPIzjlrjswcNYCP8jH3yfZ455Bg/N5caZwxCQ38TXV9c9or2/9nEy7R3YGruoer0RoWqAEZ0r62/IMLvElXJvJQRf+uztujmCkEGSkjnQ93E4= ARC-Message-Signature: i=1; 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b=OdJSB8a4lreQSbVkuGufrxPLwz8roXHsSGGa5K2b15pNfpqYVqgWOYEi4JkRJa1e5 Gamy6QLqUMfJeb6zNjSgdigbiCZOP65VuOvvYn+T62fhymaeBJL6dU3gewA73cLXkT AQ7Lsx1ja/bhVty3BKg39yq6hl2XHCaX/QCa5GE6tooveVU8j7YTqWgS09ddMDAmHM 6TOSNGwKMEwbCJ8f+3a0hGg4ZgA2uT8J9muk0fBewmZ/pz72uh4X9lshkJdpSP8mi4 tK43PInb6pp3kO+SXchqFQW0GlkZELJHb4J9KIXN/B84XYbFdGLGvV1YagYeQ19gvD 7GODggEFBVuvA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30B3CC83F22; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 16 Jul 2025 19:25:15 +0800 Subject: [PATCH v3 6/9] MIPS: loongson: Add built-in DTB support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-6-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=1673; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=31SQDWI+tNppoJhNVuSV6AMxuxSd2DNTM292TR9KcKg=; b=L+LoNxrEHQl2Mx+K+EVi55An15Kt4JUfoUjnUxlLuX2OLJMHqpJ61OBLIkj4O8uqrNDnvVUGa s7m4DrreF/bAw+lOUx3wM7mh26FovUCvITkzkdAqWLcVeFbTiYG4T3t X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Since the current bootloader for Loongson-1 does not support FDT, introduce CONFIG_BUILTIN_DTB_NAME to enable a built-in DTB. Signed-off-by: Keguang Zhang --- arch/mips/boot/dts/loongson/Makefile | 5 +++++ arch/mips/loongson32/Kconfig | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loon= gson/Makefile index e8f76e7ac303..8ee12504d353 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 + +ifneq ($(CONFIG_BUILTIN_DTB_NAME),) +dtb-y :=3D $(addsuffix .dtb, $(CONFIG_BUILTIN_DTB_NAME)) +else dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64_2core_2k1000.dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64c_4core_ls7a.dtb dtb-$(CONFIG_MACH_LOONGSON64) +=3D loongson64c_4core_rs780e.dtb @@ -10,3 +14,4 @@ dtb-$(CONFIG_MACH_LOONGSON32) +=3D cq-t300b.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D ls1b-demo.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D lsgz_1b_dev.dtb dtb-$(CONFIG_MACH_LOONGSON32) +=3D smartloong-1c.dtb +endif diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig index a7c500959577..52e925309f15 100644 --- a/arch/mips/loongson32/Kconfig +++ b/arch/mips/loongson32/Kconfig @@ -36,3 +36,11 @@ config LOONGSON1_LS1C endchoice =20 endif # MACH_LOONGSON32 + +config BUILTIN_DTB_NAME + string "Source file for built-in DTB" + depends on BUILTIN_DTB + help + Base name (without suffix, relative to arch/mips/boot/dts/loongson) + for the DTS file that will be used to produce the DTB linked into + the kernel. --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B22A2F3C20; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-7-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=38933; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=gNAz/KYzHiQiKYNtodSEuIlhmgcYIUgHx7J+xTZ+mOk=; b=uF3WJYxteRgB0dTxhGBUrn+HgBCZQoyl76FiFsYuZcSZrHKqKv+mT3ouAh5eXIA/pnjDZ8nXg E3sU/ynarqKBReeycDGM9Y7XLqy6J4T55V7cEd5JU6Qy6gT6HkGk9YE X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang The generic MIPS core is fully compatible with Loongson-1 SoCs, so migrate Loongson-1 to it. Main changes are: - Merge CPU_LOONGSON1B and CPU_LOONGSON1C into a unified CPU_LOONGSON32, as both are based on the GS232 core. - Consolidate LOONGSON1_LS1B and LOONGSON1_LS1C Kconfig options into MACH_LOONGSON32. - Enable MACH_GENERIC_CORE and remove the legacy custom implementation. - Remove all Loongson-1 platform devices and associated code, which are now obsolete due to Device Tree support. - Misc cleanup. Partially based on earlier work by Jiaxun Yang. Link: https://lore.kernel.org/all/20190411121915.8040-4-jiaxun.yang@flygoat= .com/ Signed-off-by: Keguang Zhang --- MAINTAINERS | 1 - arch/mips/Kconfig | 64 ++--- arch/mips/include/asm/cpu-type.h | 3 +- arch/mips/include/asm/mach-loongson32/irq.h | 107 -------- arch/mips/include/asm/mach-loongson32/loongson1.h | 50 ---- arch/mips/include/asm/mach-loongson32/platform.h | 23 -- arch/mips/include/asm/mach-loongson32/regs-mux.h | 124 ---------- arch/mips/loongson32/Kconfig | 37 --- arch/mips/loongson32/Makefile | 17 -- arch/mips/loongson32/Platform | 1 - arch/mips/loongson32/common/Makefile | 6 - arch/mips/loongson32/common/irq.c | 191 --------------- arch/mips/loongson32/common/platform.c | 285 ------------------= ---- arch/mips/loongson32/common/prom.c | 42 ---- arch/mips/loongson32/common/setup.c | 26 -- arch/mips/loongson32/common/time.c | 23 -- arch/mips/loongson32/ls1b/Makefile | 6 - arch/mips/loongson32/ls1b/board.c | 55 ----- arch/mips/loongson32/ls1c/Makefile | 6 - arch/mips/loongson32/ls1c/board.c | 23 -- 20 files changed, 33 insertions(+), 1057 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 0089ebca31cf..d42a83656879 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16684,7 +16684,6 @@ L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml F: arch/mips/boot/dts/loongson/loongson1* -F: arch/mips/include/asm/mach-loongson32/ F: arch/mips/loongson32/ F: drivers/*/*loongson1* F: drivers/mtd/nand/raw/loongson1-nand-controller.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1e48184ecf1e..643236ab5a01 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -481,6 +481,23 @@ config LANTIQ =20 config MACH_LOONGSON32 bool "Loongson 32-bit family of machines" + select MACH_GENERIC_CORE + select USE_OF + select BUILTIN_DTB + select BOOT_ELF32 + select CEVT_R4K + select CSRC_R4K + select COMMON_CLK + select DMA_NONCOHERENT + select GENERIC_IRQ_SHOW_LEVEL + select IRQ_MIPS_CPU + select LS1X_IRQ + select SYS_HAS_CPU_LOONGSON32 + select SYS_HAS_EARLY_PRINTK + select USE_GENERIC_EARLY_PRINTK_8250 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_ZBOOT help This enables support for the Loongson-1 family of machines. @@ -1386,25 +1403,20 @@ config CPU_LOONGSON2F have a similar programming interface with FPGA northbridge used in Loongson2E. =20 -config CPU_LOONGSON1B - bool "Loongson 1B" - depends on SYS_HAS_CPU_LOONGSON1B - select CPU_LOONGSON32 - select LEDS_GPIO_REGISTER - help - The Loongson 1B is a 32-bit SoC, which implements the MIPS32 - Release 1 instruction set and part of the MIPS32 Release 2 - instruction set. - -config CPU_LOONGSON1C - bool "Loongson 1C" - depends on SYS_HAS_CPU_LOONGSON1C - select CPU_LOONGSON32 +config CPU_LOONGSON32 + bool "Loongson 32-bit CPU" + depends on SYS_HAS_CPU_LOONGSON32 + select CPU_MIPS32 + select CPU_MIPSR2 + select CPU_HAS_PREFETCH + select CPU_HAS_LOAD_STORE_LR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select CPU_SUPPORTS_CPUFREQ select LEDS_GPIO_REGISTER help - The Loongson 1C is a 32-bit SoC, which implements the MIPS32 - Release 1 instruction set and part of the MIPS32 Release 2 - instruction set. + The Loongson GS232 microarchitecture implements the MIPS32 Release 1 + instruction set and part of the MIPS32 Release 2 instruction set. =20 config CPU_MIPS32_R1 bool "MIPS32 Release 1" @@ -1838,15 +1850,6 @@ config CPU_LOONGSON2EF select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES =20 -config CPU_LOONGSON32 - bool - select CPU_MIPS32 - select CPU_MIPSR2 - select CPU_HAS_PREFETCH - select CPU_SUPPORTS_32BIT_KERNEL - select CPU_SUPPORTS_HIGHMEM - select CPU_SUPPORTS_CPUFREQ - config CPU_BMIPS32_3300 select SMP_UP if SMP bool @@ -1884,10 +1887,7 @@ config SYS_HAS_CPU_LOONGSON2F select CPU_SUPPORTS_CPUFREQ select CPU_SUPPORTS_ADDRWINCFG if 64BIT =20 -config SYS_HAS_CPU_LOONGSON1B - bool - -config SYS_HAS_CPU_LOONGSON1C +config SYS_HAS_CPU_LOONGSON32 bool =20 config SYS_HAS_CPU_MIPS32_R1 @@ -2999,8 +2999,8 @@ choice prompt "Kernel command line type" depends on !CMDLINE_OVERRIDE default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ - !MACH_LOONGSON64 && !MIPS_MALTA && \ - !CAVIUM_OCTEON_SOC + !MACH_LOONGSON64 && !MACH_LOONGSON32 && \ + !MIPS_MALTA && !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER =20 config MIPS_CMDLINE_FROM_DTB diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-t= ype.h index a4a66bd93748..fd37a44a2f19 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -24,8 +24,7 @@ static inline int __pure __get_cpu_type(const int cpu_typ= e) case CPU_LOONGSON64: #endif =20 -#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \ - defined(CONFIG_SYS_HAS_CPU_LOONGSON1C) +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON32 case CPU_LOONGSON32: #endif =20 diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/includ= e/asm/mach-loongson32/irq.h deleted file mode 100644 index 6115f025ba21..000000000000 --- a/arch/mips/include/asm/mach-loongson32/irq.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang - * - * IRQ mappings for Loongson 1 - */ - -#ifndef __ASM_MACH_LOONGSON32_IRQ_H -#define __ASM_MACH_LOONGSON32_IRQ_H - -/* - * CPU core Interrupt Numbers - */ -#define MIPS_CPU_IRQ_BASE 0 -#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) - -#define SOFTINT0_IRQ MIPS_CPU_IRQ(0) -#define SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_IRQ MIPS_CPU_IRQ(2) -#define INT1_IRQ MIPS_CPU_IRQ(3) -#define INT2_IRQ MIPS_CPU_IRQ(4) -#define INT3_IRQ MIPS_CPU_IRQ(5) -#define INT4_IRQ MIPS_CPU_IRQ(6) -#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ - -#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) - -/* - * INT0~3 Interrupt Numbers - */ -#define LS1X_IRQ_BASE MIPS_CPU_IRQS -#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) - -#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) -#if defined(CONFIG_LOONGSON1_LS1B) -#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) -#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) -#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) -#elif defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_UART1_IRQ LS1X_IRQ(0, 4) -#define LS1X_UART2_IRQ LS1X_IRQ(0, 5) -#endif -#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) -#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) -#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) -#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) -#define LS1X_AC97_IRQ LS1X_IRQ(0, 10) -#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) -#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) -#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) -#if defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_NAND_IRQ LS1X_IRQ(0, 16) -#endif -#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) -#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) -#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) -#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) -#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) -#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) -#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) -#if defined(CONFIG_LOONGSON1_LS1B) -#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) -#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) -#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) -#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) -#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) -#define LS1X_UART4_IRQ LS1X_IRQ(0, 29) -#define LS1X_UART5_IRQ LS1X_IRQ(0, 30) -#elif defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_UART3_IRQ LS1X_IRQ(0, 29) -#define LS1X_ADC_IRQ LS1X_IRQ(0, 30) -#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31) -#endif - -#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) -#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) -#if defined(CONFIG_LOONGSON1_LS1B) -#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) -#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) -#elif defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_OTG_IRQ LS1X_IRQ(1, 2) -#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3) -#define LS1X_CAM_IRQ LS1X_IRQ(1, 4) -#define LS1X_UART4_IRQ LS1X_IRQ(1, 5) -#define LS1X_UART5_IRQ LS1X_IRQ(1, 6) -#define LS1X_UART6_IRQ LS1X_IRQ(1, 7) -#define LS1X_UART7_IRQ LS1X_IRQ(1, 8) -#define LS1X_UART8_IRQ LS1X_IRQ(1, 9) -#define LS1X_UART9_IRQ LS1X_IRQ(1, 13) -#define LS1X_UART10_IRQ LS1X_IRQ(1, 14) -#define LS1X_UART11_IRQ LS1X_IRQ(1, 15) -#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17) -#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18) -#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19) -#endif - -#if defined(CONFIG_LOONGSON1_LS1B) -#define INTN 4 -#elif defined(CONFIG_LOONGSON1_LS1C) -#define INTN 5 -#endif - -#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE) - -#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) - -#endif /* __ASM_MACH_LOONGSON32_IRQ_H */ diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/= include/asm/mach-loongson32/loongson1.h deleted file mode 100644 index 84f45461c832..000000000000 --- a/arch/mips/include/asm/mach-loongson32/loongson1.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang - * - * Register mappings for Loongson 1 - */ - -#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H -#define __ASM_MACH_LOONGSON32_LOONGSON1_H - -#if defined(CONFIG_LOONGSON1_LS1B) -#define DEFAULT_MEMSIZE 64 /* If no memsize provided */ -#elif defined(CONFIG_LOONGSON1_LS1C) -#define DEFAULT_MEMSIZE 32 -#endif - -/* Loongson 1 Register Bases */ -#define LS1X_MUX_BASE 0x1fd00420 -#define LS1X_INTC_BASE 0x1fd01040 -#define LS1X_GPIO0_BASE 0x1fd010c0 -#define LS1X_GPIO1_BASE 0x1fd010c4 -#define LS1X_DMAC_BASE 0x1fd01160 -#define LS1X_CBUS_BASE 0x1fd011c0 -#define LS1X_EHCI_BASE 0x1fe00000 -#define LS1X_OHCI_BASE 0x1fe08000 -#define LS1X_GMAC0_BASE 0x1fe10000 -#define LS1X_GMAC1_BASE 0x1fe20000 - -#define LS1X_UART0_BASE 0x1fe40000 -#define LS1X_UART1_BASE 0x1fe44000 -#define LS1X_UART2_BASE 0x1fe48000 -#define LS1X_UART3_BASE 0x1fe4c000 -#define LS1X_CAN0_BASE 0x1fe50000 -#define LS1X_CAN1_BASE 0x1fe54000 -#define LS1X_I2C0_BASE 0x1fe58000 -#define LS1X_I2C1_BASE 0x1fe68000 -#define LS1X_I2C2_BASE 0x1fe70000 -#define LS1X_PWM0_BASE 0x1fe5c000 -#define LS1X_PWM1_BASE 0x1fe5c010 -#define LS1X_PWM2_BASE 0x1fe5c020 -#define LS1X_PWM3_BASE 0x1fe5c030 -#define LS1X_WDT_BASE 0x1fe5c060 -#define LS1X_RTC_BASE 0x1fe64000 -#define LS1X_AC97_BASE 0x1fe74000 -#define LS1X_NAND_BASE 0x1fe78000 -#define LS1X_CLK_BASE 0x1fe78030 - -#include - -#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */ diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/i= nclude/asm/mach-loongson32/platform.h deleted file mode 100644 index f74292b13bc3..000000000000 --- a/arch/mips/include/asm/mach-loongson32/platform.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang - */ - -#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H -#define __ASM_MACH_LOONGSON32_PLATFORM_H - -#include - -extern struct platform_device ls1x_uart_pdev; -extern struct platform_device ls1x_eth0_pdev; -extern struct platform_device ls1x_eth1_pdev; -extern struct platform_device ls1x_ehci_pdev; -extern struct platform_device ls1x_gpio0_pdev; -extern struct platform_device ls1x_gpio1_pdev; -extern struct platform_device ls1x_rtc_pdev; -extern struct platform_device ls1x_wdt_pdev; - -void __init ls1x_rtc_set_extclk(struct platform_device *pdev); -void __init ls1x_serial_set_uartclk(struct platform_device *pdev); - -#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/i= nclude/asm/mach-loongson32/regs-mux.h deleted file mode 100644 index 95788a4f03a0..000000000000 --- a/arch/mips/include/asm/mach-loongson32/regs-mux.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 Zhang, Keguang - * - * Loongson 1 MUX Register Definitions. - */ - -#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H -#define __ASM_MACH_LOONGSON32_REGS_MUX_H - -#define LS1X_MUX_REG(x) \ - ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x))) - -#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) -#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) - -#if defined(CONFIG_LOONGSON1_LS1B) -/* MUX CTRL0 Register Bits */ -#define UART0_USE_PWM23 BIT(28) -#define UART0_USE_PWM01 BIT(27) -#define UART1_USE_LCD0_5_6_11 BIT(26) -#define I2C2_USE_CAN1 BIT(25) -#define I2C1_USE_CAN0 BIT(24) -#define NAND3_USE_UART5 BIT(23) -#define NAND3_USE_UART4 BIT(22) -#define NAND3_USE_UART1_DAT BIT(21) -#define NAND3_USE_UART1_CTS BIT(20) -#define NAND3_USE_PWM23 BIT(19) -#define NAND3_USE_PWM01 BIT(18) -#define NAND2_USE_UART5 BIT(17) -#define NAND2_USE_UART4 BIT(16) -#define NAND2_USE_UART1_DAT BIT(15) -#define NAND2_USE_UART1_CTS BIT(14) -#define NAND2_USE_PWM23 BIT(13) -#define NAND2_USE_PWM01 BIT(12) -#define NAND1_USE_UART5 BIT(11) -#define NAND1_USE_UART4 BIT(10) -#define NAND1_USE_UART1_DAT BIT(9) -#define NAND1_USE_UART1_CTS BIT(8) -#define NAND1_USE_PWM23 BIT(7) -#define NAND1_USE_PWM01 BIT(6) -#define GMAC1_USE_UART1 BIT(4) -#define GMAC1_USE_UART0 BIT(3) -#define LCD_USE_UART0_DAT BIT(2) -#define LCD_USE_UART15 BIT(1) -#define LCD_USE_UART0 BIT(0) - -/* MUX CTRL1 Register Bits */ -#define USB_RESET BIT(31) -#define SPI1_CS_USE_PWM01 BIT(24) -#define SPI1_USE_CAN BIT(23) -#define DISABLE_DDR_CONFSPACE BIT(20) -#define DDR32TO16EN BIT(16) -#define GMAC1_SHUT BIT(13) -#define GMAC0_SHUT BIT(12) -#define USB_SHUT BIT(11) -#define UART1_3_USE_CAN1 BIT(5) -#define UART1_2_USE_CAN0 BIT(4) -#define GMAC1_USE_TXCLK BIT(3) -#define GMAC0_USE_TXCLK BIT(2) -#define GMAC1_USE_PWM23 BIT(1) -#define GMAC0_USE_PWM01 BIT(0) - -#elif defined(CONFIG_LOONGSON1_LS1C) - -/* SHUT_CTRL Register Bits */ -#define UART_SPLIT GENMASK(31, 30) -#define OUTPUT_CLK GENMASK(29, 26) -#define ADC_SHUT BIT(25) -#define SDIO_SHUT BIT(24) -#define DMA2_SHUT BIT(23) -#define DMA1_SHUT BIT(22) -#define DMA0_SHUT BIT(21) -#define SPI1_SHUT BIT(20) -#define SPI0_SHUT BIT(19) -#define I2C2_SHUT BIT(18) -#define I2C1_SHUT BIT(17) -#define I2C0_SHUT BIT(16) -#define AC97_SHUT BIT(15) -#define I2S_SHUT BIT(14) -#define UART3_SHUT BIT(13) -#define UART2_SHUT BIT(12) -#define UART1_SHUT BIT(11) -#define UART0_SHUT BIT(10) -#define CAN1_SHUT BIT(9) -#define CAN0_SHUT BIT(8) -#define ECC_SHUT BIT(7) -#define GMAC_SHUT BIT(6) -#define USBHOST_SHUT BIT(5) -#define USBOTG_SHUT BIT(4) -#define SDRAM_SHUT BIT(3) -#define SRAM_SHUT BIT(2) -#define CAM_SHUT BIT(1) -#define LCD_SHUT BIT(0) - -#define UART_SPLIT_SHIFT 30 -#define OUTPUT_CLK_SHIFT 26 - -/* MISC_CTRL Register Bits */ -#define USBHOST_RSTN BIT(31) -#define PHY_INTF_SELI GENMASK(30, 28) -#define AC97_EN BIT(25) -#define SDIO_DMA_EN GENMASK(24, 23) -#define ADC_DMA_EN BIT(22) -#define SDIO_USE_SPI1 BIT(17) -#define SDIO_USE_SPI0 BIT(16) -#define SRAM_CTRL GENMASK(15, 0) - -#define PHY_INTF_SELI_SHIFT 28 -#define SDIO_DMA_EN_SHIFT 23 -#define SRAM_CTRL_SHIFT 0 - -#define LS1X_CBUS_REG(n, x) \ - ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x))) - -#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00) -#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10) -#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20) -#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30) -#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40) - -#endif - -#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig index 52e925309f15..461d518b0033 100644 --- a/arch/mips/loongson32/Kconfig +++ b/arch/mips/loongson32/Kconfig @@ -1,41 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -if MACH_LOONGSON32 - -choice - prompt "Machine Type" - -config LOONGSON1_LS1B - bool "Loongson LS1B board" - select CEVT_R4K if !MIPS_EXTERNAL_TIMER - select CSRC_R4K if !MIPS_EXTERNAL_TIMER - select SYS_HAS_CPU_LOONGSON1B - select DMA_NONCOHERENT - select BOOT_ELF32 - select IRQ_MIPS_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select USE_GENERIC_EARLY_PRINTK_8250 - select COMMON_CLK - -config LOONGSON1_LS1C - bool "Loongson LS1C board" - select CEVT_R4K if !MIPS_EXTERNAL_TIMER - select CSRC_R4K if !MIPS_EXTERNAL_TIMER - select SYS_HAS_CPU_LOONGSON1C - select DMA_NONCOHERENT - select BOOT_ELF32 - select IRQ_MIPS_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select USE_GENERIC_EARLY_PRINTK_8250 - select COMMON_CLK -endchoice - -endif # MACH_LOONGSON32 =20 config BUILTIN_DTB_NAME string "Source file for built-in DTB" diff --git a/arch/mips/loongson32/Makefile b/arch/mips/loongson32/Makefile index ba10954b4b21..a4e40e534e6a 100644 --- a/arch/mips/loongson32/Makefile +++ b/arch/mips/loongson32/Makefile @@ -1,18 +1 @@ # SPDX-License-Identifier: GPL-2.0-only -# -# Common code for all Loongson 1 based systems -# - -obj-$(CONFIG_MACH_LOONGSON32) +=3D common/ - -# -# Loongson LS1B board -# - -obj-$(CONFIG_LOONGSON1_LS1B) +=3D ls1b/ - -# -# Loongson LS1C board -# - -obj-$(CONFIG_LOONGSON1_LS1C) +=3D ls1c/ diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform index 3b9673e7a2fa..67fd07450488 100644 --- a/arch/mips/loongson32/Platform +++ b/arch/mips/loongson32/Platform @@ -1,3 +1,2 @@ cflags-$(CONFIG_CPU_LOONGSON32) +=3D -march=3Dmips32r2 -Wa,--trap -cflags-$(CONFIG_MACH_LOONGSON32) +=3D -I$(srctree)/arch/mips/include/asm/m= ach-loongson32 load-$(CONFIG_CPU_LOONGSON32) +=3D 0xffffffff80200000 diff --git a/arch/mips/loongson32/common/Makefile b/arch/mips/loongson32/co= mmon/Makefile deleted file mode 100644 index f3950d308187..000000000000 --- a/arch/mips/loongson32/common/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for common code of loongson1 based machines. -# - -obj-y +=3D time.o irq.o platform.o prom.o setup.o diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/commo= n/irq.c deleted file mode 100644 index 9a50070f74f7..000000000000 --- a/arch/mips/loongson32/common/irq.c +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2011 Zhang, Keguang - */ - -#include -#include -#include - -#include -#include - -#define LS1X_INTC_REG(n, x) \ - ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x))) - -#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0) -#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4) -#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8) -#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc) -#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10) -#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14) - -static void ls1x_irq_ack(struct irq_data *d) -{ - unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f; - unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; - - __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) - | (1 << bit), LS1X_INTC_INTCLR(n)); -} - -static void ls1x_irq_mask(struct irq_data *d) -{ - unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f; - unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; - - __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) - & ~(1 << bit), LS1X_INTC_INTIEN(n)); -} - -static void ls1x_irq_mask_ack(struct irq_data *d) -{ - unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f; - unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; - - __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) - & ~(1 << bit), LS1X_INTC_INTIEN(n)); - __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) - | (1 << bit), LS1X_INTC_INTCLR(n)); -} - -static void ls1x_irq_unmask(struct irq_data *d) -{ - unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f; - unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; - - __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) - | (1 << bit), LS1X_INTC_INTIEN(n)); -} - -static int ls1x_irq_settype(struct irq_data *d, unsigned int type) -{ - unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f; - unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; - - switch (type) { - case IRQ_TYPE_LEVEL_HIGH: - __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) - | (1 << bit), LS1X_INTC_INTPOL(n)); - __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) - & ~(1 << bit), LS1X_INTC_INTEDGE(n)); - break; - case IRQ_TYPE_LEVEL_LOW: - __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) - & ~(1 << bit), LS1X_INTC_INTPOL(n)); - __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) - & ~(1 << bit), LS1X_INTC_INTEDGE(n)); - break; - case IRQ_TYPE_EDGE_RISING: - __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) - | (1 << bit), LS1X_INTC_INTPOL(n)); - __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) - | (1 << bit), LS1X_INTC_INTEDGE(n)); - break; - case IRQ_TYPE_EDGE_FALLING: - __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) - & ~(1 << bit), LS1X_INTC_INTPOL(n)); - __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) - | (1 << bit), LS1X_INTC_INTEDGE(n)); - break; - case IRQ_TYPE_EDGE_BOTH: - __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) - & ~(1 << bit), LS1X_INTC_INTPOL(n)); - __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) - | (1 << bit), LS1X_INTC_INTEDGE(n)); - break; - case IRQ_TYPE_NONE: - break; - default: - return -EINVAL; - } - - return 0; -} - -static struct irq_chip ls1x_irq_chip =3D { - .name =3D "LS1X-INTC", - .irq_ack =3D ls1x_irq_ack, - .irq_mask =3D ls1x_irq_mask, - .irq_mask_ack =3D ls1x_irq_mask_ack, - .irq_unmask =3D ls1x_irq_unmask, - .irq_set_type =3D ls1x_irq_settype, -}; - -static void ls1x_irq_dispatch(int n) -{ - u32 int_status, irq; - - /* Get pending sources, masked by current enables */ - int_status =3D __raw_readl(LS1X_INTC_INTISR(n)) & - __raw_readl(LS1X_INTC_INTIEN(n)); - - if (int_status) { - irq =3D LS1X_IRQ(n, __ffs(int_status)); - do_IRQ(irq); - } -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending; - - pending =3D read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(TIMER_IRQ); - else if (pending & CAUSEF_IP2) - ls1x_irq_dispatch(0); /* INT0 */ - else if (pending & CAUSEF_IP3) - ls1x_irq_dispatch(1); /* INT1 */ - else if (pending & CAUSEF_IP4) - ls1x_irq_dispatch(2); /* INT2 */ - else if (pending & CAUSEF_IP5) - ls1x_irq_dispatch(3); /* INT3 */ - else if (pending & CAUSEF_IP6) - ls1x_irq_dispatch(4); /* INT4 */ - else - spurious_interrupt(); - -} - -static void __init ls1x_irq_init(int base) -{ - int n; - - /* Disable interrupts and clear pending, - * setup all IRQs as high level triggered - */ - for (n =3D 0; n < INTN; n++) { - __raw_writel(0x0, LS1X_INTC_INTIEN(n)); - __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); - __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); - /* set DMA0, DMA1 and DMA2 to edge trigger */ - __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n)); - } - - - for (n =3D base; n < NR_IRQS; n++) { - irq_set_chip_and_handler(n, &ls1x_irq_chip, - handle_level_irq); - } - - if (request_irq(INT0_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to request irq %d (cascade)\n", INT0_IRQ); - if (request_irq(INT1_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to request irq %d (cascade)\n", INT1_IRQ); - if (request_irq(INT2_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to request irq %d (cascade)\n", INT2_IRQ); - if (request_irq(INT3_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to request irq %d (cascade)\n", INT3_IRQ); -#if defined(CONFIG_LOONGSON1_LS1C) - if (request_irq(INT4_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to request irq %d (cascade)\n", INT4_IRQ); -#endif -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); - ls1x_irq_init(LS1X_IRQ_BASE); -} diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/= common/platform.c deleted file mode 100644 index 623eb4bc7b41..000000000000 --- a/arch/mips/loongson32/common/platform.c +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2011-2016 Zhang, Keguang - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* 8250/16550 compatible UART */ -#define LS1X_UART(_id) \ - { \ - .mapbase =3D LS1X_UART ## _id ## _BASE, \ - .irq =3D LS1X_UART ## _id ## _IRQ, \ - .iotype =3D UPIO_MEM, \ - .flags =3D UPF_IOREMAP | UPF_FIXED_TYPE, \ - .type =3D PORT_16550A, \ - } - -static struct plat_serial8250_port ls1x_serial8250_pdata[] =3D { - LS1X_UART(0), - LS1X_UART(1), - LS1X_UART(2), - LS1X_UART(3), - {}, -}; - -struct platform_device ls1x_uart_pdev =3D { - .name =3D "serial8250", - .id =3D PLAT8250_DEV_PLATFORM, - .dev =3D { - .platform_data =3D ls1x_serial8250_pdata, - }, -}; - -void __init ls1x_serial_set_uartclk(struct platform_device *pdev) -{ - struct clk *clk; - struct plat_serial8250_port *p; - - clk =3D clk_get(&pdev->dev, pdev->name); - if (IS_ERR(clk)) { - pr_err("unable to get %s clock, err=3D%ld", - pdev->name, PTR_ERR(clk)); - return; - } - clk_prepare_enable(clk); - - for (p =3D pdev->dev.platform_data; p->flags !=3D 0; ++p) - p->uartclk =3D clk_get_rate(clk); -} - -/* Synopsys Ethernet GMAC */ -static struct stmmac_mdio_bus_data ls1x_mdio_bus_data =3D { - .phy_mask =3D 0, -}; - -static struct stmmac_dma_cfg ls1x_eth_dma_cfg =3D { - .pbl =3D 1, -}; - -int ls1x_eth_mux_init(struct platform_device *pdev, void *priv) -{ - struct plat_stmmacenet_data *plat_dat =3D NULL; - u32 val; - - val =3D __raw_readl(LS1X_MUX_CTRL1); - -#if defined(CONFIG_LOONGSON1_LS1B) - plat_dat =3D dev_get_platdata(&pdev->dev); - if (plat_dat->bus_id) { - __raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 | - GMAC1_USE_UART0, LS1X_MUX_CTRL0); - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_RGMII: - val &=3D ~(GMAC1_USE_TXCLK | GMAC1_USE_PWM23); - break; - case PHY_INTERFACE_MODE_MII: - val |=3D (GMAC1_USE_TXCLK | GMAC1_USE_PWM23); - break; - default: - pr_err("unsupported mii mode %d\n", - plat_dat->phy_interface); - return -ENOTSUPP; - } - val &=3D ~GMAC1_SHUT; - } else { - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_RGMII: - val &=3D ~(GMAC0_USE_TXCLK | GMAC0_USE_PWM01); - break; - case PHY_INTERFACE_MODE_MII: - val |=3D (GMAC0_USE_TXCLK | GMAC0_USE_PWM01); - break; - default: - pr_err("unsupported mii mode %d\n", - plat_dat->phy_interface); - return -ENOTSUPP; - } - val &=3D ~GMAC0_SHUT; - } - __raw_writel(val, LS1X_MUX_CTRL1); -#elif defined(CONFIG_LOONGSON1_LS1C) - plat_dat =3D dev_get_platdata(&pdev->dev); - - val &=3D ~PHY_INTF_SELI; - if (plat_dat->phy_interface =3D=3D PHY_INTERFACE_MODE_RMII) - val |=3D 0x4 << PHY_INTF_SELI_SHIFT; - __raw_writel(val, LS1X_MUX_CTRL1); - - val =3D __raw_readl(LS1X_MUX_CTRL0); - __raw_writel(val & (~GMAC_SHUT), LS1X_MUX_CTRL0); -#endif - - return 0; -} - -static struct plat_stmmacenet_data ls1x_eth0_pdata =3D { - .bus_id =3D 0, - .phy_addr =3D -1, -#if defined(CONFIG_LOONGSON1_LS1B) - .phy_interface =3D PHY_INTERFACE_MODE_MII, -#elif defined(CONFIG_LOONGSON1_LS1C) - .phy_interface =3D PHY_INTERFACE_MODE_RMII, -#endif - .mdio_bus_data =3D &ls1x_mdio_bus_data, - .dma_cfg =3D &ls1x_eth_dma_cfg, - .has_gmac =3D 1, - .tx_coe =3D 1, - .rx_queues_to_use =3D 1, - .tx_queues_to_use =3D 1, - .init =3D ls1x_eth_mux_init, -}; - -static struct resource ls1x_eth0_resources[] =3D { - [0] =3D { - .start =3D LS1X_GMAC0_BASE, - .end =3D LS1X_GMAC0_BASE + SZ_64K - 1, - .flags =3D IORESOURCE_MEM, - }, - [1] =3D { - .name =3D "macirq", - .start =3D LS1X_GMAC0_IRQ, - .flags =3D IORESOURCE_IRQ, - }, -}; - -struct platform_device ls1x_eth0_pdev =3D { - .name =3D "stmmaceth", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ls1x_eth0_resources), - .resource =3D ls1x_eth0_resources, - .dev =3D { - .platform_data =3D &ls1x_eth0_pdata, - }, -}; - -#ifdef CONFIG_LOONGSON1_LS1B -static struct plat_stmmacenet_data ls1x_eth1_pdata =3D { - .bus_id =3D 1, - .phy_addr =3D -1, - .phy_interface =3D PHY_INTERFACE_MODE_MII, - .mdio_bus_data =3D &ls1x_mdio_bus_data, - .dma_cfg =3D &ls1x_eth_dma_cfg, - .has_gmac =3D 1, - .tx_coe =3D 1, - .rx_queues_to_use =3D 1, - .tx_queues_to_use =3D 1, - .init =3D ls1x_eth_mux_init, -}; - -static struct resource ls1x_eth1_resources[] =3D { - [0] =3D { - .start =3D LS1X_GMAC1_BASE, - .end =3D LS1X_GMAC1_BASE + SZ_64K - 1, - .flags =3D IORESOURCE_MEM, - }, - [1] =3D { - .name =3D "macirq", - .start =3D LS1X_GMAC1_IRQ, - .flags =3D IORESOURCE_IRQ, - }, -}; - -struct platform_device ls1x_eth1_pdev =3D { - .name =3D "stmmaceth", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ls1x_eth1_resources), - .resource =3D ls1x_eth1_resources, - .dev =3D { - .platform_data =3D &ls1x_eth1_pdata, - }, -}; -#endif /* CONFIG_LOONGSON1_LS1B */ - -/* GPIO */ -static struct resource ls1x_gpio0_resources[] =3D { - [0] =3D { - .start =3D LS1X_GPIO0_BASE, - .end =3D LS1X_GPIO0_BASE + SZ_4 - 1, - .flags =3D IORESOURCE_MEM, - }, -}; - -struct platform_device ls1x_gpio0_pdev =3D { - .name =3D "ls1x-gpio", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ls1x_gpio0_resources), - .resource =3D ls1x_gpio0_resources, -}; - -static struct resource ls1x_gpio1_resources[] =3D { - [0] =3D { - .start =3D LS1X_GPIO1_BASE, - .end =3D LS1X_GPIO1_BASE + SZ_4 - 1, - .flags =3D IORESOURCE_MEM, - }, -}; - -struct platform_device ls1x_gpio1_pdev =3D { - .name =3D "ls1x-gpio", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ls1x_gpio1_resources), - .resource =3D ls1x_gpio1_resources, -}; - -/* USB EHCI */ -static u64 ls1x_ehci_dmamask =3D DMA_BIT_MASK(32); - -static struct resource ls1x_ehci_resources[] =3D { - [0] =3D { - .start =3D LS1X_EHCI_BASE, - .end =3D LS1X_EHCI_BASE + SZ_32K - 1, - .flags =3D IORESOURCE_MEM, - }, - [1] =3D { - .start =3D LS1X_EHCI_IRQ, - .flags =3D IORESOURCE_IRQ, - }, -}; - -static struct usb_ehci_pdata ls1x_ehci_pdata =3D { -}; - -struct platform_device ls1x_ehci_pdev =3D { - .name =3D "ehci-platform", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ls1x_ehci_resources), - .resource =3D ls1x_ehci_resources, - .dev =3D { - .dma_mask =3D &ls1x_ehci_dmamask, - .platform_data =3D &ls1x_ehci_pdata, - }, -}; - -/* Real Time Clock */ -struct platform_device ls1x_rtc_pdev =3D { - .name =3D "ls1x-rtc", - .id =3D -1, -}; - -/* Watchdog */ -static struct resource ls1x_wdt_resources[] =3D { - { - .start =3D LS1X_WDT_BASE, - .end =3D LS1X_WDT_BASE + SZ_16 - 1, - .flags =3D IORESOURCE_MEM, - }, -}; - -struct platform_device ls1x_wdt_pdev =3D { - .name =3D "ls1x-wdt", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ls1x_wdt_resources), - .resource =3D ls1x_wdt_resources, -}; diff --git a/arch/mips/loongson32/common/prom.c b/arch/mips/loongson32/comm= on/prom.c deleted file mode 100644 index fc580a22748e..000000000000 --- a/arch/mips/loongson32/common/prom.c +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2011 Zhang, Keguang - * - * Modified from arch/mips/pnx833x/common/prom.c. - */ - -#include -#include -#include -#include -#include - -#include - -unsigned long memsize; - -void __init prom_init(void) -{ - void __iomem *uart_base; - - fw_init_cmdline(); - - memsize =3D fw_getenvl("memsize"); - if(!memsize) - memsize =3D DEFAULT_MEMSIZE; - - if (strstr(arcs_cmdline, "console=3DttyS3")) - uart_base =3D ioremap(LS1X_UART3_BASE, 0x0f); - else if (strstr(arcs_cmdline, "console=3DttyS2")) - uart_base =3D ioremap(LS1X_UART2_BASE, 0x0f); - else if (strstr(arcs_cmdline, "console=3DttyS1")) - uart_base =3D ioremap(LS1X_UART1_BASE, 0x0f); - else - uart_base =3D ioremap(LS1X_UART0_BASE, 0x0f); - setup_8250_early_printk_port((unsigned long)uart_base, 0, 0); -} - -void __init plat_mem_setup(void) -{ - memblock_add(0x0, (memsize << 20)); -} diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/com= mon/setup.c deleted file mode 100644 index 4733fe037176..000000000000 --- a/arch/mips/loongson32/common/setup.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2011 Zhang, Keguang - */ - -#include -#include -#include -#include -#include - -const char *get_system_type(void) -{ - unsigned int processor_id =3D (¤t_cpu_data)->processor_id; - - switch (processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: -#if defined(CONFIG_LOONGSON1_LS1B) - return "LOONGSON LS1B"; -#elif defined(CONFIG_LOONGSON1_LS1C) - return "LOONGSON LS1C"; -#endif - default: - return "LOONGSON (unknown)"; - } -} diff --git a/arch/mips/loongson32/common/time.c b/arch/mips/loongson32/comm= on/time.c deleted file mode 100644 index 74ad2b17918d..000000000000 --- a/arch/mips/loongson32/common/time.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2014 Zhang, Keguang - */ - -#include -#include -#include - -void __init plat_time_init(void) -{ - struct clk *clk =3D NULL; - - /* initialize LS1X clocks */ - of_clk_init(NULL); - - /* setup mips r4k timer */ - clk =3D clk_get(NULL, "cpu_clk"); - if (IS_ERR(clk)) - panic("unable to get cpu clock, err=3D%ld", PTR_ERR(clk)); - - mips_hpt_frequency =3D clk_get_rate(clk) / 2; -} diff --git a/arch/mips/loongson32/ls1b/Makefile b/arch/mips/loongson32/ls1b= /Makefile deleted file mode 100644 index 33c574dc0f7f..000000000000 --- a/arch/mips/loongson32/ls1b/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for loongson1B based machines. -# - -obj-y +=3D board.o diff --git a/arch/mips/loongson32/ls1b/board.c b/arch/mips/loongson32/ls1b/= board.c deleted file mode 100644 index fe115bdcb22c..000000000000 --- a/arch/mips/loongson32/ls1b/board.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2011-2016 Zhang, Keguang - */ - -#include -#include -#include - -#include -#include - -static const struct gpio_led ls1x_gpio_leds[] __initconst =3D { - { - .name =3D "LED9", - .default_trigger =3D "heartbeat", - .gpio =3D 38, - .active_low =3D 1, - .default_state =3D LEDS_GPIO_DEFSTATE_OFF, - }, { - .name =3D "LED6", - .default_trigger =3D "nand-disk", - .gpio =3D 39, - .active_low =3D 1, - .default_state =3D LEDS_GPIO_DEFSTATE_OFF, - }, -}; - -static const struct gpio_led_platform_data ls1x_led_pdata __initconst =3D { - .num_leds =3D ARRAY_SIZE(ls1x_gpio_leds), - .leds =3D ls1x_gpio_leds, -}; - -static struct platform_device *ls1b_platform_devices[] __initdata =3D { - &ls1x_uart_pdev, - &ls1x_eth0_pdev, - &ls1x_eth1_pdev, - &ls1x_ehci_pdev, - &ls1x_gpio0_pdev, - &ls1x_gpio1_pdev, - &ls1x_rtc_pdev, - &ls1x_wdt_pdev, -}; - -static int __init ls1b_platform_init(void) -{ - ls1x_serial_set_uartclk(&ls1x_uart_pdev); - - gpio_led_register_device(-1, &ls1x_led_pdata); - - return platform_add_devices(ls1b_platform_devices, - ARRAY_SIZE(ls1b_platform_devices)); -} - -arch_initcall(ls1b_platform_init); diff --git a/arch/mips/loongson32/ls1c/Makefile b/arch/mips/loongson32/ls1c= /Makefile deleted file mode 100644 index 1cf3aa264d55..000000000000 --- a/arch/mips/loongson32/ls1c/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for loongson1C based machines. -# - -obj-y +=3D board.o diff --git a/arch/mips/loongson32/ls1c/board.c b/arch/mips/loongson32/ls1c/= board.c deleted file mode 100644 index 9dcfe9de55b0..000000000000 --- a/arch/mips/loongson32/ls1c/board.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2016 Yang Ling - */ - -#include - -static struct platform_device *ls1c_platform_devices[] __initdata =3D { - &ls1x_uart_pdev, - &ls1x_eth0_pdev, - &ls1x_rtc_pdev, - &ls1x_wdt_pdev, -}; - -static int __init ls1c_platform_init(void) -{ - ls1x_serial_set_uartclk(&ls1x_uart_pdev); - - return platform_add_devices(ls1c_platform_devices, - ARRAY_SIZE(ls1c_platform_devices)); -} - -arch_initcall(ls1c_platform_init); --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E3292F3C2A; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; cv=none; b=JVoIhOA4+4K3P/c5kdoMOWqji/bPERXH13glyUHcWF/fFpSk1aOc7ItLzcC09JrdGAcB7QcgsESpP2FqvwX1FAXctXNODEiXQhSYknP+mlzg89KmwQCgXMH3KBcjIVQ5rr2BslVqzKjXUjL+M5cwa8gOBOMYngAKa4f3e2yX8Ok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; c=relaxed/simple; bh=fU7P0kdRGYXi4DlP9jTpt63rE8Tbf8cPi2O5ducVVIc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eyEca9OJSmmsRL0bpJqeLsjQsI4sHYN4LRsdKfki/FkIiO/lt0BR7Z7UXswDQceG74pY9mcjMpIHFNy9XU1LTttWlxC9Ar5aE3rkTlcEdsdtBtBeeJwqx9r5cNOS4Y7kTA3XAHt74acu1uFWEHDq3t+JSZMvH2GYyuZ15T+Z1ws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TWhACfKy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TWhACfKy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5A38DC19424; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752665139; bh=fU7P0kdRGYXi4DlP9jTpt63rE8Tbf8cPi2O5ducVVIc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TWhACfKyQ4aqtlLEOhcovW8l1uGcEZ/GPIWc+zL2tfI2W/7ZPTcXeHsdZccZG9sO3 KR6g36eQ3LG4gE7xnNX09E7p8PTLqOVIqZydZQ7y4NN9EExSBD4sprYBkQ71KRo2iv 0jwWsyS1ruA0px+IqAZ9Yv03y+uWJYBUOueIDRA7+APU6ED/sVoAAq1RkEYpA4u9H2 l8XOLQ1R/tDM+t+mDU27ET5YKz378zWdxCDkL4Nmv+ezxdQYPWQy5lBZas2ybV8YNT gsxaZAFdtSWz430suVl71hCATOWHUvEo/oE7KZHvpTPjdtiHnCXJaNOPqac7/aQl5W 5F5wxLeCL44/g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50BA7C83F27; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 16 Jul 2025 19:25:17 +0800 Subject: [PATCH v3 8/9] MIPS: Unify Loongson1 PRID_REV Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-8-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=1706; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=gUS5VFP2+HU6UgsUMUAXlQqSqNjhcNxWcW8wuO4vtbs=; b=RIqknvnlgePzsVYGaK4A+AUQMqSOzZwjxBZ2GeXqCQWM8Sb9RQSxjMpvVdr4su7gQWLBujpRw /oWJGZe1jqzDT1YlKyKNGUWpOQxm86vr2EfKPVwGvQESfg7rtwIXJGs X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang LS1B and LS1C share the same PRID value, so unify them into a single definition: PRID_REV_LOONGSON1. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Keguang Zhang --- arch/mips/include/asm/cpu.h | 3 +-- arch/mips/kernel/cpu-probe.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index ecb9854cb432..4163b22c0a9a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -248,8 +248,7 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 -#define PRID_REV_LOONGSON1B 0x0020 -#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ +#define PRID_REV_LOONGSON1 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON2K_R1_0 0x0000 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index af7412549e6e..ca1ab765d4ac 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1286,14 +1286,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_= mips *c, unsigned int cpu) set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); c->writecombine =3D _CACHE_UNCACHED_ACCELERATED; break; - case PRID_IMP_LOONGSON_32: /* Loongson-1 */ + case PRID_IMP_LOONGSON_32: decode_configs(c); =20 c->cputype =3D CPU_LOONGSON32; =20 switch (c->processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: - __cpu_name[cpu] =3D "Loongson 1B"; + case PRID_REV_LOONGSON1: + __cpu_name[cpu] =3D "ICT Loongson-1"; break; } =20 --=20 2.43.0 From nobody Tue Oct 7 00:22:43 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B621C2F3C3E; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752665139; cv=none; b=hepYH+/Ru1p6uiaC6IZAt/OzcUfWcDmBkG9/e959FD4krhtM9v3wqDLZGh/cJNaoQSiyUmLOrHqGkYU6bOk0rt6MHSVGezoukgTc3j/uhFDPSMkFo420poj2/E/qLPkb6LEyeIj/IcFNWFQTYsSaNUf++y5+9mLf6NTfW47jE8s= ARC-Message-Signature: i=1; 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b=gk3tx/tivZ9M2H6ZJ1ebouXZwJTZ7cHj5vyzmGQ+EUnjNQP08kXPhXIXOtuMX2td0 xZNdCC0SUIKVZmbMqiMrC9/yWi/9hPS+hW5l5gQ5r769Wdn7uq70tphW+FHEuzeWWh VuhPVTHD+HTQ974n6ZxcYkt0x+j2Ra4MHUhHr2l8mXOf8xnqTTJLQ0IH800A5xSnHI 9TNePbKN0uTszVo0dXvFrmTDxxnaaOEzV7VZ7SvBoq8LQoby1JMflx/IJxpFAxmTMC L5DTivAidpvnYFGWaZZ/imCr+8aHSLiNgPR++KsOpX6vekSlCVGHsTPKDsOsqY982y UgTXjOjJ/FVaA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6080BC83F34; Wed, 16 Jul 2025 11:25:39 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 16 Jul 2025 19:25:18 +0800 Subject: [PATCH v3 9/9] MIPS: configs: Consolidate Loongson1 defconfigs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250716-loongson1-arch-v3-9-d160974d696b@gmail.com> References: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> In-Reply-To: <20250716-loongson1-arch-v3-0-d160974d696b@gmail.com> To: Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxun Yang , Keguang Zhang Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752665136; l=10713; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=vXaIa8N3GToUGpAmk80FkzsQAYrU6OjHna1ZLvsKN7s=; b=TXulWvlekYH10mgmEKNMpSHZTHGFm8BteCB79xroD70KiFpzV6qJYpFNDO4DVjYMiYCQT6p54 l/U+F+LkfKeCuzSnNVe6ArwGVVhXuauePC+GKQ9Eh7eA2OAgW939W17 X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Unify loongson{1b,1c}_defconfig into a single loongson1_defconfig. Enable the following options by default: - CONFIG_SERIAL_OF_PLATFORM - CONFIG_RTC_DRV_LOONGSON - CONFIG_LOONGSON1_APB_DMA - CONFIG_MTD_NAND_LOONGSON1 - CONFIG_SND_LOONGSON1_AC97 Also disable unnecessary options. Signed-off-by: Keguang Zhang --- MAINTAINERS | 1 + .../{loongson1b_defconfig =3D> loongson1_defconfig} | 94 +++++++++++++--- arch/mips/configs/loongson1c_defconfig | 121 -----------------= ---- 3 files changed, 78 insertions(+), 138 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d42a83656879..c73e25af147c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16684,6 +16684,7 @@ L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml F: arch/mips/boot/dts/loongson/loongson1* +F: arch/mips/configs/loongson1_defconfig F: arch/mips/loongson32/ F: drivers/*/*loongson1* F: drivers/mtd/nand/raw/loongson1-nand-controller.c diff --git a/arch/mips/configs/loongson1b_defconfig b/arch/mips/configs/loo= ngson1_defconfig similarity index 51% rename from arch/mips/configs/loongson1b_defconfig rename to arch/mips/configs/loongson1_defconfig index 68207b31dc20..81acae6f61c8 100644 --- a/arch/mips/configs/loongson1b_defconfig +++ b/arch/mips/configs/loongson1_defconfig @@ -1,7 +1,6 @@ # CONFIG_LOCALVERSION_AUTO is not set CONFIG_KERNEL_XZ=3Dy CONFIG_SYSVIPC=3Dy -CONFIG_HIGH_RES_TIMERS=3Dy CONFIG_PREEMPT=3Dy CONFIG_BSD_PROCESS_ACCT=3Dy CONFIG_BSD_PROCESS_ACCT_V3=3Dy @@ -12,15 +11,16 @@ CONFIG_NAMESPACES=3Dy CONFIG_CC_OPTIMIZE_FOR_SIZE=3Dy CONFIG_EXPERT=3Dy CONFIG_PERF_EVENTS=3Dy -# CONFIG_COMPAT_BRK is not set CONFIG_MACH_LOONGSON32=3Dy -# CONFIG_SECCOMP is not set # CONFIG_SUSPEND is not set +# CONFIG_SECCOMP is not set +# CONFIG_GCC_PLUGINS is not set CONFIG_MODULES=3Dy CONFIG_MODULE_UNLOAD=3Dy CONFIG_MODVERSIONS=3Dy -# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set CONFIG_NET=3Dy CONFIG_PACKET=3Dy CONFIG_UNIX=3Dy @@ -31,6 +31,7 @@ CONFIG_SYN_COOKIES=3Dy # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set +# CONFIG_ETHTOOL_NETLINK is not set CONFIG_DEVTMPFS=3Dy CONFIG_DEVTMPFS_MOUNT=3Dy # CONFIG_STANDALONE is not set @@ -38,32 +39,75 @@ CONFIG_MTD=3Dy CONFIG_MTD_CMDLINE_PARTS=3Dy CONFIG_MTD_BLOCK=3Dy CONFIG_MTD_RAW_NAND=3Dy +CONFIG_MTD_NAND_LOONGSON1=3Dy CONFIG_MTD_UBI=3Dy CONFIG_BLK_DEV_LOOP=3Dy CONFIG_SCSI=3Dm # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=3Dm +# CONFIG_BLK_DEV_BSG is not set # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=3Dy +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set CONFIG_STMMAC_ETH=3Dy +# CONFIG_DWMAC_GENERIC is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_DAVICOM_PHY=3Dy +CONFIG_REALTEK_PHY=3Dy +# CONFIG_USB_NET_DRIVERS is not set # CONFIG_WLAN is not set CONFIG_INPUT_EVDEV=3Dy # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set +# CONFIG_VT_CONSOLE is not set CONFIG_VT_HW_CONSOLE_BINDING=3Dy CONFIG_LEGACY_PTY_COUNT=3D8 CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_OF_PLATFORM=3Dy # CONFIG_HW_RANDOM is not set +# CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIOLIB=3Dy CONFIG_GPIO_LOONGSON1=3Dy # CONFIG_HWMON is not set @@ -71,7 +115,15 @@ CONFIG_WATCHDOG=3Dy CONFIG_WATCHDOG_NOWAYOUT=3Dy CONFIG_WATCHDOG_SYSFS=3Dy CONFIG_LOONGSON1_WDT=3Dy -# CONFIG_VGA_CONSOLE is not set +CONFIG_SOUND=3Dy +CONFIG_SND=3Dy +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=3Dy +CONFIG_SND_LOONGSON1_AC97=3Dy +CONFIG_SND_SIMPLE_CARD=3Dy CONFIG_HID_GENERIC=3Dm CONFIG_USB_HID=3Dm CONFIG_USB=3Dy @@ -86,17 +138,20 @@ CONFIG_NEW_LEDS=3Dy CONFIG_LEDS_CLASS=3Dy CONFIG_LEDS_GPIO=3Dy CONFIG_LEDS_TRIGGERS=3Dy +CONFIG_LEDS_TRIGGER_MTD=3Dy CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy CONFIG_RTC_CLASS=3Dy -CONFIG_RTC_DRV_LOONGSON1=3Dy +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_LOONGSON=3Dy +CONFIG_DMADEVICES=3Dy +CONFIG_LOONGSON1_APB_DMA=3Dy +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_MIPS_PLATFORM_DEVICES is not set # CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=3Dy -CONFIG_EXT2_FS_XATTR=3Dy -CONFIG_EXT2_FS_POSIX_ACL=3Dy -CONFIG_EXT2_FS_SECURITY=3Dy -CONFIG_EXT3_FS=3Dy -CONFIG_EXT3_FS_POSIX_ACL=3Dy -CONFIG_EXT3_FS_SECURITY=3Dy +# CONFIG_NVMEM is not set +CONFIG_EXT4_FS=3Dy +CONFIG_EXT4_FS_POSIX_ACL=3Dy # CONFIG_DNOTIFY is not set CONFIG_VFAT_FS=3Dy CONFIG_PROC_KCORE=3Dy @@ -105,16 +160,21 @@ CONFIG_TMPFS_POSIX_ACL=3Dy CONFIG_UBIFS_FS=3Dy CONFIG_UBIFS_FS_ADVANCED_COMPR=3Dy CONFIG_UBIFS_ATIME_SUPPORT=3Dy +# CONFIG_UBIFS_FS_SECURITY is not set CONFIG_NFS_FS=3Dy CONFIG_ROOT_NFS=3Dy CONFIG_NLS_CODEPAGE_437=3Dm CONFIG_NLS_ISO8859_1=3Dm -# CONFIG_CRYPTO_ECHAINIV is not set # CONFIG_CRYPTO_HW is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_ARM64 is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_RISCV is not set CONFIG_DYNAMIC_DEBUG=3Dy -CONFIG_DEBUG_FS=3Dy +# CONFIG_DEBUG_MISC is not set CONFIG_MAGIC_SYSRQ=3Dy -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set # CONFIG_EARLY_PRINTK is not set diff --git a/arch/mips/configs/loongson1c_defconfig b/arch/mips/configs/loo= ngson1c_defconfig deleted file mode 100644 index c3910a9dee9e..000000000000 --- a/arch/mips/configs/loongson1c_defconfig +++ /dev/null @@ -1,121 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_KERNEL_XZ=3Dy -CONFIG_SYSVIPC=3Dy -CONFIG_HIGH_RES_TIMERS=3Dy -CONFIG_PREEMPT=3Dy -CONFIG_BSD_PROCESS_ACCT=3Dy -CONFIG_BSD_PROCESS_ACCT_V3=3Dy -CONFIG_IKCONFIG=3Dy -CONFIG_IKCONFIG_PROC=3Dy -CONFIG_LOG_BUF_SHIFT=3D16 -CONFIG_NAMESPACES=3Dy -CONFIG_CC_OPTIMIZE_FOR_SIZE=3Dy -CONFIG_EXPERT=3Dy -CONFIG_PERF_EVENTS=3Dy -# CONFIG_COMPAT_BRK is not set -CONFIG_MACH_LOONGSON32=3Dy -CONFIG_LOONGSON1_LS1C=3Dy -# CONFIG_SECCOMP is not set -# CONFIG_SUSPEND is not set -CONFIG_MODULES=3Dy -CONFIG_MODULE_UNLOAD=3Dy -CONFIG_MODVERSIONS=3Dy -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_NET=3Dy -CONFIG_PACKET=3Dy -CONFIG_UNIX=3Dy -CONFIG_INET=3Dy -CONFIG_IP_PNP=3Dy -CONFIG_IP_PNP_DHCP=3Dy -CONFIG_SYN_COOKIES=3Dy -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_DEVTMPFS=3Dy -CONFIG_DEVTMPFS_MOUNT=3Dy -# CONFIG_STANDALONE is not set -CONFIG_MTD=3Dy -CONFIG_MTD_CMDLINE_PARTS=3Dy -CONFIG_MTD_BLOCK=3Dy -CONFIG_MTD_RAW_NAND=3Dy -CONFIG_MTD_UBI=3Dy -CONFIG_BLK_DEV_LOOP=3Dy -CONFIG_SCSI=3Dm -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=3Dm -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=3Dy -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -CONFIG_STMMAC_ETH=3Dy -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_EVDEV=3Dy -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=3Dy -CONFIG_LEGACY_PTY_COUNT=3D8 -CONFIG_SERIAL_8250=3Dy -CONFIG_SERIAL_8250_CONSOLE=3Dy -# CONFIG_HW_RANDOM is not set -CONFIG_GPIOLIB=3Dy -CONFIG_GPIO_LOONGSON1=3Dy -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=3Dy -CONFIG_WATCHDOG_NOWAYOUT=3Dy -CONFIG_WATCHDOG_SYSFS=3Dy -CONFIG_LOONGSON1_WDT=3Dy -# CONFIG_VGA_CONSOLE is not set -CONFIG_HID_GENERIC=3Dm -CONFIG_USB_HID=3Dm -CONFIG_USB=3Dy -CONFIG_USB_ANNOUNCE_NEW_DEVICES=3Dy -CONFIG_USB_EHCI_HCD=3Dy -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -CONFIG_USB_EHCI_HCD_PLATFORM=3Dy -CONFIG_USB_STORAGE=3Dm -CONFIG_USB_SERIAL=3Dm -CONFIG_USB_SERIAL_PL2303=3Dm -CONFIG_NEW_LEDS=3Dy -CONFIG_LEDS_CLASS=3Dy -CONFIG_LEDS_GPIO=3Dy -CONFIG_LEDS_TRIGGERS=3Dy -CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy -CONFIG_RTC_CLASS=3Dy -CONFIG_RTC_DRV_LOONGSON1=3Dy -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=3Dy -CONFIG_EXT2_FS_XATTR=3Dy -CONFIG_EXT2_FS_POSIX_ACL=3Dy -CONFIG_EXT2_FS_SECURITY=3Dy -CONFIG_EXT3_FS=3Dy -CONFIG_EXT3_FS_POSIX_ACL=3Dy -CONFIG_EXT3_FS_SECURITY=3Dy -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=3Dy -CONFIG_PROC_KCORE=3Dy -CONFIG_TMPFS=3Dy -CONFIG_TMPFS_POSIX_ACL=3Dy -CONFIG_UBIFS_FS=3Dy -CONFIG_UBIFS_FS_ADVANCED_COMPR=3Dy -CONFIG_UBIFS_ATIME_SUPPORT=3Dy -CONFIG_NFS_FS=3Dy -CONFIG_ROOT_NFS=3Dy -CONFIG_NLS_CODEPAGE_437=3Dm -CONFIG_NLS_ISO8859_1=3Dm -# CONFIG_CRYPTO_ECHAINIV is not set -# CONFIG_CRYPTO_HW is not set -CONFIG_DYNAMIC_DEBUG=3Dy -CONFIG_DEBUG_FS=3Dy -CONFIG_MAGIC_SYSRQ=3Dy -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -# CONFIG_EARLY_PRINTK is not set --=20 2.43.0