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Tue, 15 Jul 2025 09:03:43 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Himanshu Chauhan , Anup Patel , Xu Lu , Atish Patra , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= Subject: [PATCH v5 4/5] perf: RISC-V: add support for SSE event Date: Tue, 15 Jul 2025 16:02:32 +0000 Message-ID: <20250715160234.454848-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250715160234.454848-1-cleger@rivosinc.com> References: <20250715160234.454848-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In order to use SSE within PMU drivers, register a SSE handler for the local PMU event. Reuse the existing overflow IRQ handler and pass appropriate pt_regs. Add a config option RISCV_PMU_SSE to select event delivery via SSE events. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- drivers/perf/Kconfig | 10 +++++ drivers/perf/riscv_pmu.c | 19 +++++++++ drivers/perf/riscv_pmu_sbi.c | 71 +++++++++++++++++++++++++++++----- include/linux/perf/riscv_pmu.h | 3 ++ 4 files changed, 93 insertions(+), 10 deletions(-) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 278c929dc87a..3310076ca7b0 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -105,6 +105,16 @@ config RISCV_PMU_SBI full perf feature support i.e. counter overflow, privilege mode filtering, counter configuration. =20 +config RISCV_PMU_SSE + depends on RISCV_PMU && RISCV_SSE + bool "RISC-V PMU SSE events" + default n + help + Say y if you want to use SSE events to deliver PMU interrupts. This + provides a way to profile the kernel at any level by using NMI-like + SSE events. SSE events being really intrusive, this option allows + to select it only if needed. + config STARFIVE_STARLINK_PMU depends on ARCH_STARFIVE || COMPILE_TEST depends on 64BIT diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index 7644147d50b4..1eb28381b80f 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -254,6 +255,22 @@ void riscv_pmu_start(struct perf_event *event, int fla= gs) perf_event_update_userpage(event); } =20 +static void riscv_pmu_disable(struct pmu *pmu) +{ + struct riscv_pmu *rvpmu =3D to_riscv_pmu(pmu); + + if (rvpmu->sse_evt) + sse_event_disable_local(rvpmu->sse_evt); +} + +static void riscv_pmu_enable(struct pmu *pmu) +{ + struct riscv_pmu *rvpmu =3D to_riscv_pmu(pmu); + + if (rvpmu->sse_evt) + sse_event_enable_local(rvpmu->sse_evt); +} + static int riscv_pmu_add(struct perf_event *event, int flags) { struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); @@ -411,6 +428,8 @@ struct riscv_pmu *riscv_pmu_alloc(void) .event_mapped =3D riscv_pmu_event_mapped, .event_unmapped =3D riscv_pmu_event_unmapped, .event_idx =3D riscv_pmu_event_idx, + .pmu_enable =3D riscv_pmu_enable, + .pmu_disable =3D riscv_pmu_disable, .add =3D riscv_pmu_add, .del =3D riscv_pmu_del, .start =3D riscv_pmu_start, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 698de8ddf895..8c1ac7985df6 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -948,10 +949,10 @@ static void pmu_sbi_start_overflow_mask(struct riscv_= pmu *pmu, pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); } =20 -static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) +static irqreturn_t pmu_sbi_ovf_handler(struct cpu_hw_events *cpu_hw_evt, + struct pt_regs *regs, bool from_sse) { struct perf_sample_data data; - struct pt_regs *regs; struct hw_perf_event *hw_evt; union sbi_pmu_ctr_info *info; int lidx, hidx, fidx; @@ -959,7 +960,6 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) struct perf_event *event; u64 overflow; u64 overflowed_ctrs =3D 0; - struct cpu_hw_events *cpu_hw_evt =3D dev; u64 start_clock =3D sched_clock(); struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 @@ -969,13 +969,15 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) /* Firmware counter don't support overflow yet */ fidx =3D find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS); if (fidx =3D=3D RISCV_MAX_COUNTERS) { - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); + if (!from_sse) + csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); return IRQ_NONE; } =20 event =3D cpu_hw_evt->events[fidx]; if (!event) { - ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); + if (!from_sse) + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); return IRQ_NONE; } =20 @@ -990,16 +992,16 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) =20 /* * Overflow interrupt pending bit should only be cleared after stopping - * all the counters to avoid any race condition. + * all the counters to avoid any race condition. When using SSE, + * interrupt is cleared when stopping counters. */ - ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); + if (!from_sse) + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); =20 /* No overflow bit is set */ if (!overflow) return IRQ_NONE; =20 - regs =3D get_irq_regs(); - for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { struct perf_event *event =3D cpu_hw_evt->events[lidx]; =20 @@ -1055,6 +1057,51 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void= *dev) return IRQ_HANDLED; } =20 +static irqreturn_t pmu_sbi_ovf_irq_handler(int irq, void *dev) +{ + return pmu_sbi_ovf_handler(dev, get_irq_regs(), false); +} + +#ifdef CONFIG_RISCV_PMU_SSE +static int pmu_sbi_ovf_sse_handler(u32 evt, void *arg, struct pt_regs *reg= s) +{ + struct cpu_hw_events __percpu *hw_events =3D arg; + struct cpu_hw_events *hw_event =3D raw_cpu_ptr(hw_events); + + pmu_sbi_ovf_handler(hw_event, regs, true); + + return 0; +} + +static int pmu_sbi_setup_sse(struct riscv_pmu *pmu) +{ + int ret; + struct sse_event *evt; + struct cpu_hw_events __percpu *hw_events =3D pmu->hw_events; + + evt =3D sse_event_register(SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW, 0, + pmu_sbi_ovf_sse_handler, hw_events); + if (IS_ERR(evt)) + return PTR_ERR(evt); + + ret =3D sse_event_enable(evt); + if (ret) { + sse_event_unregister(evt); + return ret; + } + + pr_info("using SSE for PMU event delivery\n"); + pmu->sse_evt =3D evt; + + return ret; +} +#else +static int pmu_sbi_setup_sse(struct riscv_pmu *pmu) +{ + return -EOPNOTSUPP; +} +#endif + static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu =3D hlist_entry_safe(node, struct riscv_pmu, node); @@ -1105,6 +1152,10 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu,= struct platform_device *pde struct cpu_hw_events __percpu *hw_events =3D pmu->hw_events; struct irq_domain *domain =3D NULL; =20 + ret =3D pmu_sbi_setup_sse(pmu); + if (!ret) + return 0; + if (riscv_isa_extension_available(NULL, SSCOFPMF)) { riscv_pmu_irq_num =3D RV_IRQ_PMU; riscv_pmu_use_irq =3D true; @@ -1139,7 +1190,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, = struct platform_device *pde return -ENODEV; } =20 - ret =3D request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu= ", hw_events); + ret =3D request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_irq_handler, "riscv= -pmu", hw_events); if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); return ret; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 701974639ff2..d4a5c55fe077 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -28,6 +28,8 @@ =20 #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 =20 +struct sse_event; + struct cpu_hw_events { /* currently enabled events */ int n_events; @@ -54,6 +56,7 @@ struct riscv_pmu { char *name; =20 irqreturn_t (*handle_irq)(int irq_num, void *dev); + struct sse_event *sse_evt; =20 unsigned long cmask; u64 (*ctr_read)(struct perf_event *event); --=20 2.43.0