From nobody Tue Oct 7 02:01:56 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A46B52D63FD; Tue, 15 Jul 2025 09:21:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571293; cv=none; b=Y2k0Em3DMZknOVgGC9feANtX9SMLmRbN0bXk/JlTBlOrtuJAzJiNK5y59vdvvO9hg+OLb3utnux/NY7+FnSJEAATxO8tqUu5ZBTE0jZ5NQ3SrTlGtUYFMlRvFp1vKDcW8DYjicK0eypilIgzpFi+8GjX0aPdHcfsSplnyMXe4rU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571293; c=relaxed/simple; bh=Yhdrbsi3xuNdiYEULNrhlmxNwKvVco8Ee/2zWHgoN20=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BO4SVndgEhhVk+icfkAtXb34RbeDat9h61AZ++f3tAaN+zlayFKoVMpLltRidp5vs8x3tgEdK7Poj7UL8t6xeEaK6NvjqmOKZPl1NWlWGKRWuZPityXPQNfYGdryLTQV7Ci+nYd44RUiusCjwWgF6IH3ZKfIHbBKmnp2hb8DQHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nLjHAb9I; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nLjHAb9I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752571292; x=1784107292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Yhdrbsi3xuNdiYEULNrhlmxNwKvVco8Ee/2zWHgoN20=; b=nLjHAb9ISnMroBnAyNa7YXP9qvMP8UIoDZMpvIME1E76CiXsuKpyW/2L mG+9IVwezj9PKKHqhqO6/WtXtc1/Zu0xXcUZ9WQlSz5HX/k6pu7XEWLFN HeP8hXhyrCEL0onAHojuoYN5+//BgVgrBKyXOM1mvC3avRv5PNcMmbGsh eekEVFko+lNzzLAD0TDpMCJnSrNhW5bi47/3OC1o+cwFHAy+bCfrmJZA/ 3dX885WKEeqgwlcKjzw//7O8/5BPTNP5G5tPtJ5LSRmgVinPtJPhXXiJ7 2yrXKtjRbqvw3FvpXRRwR60TRRrYC2RkbjQ9H8dc9iGUAJskBVXA7UoGC g==; X-CSE-ConnectionGUID: JnJg2x9FQvuugYPxe2hAKg== X-CSE-MsgGUID: UNAKeIwsROSQqNutu0U+dA== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54003326" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54003326" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 02:21:31 -0700 X-CSE-ConnectionGUID: OK7oovUBQhCxcMhG+1povw== X-CSE-MsgGUID: lU6ChvMNQV68E7Vha6HFew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="188183684" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa001.fm.intel.com with ESMTP; 15 Jul 2025 02:21:25 -0700 From: Xiaoyao Li To: "Kirill A. Shutemov" , Dave Hansen , Sean Christopherson , Paolo Bonzini Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, Rick Edgecombe , Kai Huang , binbin.wu@linux.intel.com, yan.y.zhao@intel.com, reinette.chatre@intel.com, adrian.hunter@intel.com, tony.lindgren@intel.com, xiaoyao.li@intel.com Subject: [PATCH v3 1/4] x86/tdx: Fix the typo in TDX_ATTR_MIGRTABLE Date: Tue, 15 Jul 2025 17:13:09 +0800 Message-ID: <20250715091312.563773-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250715091312.563773-1-xiaoyao.li@intel.com> References: <20250715091312.563773-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TD scoped TDCS attributes are defined by bit positions. In the guest side of the TDX code, the 'tdx_attributes' string array holds pretty print names for these attributes, which are generated via macros and defines. Today these pretty print names are only used to print the attribute names to dmesg. Unfortunately there is a typo in the define for the migratable bit. Change the defines TDX_ATTR_MIGRTABLE* to TDX_ATTR_MIGRATABLE*. Update the sole user, the tdx_attributes array, to use the fixed name. Since these defines control the string printed to dmesg, the change is user visible. But the risk of breakage is almost zero since it is not exposed in any interface expected to be consumed programmatically. Fixes: 564ea84c8c14 ("x86/tdx: Dump attributes and TD_CTLS on boot") Reviewed-by: Kirill A. Shutemov Reviewed-by: Kai Huang Signed-off-by: Xiaoyao Li Acked-by: Sean Christopherson --- Changes in v3: - Use the rewritten changelog from Rick. Changes in v2: - Add the impact of the change in the commit message. (provided by Rick) --- arch/x86/coco/tdx/debug.c | 2 +- arch/x86/include/asm/shared/tdx.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/coco/tdx/debug.c b/arch/x86/coco/tdx/debug.c index cef847c8bb67..28990c2ab0a1 100644 --- a/arch/x86/coco/tdx/debug.c +++ b/arch/x86/coco/tdx/debug.c @@ -17,7 +17,7 @@ static __initdata const char *tdx_attributes[] =3D { DEF_TDX_ATTR_NAME(ICSSD), DEF_TDX_ATTR_NAME(LASS), DEF_TDX_ATTR_NAME(SEPT_VE_DISABLE), - DEF_TDX_ATTR_NAME(MIGRTABLE), + DEF_TDX_ATTR_NAME(MIGRATABLE), DEF_TDX_ATTR_NAME(PKS), DEF_TDX_ATTR_NAME(KL), DEF_TDX_ATTR_NAME(TPA), diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 8bc074c8d7c6..11f3cf30b1ac 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -35,8 +35,8 @@ #define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT) #define TDX_ATTR_SEPT_VE_DISABLE_BIT 28 #define TDX_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_ATTR_SEPT_VE_DISABLE_BIT) -#define TDX_ATTR_MIGRTABLE_BIT 29 -#define TDX_ATTR_MIGRTABLE BIT_ULL(TDX_ATTR_MIGRTABLE_BIT) +#define TDX_ATTR_MIGRATABLE_BIT 29 +#define TDX_ATTR_MIGRATABLE BIT_ULL(TDX_ATTR_MIGRATABLE_BIT) #define TDX_ATTR_PKS_BIT 30 #define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT) #define TDX_ATTR_KL_BIT 31 --=20 2.43.0 From nobody Tue Oct 7 02:01:56 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AC062D7810; Tue, 15 Jul 2025 09:21:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571297; cv=none; b=iq/nSY41MVqVTo2gO0Vg2ZXociE4HgPQuK/wmTwObQsinbO3nEkojgkH8OjQCZoRubmAFfZpjh6cY5pWrjIt1R0QmVImEWqpGxqeUf5uVJC35wMhhUg7iOFRNVC8wt75RvnojVKMGy9d3NyDc741S2OinHJD15y+JmwLv8eCNEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571297; c=relaxed/simple; bh=x092r1fSBa4wry6ULv5QvHdrP4+so9lToB70GqLJWdY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X/B71A+fBIeegKAltx3ymFisfhHCb8b+ANybAULrVP8P6qkw3ztIdnifhAcnUBlWZ1iXiWmra9wSuaDRQ3uw2ppMLNrC93vma4SWYn3byLEce6c1cJYsK1wDYk4CcdMmmOUuzqpycSSELbUdBIvmW74kCDeuxaLK4x55IsvONKA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nwGLhbNt; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nwGLhbNt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752571296; x=1784107296; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x092r1fSBa4wry6ULv5QvHdrP4+so9lToB70GqLJWdY=; b=nwGLhbNtBNfoF9GTT5h5kVhDt7WCI/+ZkT+5rywQWNUUF3yMYr2IdCg7 XUuLSq141RtWIPMUzEbXsNumEMDvEkHxQ+s64HhfyX4H/aUXzwa0b4+BR dihzQKvN76z5YqMLQqytqCwIUjFd5KJpFjHJ1e090N9bg8FpTMgJJFIFs 0dFfvs9QpVsT8OAfrZ5b4xEGKZdsZB1abWWBUahSL5Iwtc8a778/S8eLS p01Y8kUxEhhMf8aWSck8Yo0+MtsrSp041659/NxnKo+yV8fIeMcSw6xLh IoSMw7PgwgNfFb8mm/K2kyvxlSglP/OUjnoTvXfQ9OwFjlQ9/C/fF+gV+ w==; X-CSE-ConnectionGUID: AvrbvQnCQ6uymaH9Az09IA== X-CSE-MsgGUID: s7mlzyBuTs+ZBGRoEQEEpQ== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54003351" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54003351" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 02:21:36 -0700 X-CSE-ConnectionGUID: 19HcrPZkQyaUkFNFIdbYUA== X-CSE-MsgGUID: 8P4M9pqnQOmbtc9nqXq5vg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="188183701" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa001.fm.intel.com with ESMTP; 15 Jul 2025 02:21:31 -0700 From: Xiaoyao Li To: "Kirill A. Shutemov" , Dave Hansen , Sean Christopherson , Paolo Bonzini Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, Rick Edgecombe , Kai Huang , binbin.wu@linux.intel.com, yan.y.zhao@intel.com, reinette.chatre@intel.com, adrian.hunter@intel.com, tony.lindgren@intel.com, xiaoyao.li@intel.com Subject: [PATCH v3 2/4] KVM: TDX: Remove redundant definitions of TDX_TD_ATTR_* Date: Tue, 15 Jul 2025 17:13:10 +0800 Message-ID: <20250715091312.563773-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250715091312.563773-1-xiaoyao.li@intel.com> References: <20250715091312.563773-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are definitions of TD attributes bits inside asm/shared/tdx.h as TDX_ATTR_*. Remove KVM's definitions and use the ones in asm/shared/tdx.h Reviewed-by: Kirill A. Shutemov Reviewed-by: Kai Huang Signed-off-by: Xiaoyao Li Acked-by: Sean Christopherson Reviewed-by: Rick Edgecombe --- arch/x86/kvm/vmx/tdx.c | 4 ++-- arch/x86/kvm/vmx/tdx_arch.h | 6 ------ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index c539c2e6109f..efb7d589b672 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -62,7 +62,7 @@ void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass,= char *op, u32 field, pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, = val, err); } =20 -#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE) +#define KVM_SUPPORTED_TD_ATTRS (TDX_ATTR_SEPT_VE_DISABLE) =20 static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm) { @@ -700,7 +700,7 @@ int tdx_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.l1_tsc_scaling_ratio =3D kvm_tdx->tsc_multiplier; =20 vcpu->arch.guest_state_protected =3D - !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_TD_ATTR_DEBUG); + !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_ATTR_DEBUG); =20 if ((kvm_tdx->xfam & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTILE) vcpu->arch.xfd_no_write_intercept =3D true; diff --git a/arch/x86/kvm/vmx/tdx_arch.h b/arch/x86/kvm/vmx/tdx_arch.h index a30e880849e3..350143b9b145 100644 --- a/arch/x86/kvm/vmx/tdx_arch.h +++ b/arch/x86/kvm/vmx/tdx_arch.h @@ -75,12 +75,6 @@ struct tdx_cpuid_value { u32 edx; } __packed; =20 -#define TDX_TD_ATTR_DEBUG BIT_ULL(0) -#define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(28) -#define TDX_TD_ATTR_PKS BIT_ULL(30) -#define TDX_TD_ATTR_KL BIT_ULL(31) -#define TDX_TD_ATTR_PERFMON BIT_ULL(63) - #define TDX_EXT_EXIT_QUAL_TYPE_MASK GENMASK(3, 0) #define TDX_EXT_EXIT_QUAL_TYPE_PENDING_EPT_VIOLATION 6 /* --=20 2.43.0 From nobody Tue Oct 7 02:01:56 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71C2A2D63F7; Tue, 15 Jul 2025 09:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571303; cv=none; b=OTOBZQktcAtnzx7tQZsVycnTjOp3txk9rNgK8h94ZIDC/q2tFbgPYLE/2+10vi/I1F0Y+I1/ETqe9VqJFFKyibEq+NeqBeThcP3C8XcfTMTNaKO2Z9aM5ciFly0MNS2YEv0Hwv46DhMDJWpUXyFK4lraKRy2oMMPBta9Qrhwmmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571303; c=relaxed/simple; bh=pGVqlGqCP/o6RjK9s7ShTdEMqkimt6Dd+lPwwZHbtKQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JqJvzi2VTbyIzRmNCJCgoxjk60KsfFoVJDweRqqw7lztWS+bwZFlmYP5SJvF6GaVoF018pCT23ztC6aA9Effz95vEJ+o3vaggZ+fZyzXslXw7rzTz0NTeXA2SxvDb8Kdt9ULVg6VaVEQwzXfJfGGgu9XFRVTTblIPdIFP4JPkIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gxvT+8Ka; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gxvT+8Ka" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752571301; x=1784107301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pGVqlGqCP/o6RjK9s7ShTdEMqkimt6Dd+lPwwZHbtKQ=; b=gxvT+8KaLcaGOZmC4z1SuNwSwc3JJAZKI96Hs+WWaY+L5p7H3C6vxZqn NGfv/Sn7UJdlPV3Yp9WCwvAz+9pGOHf7ndZBj/CXoxtWSFAmUUPR5tSQ9 n1k9b5uy8Tt5sFYVY6v8MP7i8J4oJLEwCGSEkAoAXiklZKTcuhkgdMNBd yHGKd/LDccc+FRvSdJmEx5c1jSAXjTK3+NvQAYB+eY8XyEI5HSpiCngFb 0zPzps4KUkXRq7X0ydKdwLau0fq1ERzipUW7G29wQ7Gs52f62X0grHGMH NXLHanzqDg14o1j45nK8nrqHe/SiAXc6ZQIw4RZJaLhTxBCHroTQaTvnl A==; X-CSE-ConnectionGUID: YHWcrHUbRN63UpAyl9/AUQ== X-CSE-MsgGUID: 98fw8hxiQQiJ7UP4+NKlpg== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54003377" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54003377" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 02:21:41 -0700 X-CSE-ConnectionGUID: X/u3Zql4Rw6fRG5VAw2FBw== X-CSE-MsgGUID: tjXHMJCuQny68BqE2yF8yA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="188183716" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa001.fm.intel.com with ESMTP; 15 Jul 2025 02:21:36 -0700 From: Xiaoyao Li To: "Kirill A. Shutemov" , Dave Hansen , Sean Christopherson , Paolo Bonzini Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, Rick Edgecombe , Kai Huang , binbin.wu@linux.intel.com, yan.y.zhao@intel.com, reinette.chatre@intel.com, adrian.hunter@intel.com, tony.lindgren@intel.com, xiaoyao.li@intel.com Subject: [PATCH v3 3/4] x86/tdx: Rename TDX_ATTR_* to TDX_TD_ATTR_* Date: Tue, 15 Jul 2025 17:13:11 +0800 Message-ID: <20250715091312.563773-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250715091312.563773-1-xiaoyao.li@intel.com> References: <20250715091312.563773-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The macros TDX_ATTR_* and DEF_TDX_ATTR_* are related to TD attributes, which are TD-scope attributes. Naming them as TDX_ATTR_* can be somewhat confusing and might mislead people into thinking they are TDX global things. Rename TDX_ATTR_* to TDX_TD_ATTR_* to explicitly clarify they are TD-scope things. Suggested-by: Rick Edgecombe Signed-off-by: Xiaoyao Li Acked-by: Sean Christopherson Reviewed-by: Binbin Wu Reviewed-by: Kiryl Shutsemau Reviewed-by: Rick Edgecombe --- arch/x86/coco/tdx/debug.c | 26 ++++++++-------- arch/x86/coco/tdx/tdx.c | 8 ++--- arch/x86/include/asm/shared/tdx.h | 50 +++++++++++++++---------------- arch/x86/kvm/vmx/tdx.c | 4 +-- 4 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/x86/coco/tdx/debug.c b/arch/x86/coco/tdx/debug.c index 28990c2ab0a1..8e477db4ce0a 100644 --- a/arch/x86/coco/tdx/debug.c +++ b/arch/x86/coco/tdx/debug.c @@ -7,21 +7,21 @@ #include #include =20 -#define DEF_TDX_ATTR_NAME(_name) [TDX_ATTR_##_name##_BIT] =3D __stringify(= _name) +#define DEF_TDX_TD_ATTR_NAME(_name) [TDX_TD_ATTR_##_name##_BIT] =3D __stri= ngify(_name) =20 static __initdata const char *tdx_attributes[] =3D { - DEF_TDX_ATTR_NAME(DEBUG), - DEF_TDX_ATTR_NAME(HGS_PLUS_PROF), - DEF_TDX_ATTR_NAME(PERF_PROF), - DEF_TDX_ATTR_NAME(PMT_PROF), - DEF_TDX_ATTR_NAME(ICSSD), - DEF_TDX_ATTR_NAME(LASS), - DEF_TDX_ATTR_NAME(SEPT_VE_DISABLE), - DEF_TDX_ATTR_NAME(MIGRATABLE), - DEF_TDX_ATTR_NAME(PKS), - DEF_TDX_ATTR_NAME(KL), - DEF_TDX_ATTR_NAME(TPA), - DEF_TDX_ATTR_NAME(PERFMON), + DEF_TDX_TD_ATTR_NAME(DEBUG), + DEF_TDX_TD_ATTR_NAME(HGS_PLUS_PROF), + DEF_TDX_TD_ATTR_NAME(PERF_PROF), + DEF_TDX_TD_ATTR_NAME(PMT_PROF), + DEF_TDX_TD_ATTR_NAME(ICSSD), + DEF_TDX_TD_ATTR_NAME(LASS), + DEF_TDX_TD_ATTR_NAME(SEPT_VE_DISABLE), + DEF_TDX_TD_ATTR_NAME(MIGRATABLE), + DEF_TDX_TD_ATTR_NAME(PKS), + DEF_TDX_TD_ATTR_NAME(KL), + DEF_TDX_TD_ATTR_NAME(TPA), + DEF_TDX_TD_ATTR_NAME(PERFMON), }; =20 #define DEF_TD_CTLS_NAME(_name) [TD_CTLS_##_name##_BIT] =3D __stringify(_n= ame) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 7b2833705d47..186915a17c50 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -238,14 +238,14 @@ static void __noreturn tdx_panic(const char *msg) * * TDX 1.0 does not allow the guest to disable SEPT #VE on its own. The VMM * controls if the guest will receive such #VE with TD attribute - * TDX_ATTR_SEPT_VE_DISABLE. + * TDX_TD_ATTR_SEPT_VE_DISABLE. * * Newer TDX modules allow the guest to control if it wants to receive SEPT * violation #VEs. * * Check if the feature is available and disable SEPT #VE if possible. * - * If the TD is allowed to disable/enable SEPT #VEs, the TDX_ATTR_SEPT_VE_= DISABLE + * If the TD is allowed to disable/enable SEPT #VEs, the TDX_TD_ATTR_SEPT_= VE_DISABLE * attribute is no longer reliable. It reflects the initial state of the * control for the TD, but it will not be updated if someone (e.g. bootloa= der) * changes it before the kernel starts. Kernel must check TDCS_TD_CTLS bit= to @@ -254,14 +254,14 @@ static void __noreturn tdx_panic(const char *msg) static void disable_sept_ve(u64 td_attr) { const char *msg =3D "TD misconfiguration: SEPT #VE has to be disabled"; - bool debug =3D td_attr & TDX_ATTR_DEBUG; + bool debug =3D td_attr & TDX_TD_ATTR_DEBUG; u64 config, controls; =20 /* Is this TD allowed to disable SEPT #VE */ tdg_vm_rd(TDCS_CONFIG_FLAGS, &config); if (!(config & TDCS_CONFIG_FLEXIBLE_PENDING_VE)) { /* No SEPT #VE controls for the guest: check the attribute */ - if (td_attr & TDX_ATTR_SEPT_VE_DISABLE) + if (td_attr & TDX_TD_ATTR_SEPT_VE_DISABLE) return; =20 /* Relax SEPT_VE_DISABLE check for debug TD for backtraces */ diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 11f3cf30b1ac..049638e3da74 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -20,31 +20,31 @@ #define TDG_VM_RD 7 #define TDG_VM_WR 8 =20 -/* TDX attributes */ -#define TDX_ATTR_DEBUG_BIT 0 -#define TDX_ATTR_DEBUG BIT_ULL(TDX_ATTR_DEBUG_BIT) -#define TDX_ATTR_HGS_PLUS_PROF_BIT 4 -#define TDX_ATTR_HGS_PLUS_PROF BIT_ULL(TDX_ATTR_HGS_PLUS_PROF_BIT) -#define TDX_ATTR_PERF_PROF_BIT 5 -#define TDX_ATTR_PERF_PROF BIT_ULL(TDX_ATTR_PERF_PROF_BIT) -#define TDX_ATTR_PMT_PROF_BIT 6 -#define TDX_ATTR_PMT_PROF BIT_ULL(TDX_ATTR_PMT_PROF_BIT) -#define TDX_ATTR_ICSSD_BIT 16 -#define TDX_ATTR_ICSSD BIT_ULL(TDX_ATTR_ICSSD_BIT) -#define TDX_ATTR_LASS_BIT 27 -#define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT) -#define TDX_ATTR_SEPT_VE_DISABLE_BIT 28 -#define TDX_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_ATTR_SEPT_VE_DISABLE_BIT) -#define TDX_ATTR_MIGRATABLE_BIT 29 -#define TDX_ATTR_MIGRATABLE BIT_ULL(TDX_ATTR_MIGRATABLE_BIT) -#define TDX_ATTR_PKS_BIT 30 -#define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT) -#define TDX_ATTR_KL_BIT 31 -#define TDX_ATTR_KL BIT_ULL(TDX_ATTR_KL_BIT) -#define TDX_ATTR_TPA_BIT 62 -#define TDX_ATTR_TPA BIT_ULL(TDX_ATTR_TPA_BIT) -#define TDX_ATTR_PERFMON_BIT 63 -#define TDX_ATTR_PERFMON BIT_ULL(TDX_ATTR_PERFMON_BIT) +/* TDX TD attributes */ +#define TDX_TD_ATTR_DEBUG_BIT 0 +#define TDX_TD_ATTR_DEBUG BIT_ULL(TDX_TD_ATTR_DEBUG_BIT) +#define TDX_TD_ATTR_HGS_PLUS_PROF_BIT 4 +#define TDX_TD_ATTR_HGS_PLUS_PROF BIT_ULL(TDX_TD_ATTR_HGS_PLUS_PROF_BIT) +#define TDX_TD_ATTR_PERF_PROF_BIT 5 +#define TDX_TD_ATTR_PERF_PROF BIT_ULL(TDX_TD_ATTR_PERF_PROF_BIT) +#define TDX_TD_ATTR_PMT_PROF_BIT 6 +#define TDX_TD_ATTR_PMT_PROF BIT_ULL(TDX_TD_ATTR_PMT_PROF_BIT) +#define TDX_TD_ATTR_ICSSD_BIT 16 +#define TDX_TD_ATTR_ICSSD BIT_ULL(TDX_TD_ATTR_ICSSD_BIT) +#define TDX_TD_ATTR_LASS_BIT 27 +#define TDX_TD_ATTR_LASS BIT_ULL(TDX_TD_ATTR_LASS_BIT) +#define TDX_TD_ATTR_SEPT_VE_DISABLE_BIT 28 +#define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_TD_ATTR_SEPT_VE_DISABLE_BI= T) +#define TDX_TD_ATTR_MIGRATABLE_BIT 29 +#define TDX_TD_ATTR_MIGRATABLE BIT_ULL(TDX_TD_ATTR_MIGRATABLE_BIT) +#define TDX_TD_ATTR_PKS_BIT 30 +#define TDX_TD_ATTR_PKS BIT_ULL(TDX_TD_ATTR_PKS_BIT) +#define TDX_TD_ATTR_KL_BIT 31 +#define TDX_TD_ATTR_KL BIT_ULL(TDX_TD_ATTR_KL_BIT) +#define TDX_TD_ATTR_TPA_BIT 62 +#define TDX_TD_ATTR_TPA BIT_ULL(TDX_TD_ATTR_TPA_BIT) +#define TDX_TD_ATTR_PERFMON_BIT 63 +#define TDX_TD_ATTR_PERFMON BIT_ULL(TDX_TD_ATTR_PERFMON_BIT) =20 /* TDX TD-Scope Metadata. To be used by TDG.VM.WR and TDG.VM.RD */ #define TDCS_CONFIG_FLAGS 0x1110000300000016 diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index efb7d589b672..c539c2e6109f 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -62,7 +62,7 @@ void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass,= char *op, u32 field, pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, = val, err); } =20 -#define KVM_SUPPORTED_TD_ATTRS (TDX_ATTR_SEPT_VE_DISABLE) +#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE) =20 static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm) { @@ -700,7 +700,7 @@ int tdx_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.l1_tsc_scaling_ratio =3D kvm_tdx->tsc_multiplier; =20 vcpu->arch.guest_state_protected =3D - !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_ATTR_DEBUG); + !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_TD_ATTR_DEBUG); =20 if ((kvm_tdx->xfam & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTILE) vcpu->arch.xfd_no_write_intercept =3D true; --=20 2.43.0 From nobody Tue Oct 7 02:01:56 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DED0E2D5A08; Tue, 15 Jul 2025 09:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571307; cv=none; b=XLB9N2oPZ42KJ2UEfu9dt5fbvUrTOViSYQH4W1QvY9SAfGfx3xpgqXkGTWIE7F0U5gmrQSVHmrmP9c6SSb6XhsqGSzFM5DUKB9UEjlxXADaa3/hzGuWPdxwUfs+7uIDhwyitliNbGOfkmrbeOuPSH+5BMn5p9fBcYzrdxN/s0bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752571307; c=relaxed/simple; bh=AJZCa/zxixHSRjGU574C3rCz/DtBj23gZzVQ/NXvAG0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y1ZhBB0lZbCHUlyXySqROcPq6vOeGLXPZSUWO+OkZMN6EpSbmn8cLgs592S70aDYoMFqLoEUz1YubkpBh9LV2N1S5680bjSyq5eL2mxwiXlSvENpwo+sGJPm7oSv9cbHG563MVrfw9m5AHXRo9QPUuPcNXl++TsPWhGEfqAnLFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FUMuw6e0; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FUMuw6e0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752571306; x=1784107306; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AJZCa/zxixHSRjGU574C3rCz/DtBj23gZzVQ/NXvAG0=; b=FUMuw6e04Fg+8Of2nFdFOSYuRQOCIIvZOIjs+lja7QZYVCt/SgTHvrU5 XnAfrPB+Zd+CS/ETnYQQK4yLNLRhHlgbhtwicyY9Gcm3yBB/6Yt9015m/ wwrC2S2CK434XbEiLpDzeBUaLlfzoJyAJrFfaAf/jX0wON6WVI6FdBGDG LzOO4VNBSt1Fysp4gWAZpNTRkuhqgDZxfk1hZC7UwJN/XRhwLNPvvm+R9 IwO81/Yn9RuOnwFOVGO8fjjMbDlUX5bs2wN6MeUarJPToWU2sJoZMIO0M rottzKkAjErNgCxm5OAS9teVLoZn3stdzocm/ua9cuqhpLPIRASMEpdiK Q==; X-CSE-ConnectionGUID: ZA5kOMQ1QEegenl2jL61UQ== X-CSE-MsgGUID: BYzTS07aThOHkxg0zQA/5A== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54003398" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54003398" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 02:21:45 -0700 X-CSE-ConnectionGUID: 9psXVbHbSkKipD84/pTxvw== X-CSE-MsgGUID: T9bCbQFLRCatMEt6RJ4j/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="188183753" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa001.fm.intel.com with ESMTP; 15 Jul 2025 02:21:41 -0700 From: Xiaoyao Li To: "Kirill A. Shutemov" , Dave Hansen , Sean Christopherson , Paolo Bonzini Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, Rick Edgecombe , Kai Huang , binbin.wu@linux.intel.com, yan.y.zhao@intel.com, reinette.chatre@intel.com, adrian.hunter@intel.com, tony.lindgren@intel.com, xiaoyao.li@intel.com Subject: [PATCH v3 4/4] KVM: TDX: Rename KVM_SUPPORTED_TD_ATTRS to KVM_SUPPORTED_TDX_TD_ATTRS Date: Tue, 15 Jul 2025 17:13:12 +0800 Message-ID: <20250715091312.563773-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250715091312.563773-1-xiaoyao.li@intel.com> References: <20250715091312.563773-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename KVM_SUPPORTED_TD_ATTRS to KVM_SUPPORTED_TDX_TD_ATTRS to include "TDX" in the name, making it clear that it pertains to TDX. Reviewed-by: Rick Edgecombe Suggested-by: Sean Christopherson Signed-off-by: Xiaoyao Li Acked-by: Sean Christopherson Reviewed-by: Kiryl Shutsemau --- arch/x86/kvm/vmx/tdx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index c539c2e6109f..9473610d32e6 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -62,7 +62,7 @@ void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass,= char *op, u32 field, pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, = val, err); } =20 -#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE) +#define KVM_SUPPORTED_TDX_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE) =20 static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm) { @@ -76,7 +76,7 @@ static __always_inline struct vcpu_tdx *to_tdx(struct kvm= _vcpu *vcpu) =20 static u64 tdx_get_supported_attrs(const struct tdx_sys_info_td_conf *td_c= onf) { - u64 val =3D KVM_SUPPORTED_TD_ATTRS; + u64 val =3D KVM_SUPPORTED_TDX_TD_ATTRS; =20 if ((val & td_conf->attributes_fixed1) !=3D td_conf->attributes_fixed1) return 0; --=20 2.43.0