From nobody Tue Oct 7 05:27:25 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE0C2D3749; Tue, 15 Jul 2025 03:43:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551016; cv=none; b=RoWywifxG7Q3iyhAJ04mjp3Nwt7R49FRID1dlGebIQBPukGejk0uYyiM/Ol3aDTZ9wEaX9aPsMB6NQxRs/pnt0IRQRMh/gZSYhBKMDFajroUfuVt9GjeAQUNiQemvMrQ8/2QF8e2XC8jSrUGADNO74w4WpsboTP1tSFHC0YBfwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551016; c=relaxed/simple; bh=mgc55NIMPiK4hx2qg381kbrLekpEb+TAYxut3JZjhho=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q/1HN6rbREr/Rj2zC0ByUyaPfBQrlewJPcaH3GfHXv4aFdR4ts9TPw4WuHfprzxrmigEAB4wN0xep7zJ+Bm5RldelBegfVtTMbXqGRmZKuDlj5j5mTVY9euK+HOqKUTMSbIhhI6FRXWVxDYRq5CqS1QmoyqSrjWLKrbHZQKvOuQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Date: Tue, 15 Jul 2025 11:43:14 +0800 Message-ID: <20250715034320.2553837-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe PERST# group to support for PCIe RC. Signed-off-by: Jacky Chou --- .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinct= rl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.= yaml index 80974c46f3ef..5d7fbb1c72b7 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -254,6 +254,7 @@ additionalProperties: - WDTRST2 - WDTRST3 - WDTRST4 + - PCIERC1 =20 groups: enum: @@ -497,6 +498,7 @@ additionalProperties: - WDTRST2 - WDTRST3 - WDTRST4 + - PCIERC1 =20 pins: true bias-disable: true --=20 2.43.0