From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C09892D12E9; Tue, 15 Jul 2025 03:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551008; cv=none; b=SLIdB1EYI1uxwJJqTKeXez6p1Ht934lSz4ENcvlXl8JQmxHaYkf+3Nn8ZtZNzDfzZjicXCQyW2OWIvTxpcycSHN/xOIVrlbRGn6nIbZvlfSsAQhQs1HLnhmRx8vLNvHBRKaQVvE3F3+dPT2d5RFLHlyVG7QGwXIAZUlZQIZYiOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551008; c=relaxed/simple; bh=y2DhT8R0ne8NBgP2oAmQXnxUXIXvVpOb73za3zmK/uI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dOiWuPKtva4xpSazr1EEbnikz0E5Qcz9NkbjcJsr+UcHrf0gLqyJeUCwxKguUchDl/xLCTfZpYGQsqAM/iFIJbQlfl5cROnYRn6z+WEXA8GveVTR87JX1eQJK7uixoxnWl0c7UUVOLZYUJcjSvKrL+yWR8CVxejO8K3MXbh/95g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:20 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:20 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Date: Tue, 15 Jul 2025 11:43:11 +0800 Message-ID: <20250715034320.2553837-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the ASPEED PCIe configuration syscon block. This shared register space is used by multiple PCIe-related devices to coordinate and manage common PCIe settings. The binding describes the required compatible strings and register space for the configuration node. Signed-off-by: Jacky Chou --- .../bindings/soc/aspeed/aspeed,pcie-cfg.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,pci= e-cfg.yaml diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.y= aml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml new file mode 100644 index 000000000000..6b282f06b914 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/aspeed/aspeed,pcie-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe Configuration + +maintainers: + - Jacky Chou + +description: | + The ASPEED PCIe configuration syscon block provides a set of registers s= hared + by multiple PCIe-related devices within the SoC. This node represents the + common configuration space that allows these devices to coordinate and m= anage + shared PCIe settings, including address mapping, control, and status + registers. The syscon interface enables for various PCIe devices to acce= ss + and modify these shared registers in a consistent and centralized manner. + +properties: + compatible: + items: + - enum: + - aspeed,pcie-cfg + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@1e770000 { + compatible =3D "aspeed,pcie-cfg", "syscon"; + reg =3D <0x1e770000 0x80>; + }; --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE7BF2D1F4E; Tue, 15 Jul 2025 03:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551012; cv=none; b=opvtKtHjS8yq2ugagNNDlKOf0kQr3jA94b5EBOBG+Sr0CE160p8XgjbRNklDVuAwRgcvnmwoG27t+0rWIHoFJEQH3r3f6ZWcsczklkk5eOViCvK1zQHyLntb+k1rzwG2gIvFS+rRxVGo6nzGVyLjNrvvsJpWNtG2VRCIsQVbZJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551012; c=relaxed/simple; bh=fdg1A0Kys3/8bLCqJkQ3l70v3ZlIvIrbrKlo1cOBH6U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TKMxcOSAMV2CP88CM77eBXxWMNthRWywDMOQc3YCnvXCuZ4pw9PnTSpOzSXOffGSX4ggL6oC3wNiQYQxymUZ6jr2Zx1sGohxvNqECLCVh2Knr1KDkHywcZppoXWU7JgZQiJaZ4q9hC2/9dc3B64D26AR/jOM++6WIeOv6y2ETKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:20 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:20 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support Date: Tue, 15 Jul 2025 11:43:12 +0800 Message-ID: <20250715034320.2553837-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This PHY is used by many modules. In our design, our PCIe has RC and EP funcitons. On the different function, each driver will use configure and get some information from the PHY interface to do somting that it wants to. Getting link status, setting syscon credits and so on. Therefore, define it as syscon for all modules. Signed-off-by: Jacky Chou --- .../bindings/soc/aspeed/aspeed,pcie-phy.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,pci= e-phy.yaml diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.y= aml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml new file mode 100644 index 000000000000..5fa585d63ca6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/aspeed/aspeed,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe PHY + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe PHY provides the physical layer interface for PCIe + controllers in the SoC. This node represents the register block for the = PCIe + PHY, which is typically accessed by PCIe Root Complex or Endpoint drivers + via syscon. It is used to configure and get the status of the PCIe PHY + hardware, including power management, link training, and other PHY-speci= fic + operations. + +properties: + compatible: + items: + - enum: + - aspeed,pcie-phy + - const: syscon + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@1e6ed200 { + compatible =3D "aspeed,pcie-phy", "syscon"; + reg =3D <0x1e6ed200 0x100>; + }; --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B46B12D3229; Tue, 15 Jul 2025 03:43:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551014; cv=none; b=cRSeIOW4bueA2guJhtkaHZ+pQN7lX3iDQxq2AjeIV/CiNvoi9WAfbvkJ7oB4HPJ+6GwzyP4lKHDmf0c9/rRBinU0+00LcG4jt8bS1oBXGvjLDRRFkPTOJ3aL0xvpwtOAnSVoR/vWr2m8WSkVmA5W3o6+7VCMg+GtExixBwHTClc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551014; c=relaxed/simple; bh=o9A8tpjLNA+7hV3ddUrRPAxEjqJVFGyMhdNtQnuVihU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EdfdG8ySoQQC5fKG4ayF7CWiDxSgMTrZSd9kV7CrnY/j6ZPk4qEizyzmLsgwNDmSGGgk46LhbsROQRF7AUVotZ3NfZkIGkcNj5Evdx9Q9xVguSOu8noWNKr9CrKAOh7pO26cJ/aqfd9ZgY0yYPzBCjAv1j0ftXjc2sIoBfuoaw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 03/10] dt-bindings: PCI: Add ASPEED PCIe RC support Date: Tue, 15 Jul 2025 11:43:13 +0800 Message-ID: <20250715034320.2553837-4-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This binding describes the required and optional properties for configuring the PCIe RC node, including support for syscon phandles, MSI, clocks, resets, and interrupt mapping. The schema enforces strict property validation and provides a comprehensive example for reference. Signed-off-by: Jacky Chou --- .../bindings/pci/aspeed,ast2600-pcie.yaml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/aspeed,ast2600-pc= ie.yaml diff --git a/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml= b/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml new file mode 100644 index 000000000000..6fb6cf59c230 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe Root Complex Controller + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe Root Complex controller provides PCI Express Root Complex + functionality for ASPEED SoCs, such as the AST2600 and AST2700. + This controller enables connectivity to PCIe endpoint devices, supporting + memory and I/O windows, MSI and legacy interrupts, and integration with + the SoC's clock, reset, and pinctrl subsystems. + +properties: + compatible: + enum: + - aspeed,ast2600-pcie + - aspeed,ast2700-pcie + + reg: + maxItems: 1 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + maxItems: 1 + description: IntX and MSI interrupt + + resets: + items: + - description: PCIe controller reset + + reset-names: + items: + - const: h2x + + msi-parent: true + + aspeed,ahbc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the ASPEED AHB Controller (AHBC) syscon node. + This reference is used by the PCIe controller to access + system-level configuration registers related to the AHB bus. + To enable AHB access for the PCIe controller. + + aspeed,pciecfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the ASPEED PCIe configuration syscon node. + This reference allows the PCIe controller to access + SoC-specific PCIe configuration registers. There are the others + functions such PCIe RC and PCIe EP will use this common register + to configure the SoC interfaces. + + aspeed,pciephy: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the ASPEED PCIe PHY syscon node. + This property provides access to the PCIe PHY control + registers required for link initialization and management. + The other functions such PCIe RC and PCIe EP will use this + common register to configure the PHY interfaces and get some + information from the PHY. + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interru= pts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +allOf: + - $ref: /schemas/pci/pci-bus-common.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - if: + properties: + compatible: + contains: + const: aspeed,ast2600-pcie + then: + required: + - aspeed,ahbc + else: + properties: + aspeed,ahbc: false + +required: + - reg + - interrupts + - bus-range + - ranges + - resets + - reset-names + - msi-parent + - msi-controller + - aspeed,pciecfg + - interrupt-map-mask + - interrupt-map + - interrupt-controller + +unevaluatedProperties: false + +patternProperties: + "^pcie@[0-9a-f,]+$": + type: object + properties: + resets: + items: + - description: PCIe PERST + reset-names: + items: + - const: perst + clocks: + maxItems: 1 + description: PCIe BUS clock + required: + - resets + - reset-names + - clocks + - aspeed,pciephy + +examples: + - | + #include + #include + + apb { + #address-cells =3D <1>; + #size-cells =3D <1>; + + pcie0: pcie@1e7700c0 { + compatible =3D "aspeed,ast2600-pcie"; + device_type =3D "pci"; + reg =3D <0x1e7700c0 0x40>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + bus-range =3D <0x80 0xff>; + + ranges =3D <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; + + resets =3D <&syscon ASPEED_RESET_H2X>; + reset-names =3D "h2x"; + + #interrupt-cells =3D <1>; + msi-parent =3D <&pcie0>; + msi-controller; + + aspeed,ahbc =3D <&ahbc>; + aspeed,pciecfg =3D <&pcie_cfg>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + pcie@8,0 { + reg =3D <0x804000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + resets =3D <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names =3D "perst"; + clocks =3D <&syscon ASPEED_CLK_GATE_BCLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcierc1_default>; + aspeed,pciephy =3D <&pcie_phy1>; + ranges; + }; + }; + }; --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE0C2D3749; Tue, 15 Jul 2025 03:43:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551016; cv=none; b=RoWywifxG7Q3iyhAJ04mjp3Nwt7R49FRID1dlGebIQBPukGejk0uYyiM/Ol3aDTZ9wEaX9aPsMB6NQxRs/pnt0IRQRMh/gZSYhBKMDFajroUfuVt9GjeAQUNiQemvMrQ8/2QF8e2XC8jSrUGADNO74w4WpsboTP1tSFHC0YBfwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Date: Tue, 15 Jul 2025 11:43:14 +0800 Message-ID: <20250715034320.2553837-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe PERST# group to support for PCIe RC. Signed-off-by: Jacky Chou --- .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinct= rl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.= yaml index 80974c46f3ef..5d7fbb1c72b7 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -254,6 +254,7 @@ additionalProperties: - WDTRST2 - WDTRST3 - WDTRST4 + - PCIERC1 =20 groups: enum: @@ -497,6 +498,7 @@ additionalProperties: - WDTRST2 - WDTRST3 - WDTRST4 + - PCIERC1 =20 pins: true bias-disable: true --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C867C2D3A91; Tue, 15 Jul 2025 03:43:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551018; cv=none; b=bJ7CECHTs/c5sP3SQNz+U+ElyS0b9vxjbPq/kBrRDQcGyTewkhmtovVKDPRPNLTqqspA2zptrPIXpeDUatmaiquyJR1+Wc5JtkLFbF6BzZgiU8VLIk2LDuQy1XximtBcU2Q5rYeljlPP0pZg9aDtTRa4kjoUGnwzAoIX4DU8/oA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551018; c=relaxed/simple; bh=RqjotwS+RxLBGQqfKYO247rq44b0pwn5qtigHjVvh8k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ru8gXMv/mHRnXJ3vctzhVYHkfYM+wW0Q/cBe758Ig2IxqDVtRAmd7UDj1a6LnGa3Q12ULbVPHzUuMJ++oaz0Z4ZjD5FZax0uLeBXCaiWmYrmPTAlcvPQrbgoPet1sEA6IRLI8MVQ0VrwAD3d7BtxYILGqy6rMsSeVhR8EtbrmFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Date: Tue, 15 Jul 2025 11:43:15 +0800 Message-ID: <20250715034320.2553837-6-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinctrl support for PCIe RC PERST#. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boo= t/dts/aspeed/aspeed-g6-pinctrl.dtsi index 289668f051eb..ea879f086c25 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -2,6 +2,11 @@ // Copyright 2019 IBM Corp. =20 &pinctrl { + pinctrl_pcierc1_default: pcierc1-default { + function =3D "PCIERC1"; + groups =3D "PCIERC1"; + }; + pinctrl_adc0_default: adc0_default { function =3D "ADC0"; groups =3D "ADC0"; --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890152D46C8; Tue, 15 Jul 2025 03:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551020; cv=none; b=KrzvPeDR4RgGs6WB+YtcfkvVCJJYrepuwFiYBv0C7tGv4x3bgtkp0ZhufOf84riaSuB3pQjAJzKA7H7CDW9gwKa/lpBeAyKKOtLbiHVOjqlju/YKOp2hptGEiaJSfJSDgVNCZRvFQ7aCyQuSCZGcAB13gNb2CnsdF07E0Vi0Msg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551020; c=relaxed/simple; bh=hjViZpXEUkSxf617dnE/GzfBvxIbI8+B9htFKuVtR24=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pNwI8knqKbzyFRUkT4tvmV92B0aafln4By7Jg4mlnvqRmCxRaZTU5940IVNAPbZn1TXLLg+EDGvjFF+nEIxsGBZO8aaRaD4kDeoHA7QoeCvGj7VVeEqWDqlDfaugYxL/X0JU3rCw0uBbmOUUcgLWerNhiMzP2Mq4P0WRz+g1V8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Date: Tue, 15 Jul 2025 11:43:16 +0800 Message-ID: <20250715034320.2553837-7-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2600 has one PCIe RC, and add the relative configure regmap. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/as= peed/aspeed-g6.dtsi index 8ed715bd53aa..ed99780b6860 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -379,6 +379,67 @@ rng: hwrng@1e6e2524 { quality =3D <100>; }; =20 + pcie_phy1: syscon@1e6ed200 { + compatible =3D "aspeed,pcie-phy", "syscon"; + reg =3D <0x1e6ed200 0x100>; + }; + + pcie_cfg: syscon@1e770000 { + compatible =3D "aspeed,pcie-cfg", "syscon"; + reg =3D <0x1e770000 0x80>; + }; + + pcie0: pcie@1e7700c0 { + compatible =3D "aspeed,ast2600-pcie"; + device_type =3D "pci"; + reg =3D <0x1e7700c0 0x40>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + bus-range =3D <0x80 0xff>; + + ranges =3D <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; + + status =3D "disabled"; + + resets =3D <&syscon ASPEED_RESET_H2X>; + reset-names =3D "h2x"; + + #interrupt-cells =3D <1>; + msi-parent =3D <&pcie0>; + msi-controller; + + aspeed,ahbc =3D <&ahbc>; + aspeed,pciecfg =3D <&pcie_cfg>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + pcie@8,0 { + reg =3D <0x804000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + resets =3D <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names =3D "perst"; + clocks =3D <&syscon ASPEED_CLK_GATE_BCLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcierc1_default>; + aspeed,pciephy =3D <&pcie_phy1>; + ranges; + }; + }; + gfx: display@1e6e6000 { compatible =3D "aspeed,ast2600-gfx", "syscon"; reg =3D <0x1e6e6000 0x1000>; --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D87E2D4B5F; Tue, 15 Jul 2025 03:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551022; cv=none; b=FQeSg1B6aQjnbfduKzyKDVFiHGrqMvsHJaR4QCynBJb13UpvOQqb0tYSoOTgSRwxtHojw+GEOfEuPioOICz/PbEF6WSIKPb8vbMiQFnMuQXOo8q7s56I1gh6l9jHmgYz7a0gGmTrcdboCW0iUe/1UYHxFmA7WVJX1POR4F+49uw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551022; c=relaxed/simple; bh=0DkfuTwKKA84kc4r3PvUw4eOW7Btqxbf9v4apXk9BvY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OfBcr2dAFaPCc5dR05QdnVq9FhJNYd/AE0yLu2RnDzLnVFPiBU36q2K1OTeu1eKOicp7Le2DW9rUwpEUg06prgLLqLXmEv/DhGb3YMNlZve5qF2YJMIkANXqivdur+fGIF7/5+FY14t6JSgYU28IhrOHGHOPGyhKGlbDT4M9d/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Date: Tue, 15 Jul 2025 11:43:17 +0800 Message-ID: <20250715034320.2553837-8-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCIe RC PERST uses SSPRST# as PERST# and enable this pin to output. Signed-off-by: Jacky Chou --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/a= speed/pinctrl-aspeed-g6.c index 5a7cd0a88687..c751703acdb9 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -17,6 +17,7 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" =20 +#define SCU040 0x040 /* Reset Control Set 1 */ #define SCU400 0x400 /* Multi-function Pin Control #1 */ #define SCU404 0x404 /* Multi-function Pin Control #2 */ #define SCU40C 0x40C /* Multi-function Pin Control #3 */ @@ -52,7 +53,7 @@ #define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */ #define SCUC20 0xC20 /* PCIE configuration Setting Control */ =20 -#define ASPEED_G6_NR_PINS 256 +#define ASPEED_G6_NR_PINS 258 =20 #define M24 0 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); @@ -1636,6 +1637,12 @@ FUNC_DECL_1(USB11BHID, USBB); FUNC_DECL_1(USB2BD, USBB); FUNC_DECL_1(USB2BH, USBB); =20 +#define D7 257 +SIG_EXPR_LIST_DECL_SESG(D7, RCRST, PCIERC1, SIG_DESC_SET(SCU040, 19), + SIG_DESC_SET(SCU500, 24)); +PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, RCRST)); +FUNC_GROUP_DECL(PCIERC1, D7); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ =20 static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] =3D { @@ -1806,6 +1813,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_= G6_NR_PINS] =3D { ASPEED_PINCTRL_PIN(D4), ASPEED_PINCTRL_PIN(D5), ASPEED_PINCTRL_PIN(D6), + ASPEED_PINCTRL_PIN(D7), ASPEED_PINCTRL_PIN(E1), ASPEED_PINCTRL_PIN(E11), ASPEED_PINCTRL_PIN(E12), @@ -2073,6 +2081,7 @@ static const struct aspeed_pin_group aspeed_g6_groups= [] =3D { ASPEED_PINCTRL_GROUP(SALT9G1), ASPEED_PINCTRL_GROUP(SD1), ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(PCIERC1), ASPEED_PINCTRL_GROUP(EMMCG1), ASPEED_PINCTRL_GROUP(EMMCG4), ASPEED_PINCTRL_GROUP(EMMCG8), @@ -2314,6 +2323,7 @@ static const struct aspeed_pin_function aspeed_g6_fun= ctions[] =3D { ASPEED_PINCTRL_FUNC(SPI2), ASPEED_PINCTRL_FUNC(SPI2CS1), ASPEED_PINCTRL_FUNC(SPI2CS2), + ASPEED_PINCTRL_FUNC(PCIERC1), ASPEED_PINCTRL_FUNC(TACH0), ASPEED_PINCTRL_FUNC(TACH1), ASPEED_PINCTRL_FUNC(TACH10), --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F49C2D5420; Tue, 15 Jul 2025 03:43:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551024; cv=none; b=MNHD0VnT9CBfzrvB6Fsm5Q54+k1Tjo3QuBOCT6pgE6L2fjHQ5M+Zap2ZtTjhX/vTvi6sbuPWzZ14y6KGrlvEN+gnncJvh6Sz1jMiE/xbHfPEcVGpFCyItypNR79LfTRqG+87JMJ0y31F9Ry5VfFwqAAa0tOGLDyhfeDF700Drko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551024; c=relaxed/simple; bh=1ELj8K0qv9rwEYVoYILkFh2eTrCj/a7OU84C6H7sm6E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cVMN7cOLkURFRcofYQvADSWP6KgKfAEpcrDaHk22BhT/fyOMbraqRnf1TAzFY/gUmU+7eoChmidyfyg1vE1RFy8tGtknELYnnrMXZR2J0rrTgxaH6EBShPdxEBEpKURgEsIcWq32YyohA8JNwwvOZFsxGQ3RuvrbsDG3AsZc6yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header Date: Tue, 15 Jul 2025 11:43:18 +0800 Message-ID: <20250715034320.2553837-9-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to PCIe specification, add FMT and TYPE definition for TLP header. And also add macro to combine FMT and TYPE to 1 byte. Signed-off-by: Jacky Chou --- include/uapi/linux/pci_regs.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a3a3e942dedf..700b915e00f5 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1230,4 +1230,36 @@ #define PCI_DVSEC_CXL_PORT_CTL 0x0c #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 =20 +/* Fmt[2:0] encoding for TLP Header */ +#define PCI_TLP_FMT_3DW_NO_DATA 0x0 // 3DW header, no data +#define PCI_TLP_FMT_4DW_NO_DATA 0x1 // 4DW header, no data +#define PCI_TLP_FMT_3DW_DATA 0x2 // 3DW header, with data +#define PCI_TLP_FMT_4DW_DATA 0x3 // 4DW header, with data +#define PCI_TLP_FMT_PREFIX 0x4 // Prefix header + +/* Type[4:0] encoding for TLP Header */ +#define PCI_TLP_TYPE_MEM_RD 0x00 // Memory Read Request +#define PCI_TLP_TYPE_MEM_RDLK 0x01 // Memory Read Lock Request +#define PCI_TLP_TYPE_MEM_WR 0x00 // Memory Write Request (Fmt must be wit= h data) +#define PCI_TLP_TYPE_IO_RD 0x02 // IO Read Request +#define PCI_TLP_TYPE_IO_WR 0x02 // IO Write Request (Fmt must be with dat= a) +#define PCI_TLP_TYPE_CFG0_RD 0x04 // Config Type 0 Read Request +#define PCI_TLP_TYPE_CFG0_WR 0x04 // Config Type 0 Write Request (Fmt mus= t be with data) +#define PCI_TLP_TYPE_CFG1_RD 0x05 // Config Type 1 Read Request +#define PCI_TLP_TYPE_CFG1_WR 0x05 // Config Type 1 Write Request (Fmt mus= t be with data) +#define PCI_TLP_TYPE_MSG 0x10 // Message Request (see routing field) +#define PCI_TLP_TYPE_MSGD 0x11 // Message Request with Data (see routing = field) +#define PCI_TLP_TYPE_CPL 0x0A // Completion without Data +#define PCI_TLP_TYPE_CPLD 0x0A // Completion with Data (Fmt must be with = data) +#define PCI_TLP_TYPE_CPLLCK 0x0B // Completion Locked +#define PCI_TLP_TYPE_CPLDLCK 0x0B // Completion with Data Locked (Fmt mus= t be with data) +#define PCI_TLP_TYPE_FETCH_ADD 0x0C // Fetch and Add AtomicOp Request +#define PCI_TLP_TYPE_SWAP 0x0D // Unconditional Swap AtomicOp Request +#define PCI_TLP_TYPE_CMP_SWAP 0x0E // Compare and Swap AtomicOp Request +#define PCI_TLP_TYPE_LOCAL_PREFIX 0x00 // Local TLP Prefix (Fmt =3D 0x4) +#define PCI_TLP_TYPE_E2E_PREFIX 0x10 // End-to-End TLP Prefix (Fmt =3D 0x= 4) + +/* Macro to combine Fmt and Type into the 8-bit field */ +#define PCIE_TLP_FMT_TYPE(fmt, type) (((fmt) << 5) | ((type) & 0x1F)) + #endif /* LINUX_PCI_REGS_H */ --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7292D5C78; Tue, 15 Jul 2025 03:43:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551026; cv=none; b=c5qxiyhHbjcafDFRHVCrY4piIO1ZDQddx4zPSYaBbdN+osciG8h/q98m0ZROYP8877sX9oZ0kUfQaqCv8l5V+Prjyh3+lb8+VMFjGNpwvfeHC/5Onso9Os6hOesCOp+bbDgNNsBlSOETjj+Eb8vuhy8U9Ta3IdhTDkq3+POTbdM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551026; c=relaxed/simple; bh=tf1gNNNEzddqapo6fqgATS7+37oKa3F8TBExBi86SHE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YzCAbpeD3g0nCUkwPnPmpxeFEg8o42PK6ygcDb0NpZeLE3vDRc1Exz+rXBvOo9ryjv8EtQeBDKPQRqVjM2ToWASfdfUiLNyq/tuJxgFcWqeRf+8AbyCgP4m/TkpKutXEnXAQoIpdxTGXsk5/dS69NhTX/GwRvu4o1dLoxNBz2SY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Date: Tue, 15 Jul 2025 11:43:19 +0800 Message-ID: <20250715034320.2553837-10-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce PCIe Root Complex driver for ASPEED SoCs. Support RC initialization, reset, clock, IRQ domain, and MSI domain setup. Implement platform-specific setup and register configuration for ASPEED. And provide PCI config space read/write and INTx/MSI interrupt handling. Signed-off-by: Jacky Chou --- drivers/pci/controller/Kconfig | 13 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-aspeed.c | 1137 ++++++++++++++++++++++++++ 3 files changed, 1151 insertions(+) create mode 100644 drivers/pci/controller/pcie-aspeed.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 886f6f43a895..acab0dd48e8d 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -52,6 +52,19 @@ config PCIE_APPLE =20 If unsure, say Y if you have an Apple Silicon system. =20 +config PCIE_ASPEED + bool "ASPEED PCIe controller" + depends on ARCH_ASPEED || COMPILE_TEST + depends on OF + select PCI_MSI_ARCH_FALLBACKS + help + Enable this option to add support for the PCIe controller + found on ASPEED SoCs. + This driver provides initialization and management for PCIe + Root Complex functionality, including interrupt and MSI support. + Select Y if your platform uses an ASPEED SoC and requires PCIe + connectivity. + config PCI_VERSATILE bool "ARM Versatile PB PCI controller" depends on ARCH_VERSATILE || COMPILE_TEST diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makef= ile index 038ccbd9e3ba..1339f88e153d 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) +=3D pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) +=3D pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) +=3D pcie-apple.o obj-$(CONFIG_PCIE_MT7621) +=3D pcie-mt7621.o +obj-$(CONFIG_PCIE_ASPEED) +=3D pcie-aspeed.o =20 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y +=3D dwc/ diff --git a/drivers/pci/controller/pcie-aspeed.c b/drivers/pci/controller/= pcie-aspeed.c new file mode 100644 index 000000000000..a7e679d5fb42 --- /dev/null +++ b/drivers/pci/controller/pcie-aspeed.c @@ -0,0 +1,1137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Aspeed Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_MSI_HOST_IRQS 64 +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 500 +#define PCIE_RESET_CONFIG_RC_WAIT_MS 10 + +/* AST2600 AHBC Registers */ +#define AHBC_KEY 0x00 +#define AHBC_UNLOCK_KEY 0xAEED1A03 +#define AHBC_UNLOCK 0x01 +#define AHBC_ADDR_MAPPING 0x8C +#define PCIE_RC_MEMORY_EN BIT(5) + +/* AST2600 PCIe Host Controller Registers */ +#define PEHR_GLOBAL 0x30 +#define AST2600_PORT_TYPE_MASK GENMASK(5, 4) +#define AST2600_PORT_TYPE(x) FIELD_PREP(AST2600_PORT_TYPE_MASK, x) +#define PEHR_LOCK 0x7C +#define PCIE_UNLOCK 0xa8 +#define PEHR_LINK 0xC0 +#define PCIE_LINK_UP BIT(5) + +/* AST2600 H2X Controller Registers */ +/* Common Registers*/ +#define H2X_INT_STS 0x08 +#define PCIE_TX_IDLE_CLEAR BIT(0) +#define PCIE_INTX_STS GENMASK(3, 0) +#define H2X_TX_DESC0 0x10 +#define H2X_TX_DESC1 0x14 +#define H2X_TX_DESC2 0x18 +#define H2X_TX_DESC3 0x1C +#define H2X_TX_DESC_DATA 0x20 +#define H2X_STS 0x24 +#define PCIE_TX_IDLE BIT(31) +#define PCIE_STATUS_OF_TX GENMASK(25, 24) +#define PCIE_RC_L_TX_COMPLETE BIT(24) +#define PCIE_RC_H_TX_COMPLETE BIT(25) +#define PCIE_TRIGGER_TX BIT(0) +#define H2X_AHB_ADDR_CONFIG0 0x60 +#define AHB_REMAP_LO_ADDR(x) FIELD_PREP(GENMASK(15, 4), x) +#define AHB_MASK_LO_ADDR(x) FIELD_PREP(GENMASK(31, 20), x) +#define H2X_AHB_ADDR_CONFIG1 0x64 +#define AHB_REMAP_HI_ADDR(x) (x) +#define H2X_AHB_ADDR_CONFIG2 0x68 +#define AHB_MASK_HI_ADDR(x) (x) + +/* Device Registers */ +#define H2X_DEV_CTRL 0x00 +#define PCIE_RX_DMA_EN BIT(9) +#define PCIE_RX_LINEAR BIT(8) +#define PCIE_RX_MSI_SEL BIT(7) +#define PCIE_RX_MSI_EN BIT(6) +#define PCIE_UNLOCK_RX_BUFF BIT(4) +#define PCIE_Wait_RX_TLP_CLR BIT(2) +#define PCIE_RC_RX_ENABLE BIT(1) +#define PCIE_RC_ENABLE BIT(0) +#define H2X_DEV_STS 0x08 +#define PCIE_RC_RX_DONE_ISR BIT(4) +#define H2X_DEV_RX_DESC_DATA 0x0C +#define H2X_DEV_RX_DESC1 0x14 +#define H2X_DEV_TX_TAG 0x3C + +/* AST2700 H2X */ +#define H2X_CTRL 0x00 +#define H2X_BRIDGE_EN BIT(0) +#define H2X_BRIDGE_DIRECT_EN BIT(1) +#define H2X_CFGE_INT_STS 0x08 +#define CFGE_TX_IDLE BIT(0) +#define CFGE_RX_BUSY BIT(1) +#define H2X_CFGI_TLP 0x20 +#define CFGI_BYTE_EN_MASK GENMASK(19, 16) +#define CFGI_BYTE_EN(x) FIELD_PREP(CFGI_BYTE_EN_MASK, (x)) +#define H2X_CFGI_WR_DATA 0x24 +#define CFGI_WRITE BIT(20) +#define H2X_CFGI_CTRL 0x28 +#define CFGI_TLP_FIRE BIT(0) +#define H2X_CFGI_RET_DATA 0x2C +#define H2X_CFGE_TLP_1ST 0x30 +#define H2X_CFGE_TLP_NEXT 0x34 +#define H2X_CFGE_CTRL 0x38 +#define CFGE_TLP_FIRE BIT(0) +#define H2X_CFGE_RET_DATA 0x3C +#define H2X_REMAP_PREF_ADDR 0x70 +#define REMAP_PREF_ADDR_63_32(x) (x) +#define H2X_REMAP_DIRECT_ADDR 0x78 +#define REMAP_BAR_BASE(x) (x) + +/* AST2700 PEHR */ +#define PEHR_MISC_58 0x58 +#define LOCAL_SCALE_SUP BIT(0) +#define PEHR_MISC_5C 0x5C +#define CONFIG_RC_DEVICE BIT(30) +#define PEHR_MISC_60 0x60 +#define AST2700_PORT_TYPE_MASK GENMASK(7, 4) +#define PORT_TYPE_ROOT BIT(2) +#define PEHR_MISC_70 0x70 +#define POSTED_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x) +#define POSTED_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x) +#define PEHR_MISC_78 0x78 +#define COMPLETION_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x) +#define COMPLETION_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x) +#define PEHR_MISC_300 0x300 +#define RC_GEN2 BIT(0) +#define PEHR_MISC_344 0x344 +#define LINK_UP_GEN2 BIT(18) +#define PEHR_MISC_358 0x358 +#define LINK_UP_GEN4 BIT(8) + +/* AST2700 SCU */ +#define SCU_60 0x60 +#define RC_E2M_PATH_EN BIT(0) +#define RC_H2XS_PATH_EN BIT(16) +#define RC_H2XD_PATH_EN BIT(17) +#define RC_H2XX_PATH_EN BIT(18) +#define RC_UPSTREAM_MEM_EN BIT(19) +#define SCU_64 0x64 +#define RC0_DECODE_DMA_BASE(x) FIELD_PREP(GENMASK(7, 0), x) +#define RC0_DECODE_DMA_LIMIT(x) FIELD_PREP(GENMASK(15, 8), x) +#define RC1_DECODE_DMA_BASE(x) FIELD_PREP(GENMASK(23, 16), x) +#define RC1_DECODE_DMA_LIMIT(x) FIELD_PREP(GENMASK(31, 24), x) +#define SCU_70 0x70 +#define DISABLE_EP_FUNC 0 + +/* TLP configuration type 0 and type 1 */ +#define CRG0_READ_FMTTYPE = \ + FIELD_PREP(GENMASK(31, 24), PCIE_TLP_FMT_TYPE(PCI_TLP_FMT_3DW_NO_DATA, \ + PCI_TLP_TYPE_CFG0_RD)) +#define CRG0_WRITE_FMTTYPE = \ + FIELD_PREP(GENMASK(31, 24), PCIE_TLP_FMT_TYPE(PCI_TLP_FMT_3DW_DATA, \ + PCI_TLP_TYPE_CFG0_WR)) +#define CRG1_READ_FMTTYPE = \ + FIELD_PREP(GENMASK(31, 24), PCIE_TLP_FMT_TYPE(PCI_TLP_FMT_3DW_NO_DATA, \ + PCI_TLP_TYPE_CFG1_RD)) +#define CRG1_WRITE_FMTTYPE = \ + FIELD_PREP(GENMASK(31, 24), PCIE_TLP_FMT_TYPE(PCI_TLP_FMT_3DW_DATA, \ + PCI_TLP_TYPE_CFG1_WR)) +#define CRG_PAYLOAD_SIZE 0x01 /* 1 DWORD */ +#define TLP_HEADER_BYTE_EN(x, y) ((GENMASK((x) - 1, 0) << ((y) % 4))) +#define TLP_GET_VALUE(x, y, z) (((x) >> ((((z) % 4)) * 8)) & GENMASK((8 *= (y)) - 1, 0)) +#define TLP_SET_VALUE(x, y, z) ((((x) & GENMASK((8 * (y)) - 1, 0)) << (((= (z) % 4)) * 8))) +#define AST2600_TX_DESC1_VALUE 0x00002000 +#define AST2700_TX_DESC1_VALUE 0x00401000 + +/** + * struct aspeed_pcie_port - PCIe port information + * @list: port list + * @pcie: pointer to PCIe host info + * @clk: pointer to the port clock gate + * @phy: pointer to PHY control block + * @perst: pointer to port reset control + * @slot: port slot + */ +struct aspeed_pcie_port { + struct list_head list; + struct aspeed_pcie *pcie; + struct clk *clk; + struct regmap *pciephy; + struct reset_control *perst; + u32 slot; +}; + +/** + * struct aspeed_pcie - PCIe port information + * @host: pointer to pcie host bridge + * @dev: pointer to device structure + * @reg: PCIe Host register base address + * @ahbc: pointer to AHHC register map + * @cfg: pointer to Aspeed PCIe configuration register map + * @platform: platform specific information + * @ports: list of PCIe ports + * @domain: PCI domain number + * @tx_tag: current TX tag for the port + * @h2xrst: pointer to H2X reset control + * @irq_domain: IRQ domain for INTx interrupts + * @dev_domain: IRQ domain for device interrupts + * @msi_domain: IRQ domain for MSI interrupts + * @lock: mutex to protect MSI bitmap variable + * @msi_irq_in_use: bitmap to track used MSI host IRQs + */ +struct aspeed_pcie { + struct pci_host_bridge *host; + struct device *dev; + void __iomem *reg; + struct regmap *ahbc; + struct regmap *cfg; + const struct aspeed_pcie_rc_platform *platform; + struct list_head ports; + + int domain; + u8 tx_tag; + + struct reset_control *h2xrst; + + struct irq_domain *irq_domain; + struct irq_domain *dev_domain; + struct irq_domain *msi_domain; + struct mutex lock; /* Protect MSI bitmap variable */ + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_HOST_IRQS); +}; + +/** + * struct aspeed_pcie_rc_platform - Platform information + * @setup: initialization function + * @get_link: port link status function + * @port_init: port initialization function + * @reg_intx_en: INTx enable register offset + * @reg_intx_sts: INTx status register offset + * @reg_msi_en: MSI enable register offset + * @reg_msi_sts: MSI enable register offset + * @msi_address: HW fixed MSI address + */ +struct aspeed_pcie_rc_platform { + int (*setup)(struct platform_device *pdev); + bool (*get_link)(struct aspeed_pcie_port *port); + void (*port_init)(struct aspeed_pcie_port *port); + int reg_intx_en; + int reg_intx_sts; + int reg_msi_en; + int reg_msi_sts; + int msi_address; +}; + +static void aspeed_pcie_intx_irq_ack(struct irq_data *d) +{ + struct aspeed_pcie *pcie =3D irq_data_get_irq_chip_data(d); + int intx_en =3D pcie->platform->reg_intx_en; + u32 en; + + en =3D readl(pcie->reg + intx_en); + en |=3D BIT(d->hwirq); + writel(en, pcie->reg + intx_en); +} + +static void aspeed_pcie_intx_irq_mask(struct irq_data *d) +{ + struct aspeed_pcie *pcie =3D irq_data_get_irq_chip_data(d); + int intx_en =3D pcie->platform->reg_intx_en; + u32 en; + + en =3D readl(pcie->reg + intx_en); + en |=3D BIT(d->hwirq); + writel(en, pcie->reg + intx_en); +} + +static void aspeed_pcie_intx_irq_unmask(struct irq_data *d) +{ + struct aspeed_pcie *pcie =3D irq_data_get_irq_chip_data(d); + int intx_en =3D pcie->platform->reg_intx_en; + u32 en; + + en =3D readl(pcie->reg + intx_en); + en |=3D BIT(d->hwirq); + writel(en, pcie->reg + intx_en); +} + +static struct irq_chip aspeed_intx_irq_chip =3D { + .name =3D "IntX", + .irq_ack =3D aspeed_pcie_intx_irq_ack, + .irq_mask =3D aspeed_pcie_intx_irq_mask, + .irq_unmask =3D aspeed_pcie_intx_irq_unmask, +}; + +static int aspeed_pcie_intx_map(struct irq_domain *domain, unsigned int ir= q, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &aspeed_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + irq_set_status_flags(irq, IRQ_LEVEL); + + return 0; +} + +static const struct irq_domain_ops aspeed_intx_domain_ops =3D { + .map =3D aspeed_pcie_intx_map, +}; + +static irqreturn_t aspeed_pcie_intr_handler(int irq, void *dev_id) +{ + struct aspeed_pcie *pcie =3D dev_id; + const struct aspeed_pcie_rc_platform *platform =3D pcie->platform; + unsigned long status; + unsigned long intx; + u32 bit; + int i; + + intx =3D readl(pcie->reg + platform->reg_intx_sts) & PCIE_INTX_STS; + for_each_set_bit(bit, &intx, PCI_NUM_INTX) + generic_handle_domain_irq(pcie->irq_domain, bit); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + for (i =3D 0; i < 2; i++) { + status =3D readl(pcie->reg + platform->reg_msi_sts + (i * 4)); + writel(status, pcie->reg + platform->reg_msi_sts + (i * 4)); + + for_each_set_bit(bit, &status, 32) { + bit +=3D (i * 32); + generic_handle_domain_irq(pcie->dev_domain, bit); + } + } + } + + return IRQ_HANDLED; +} + +static u32 aspeed_pcie_get_bdf_offset(struct pci_bus *bus, unsigned int de= vfn, + int where) +{ + return ((bus->number) << 24) | (PCI_SLOT(devfn) << 19) | + (PCI_FUNC(devfn) << 16) | (where & ~3); +} + +static bool aspeed_ast2600_get_link(struct aspeed_pcie_port *port) +{ + u32 link_sts; + + regmap_read(port->pciephy, PEHR_LINK, &link_sts); + + return !!(link_sts & PCIE_LINK_UP); +} + +static int aspeed_ast2600_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val, u32 fmt_type, + bool write) +{ + struct aspeed_pcie *pcie =3D bus->sysdata; + u32 bdf_offset, cfg_val, isr; + int ret; + + bdf_offset =3D aspeed_pcie_get_bdf_offset(bus, devfn, where); + + /* Driver may set unlock RX buffer before triggering next TX config */ + writel(PCIE_UNLOCK_RX_BUFF | readl(pcie->reg + H2X_DEV_CTRL), + pcie->reg + H2X_DEV_CTRL); + + cfg_val =3D fmt_type | CRG_PAYLOAD_SIZE; + regmap_write(pcie->cfg, H2X_TX_DESC0, cfg_val); + + cfg_val =3D AST2600_TX_DESC1_VALUE | FIELD_PREP(GENMASK(11, 8), pcie->tx_= tag) | + TLP_HEADER_BYTE_EN(size, where); + regmap_write(pcie->cfg, H2X_TX_DESC1, cfg_val); + + regmap_write(pcie->cfg, H2X_TX_DESC2, bdf_offset); + regmap_write(pcie->cfg, H2X_TX_DESC3, 0); + if (write) + regmap_write(pcie->cfg, H2X_TX_DESC_DATA, TLP_SET_VALUE(*val, size, wher= e)); + + regmap_write_bits(pcie->cfg, H2X_STS, PCIE_TRIGGER_TX, PCIE_TRIGGER_TX); + + ret =3D regmap_read_poll_timeout(pcie->cfg, H2X_STS, cfg_val, + (cfg_val & PCIE_TX_IDLE), 0, 50); + if (ret) { + dev_err(pcie->dev, + "%04x:%02x:%02x.%d CR tx timeout sts: 0x%08x\n", + pcie->domain, bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), cfg_val); + ret =3D PCIBIOS_SET_FAILED; + PCI_SET_ERROR_RESPONSE(val); + goto out; + } + + regmap_write_bits(pcie->cfg, H2X_INT_STS, PCIE_TX_IDLE_CLEAR, + PCIE_TX_IDLE_CLEAR); + + regmap_read(pcie->cfg, H2X_STS, &cfg_val); + switch (cfg_val & PCIE_STATUS_OF_TX) { + case PCIE_RC_L_TX_COMPLETE: + case PCIE_RC_H_TX_COMPLETE: + ret =3D readl_poll_timeout(pcie->reg + H2X_DEV_STS, isr, + (isr & PCIE_RC_RX_DONE_ISR), 0, 50); + if (ret) { + dev_err(pcie->dev, + "%04x:%02x:%02x.%d CR rx timeout sts: 0x%08x\n", + pcie->domain, bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), isr); + ret =3D PCIBIOS_SET_FAILED; + PCI_SET_ERROR_RESPONSE(val); + goto out; + } + if (!write) { + if (readl(pcie->reg + H2X_DEV_RX_DESC1) & BIT(13)) { + ret =3D PCIBIOS_SET_FAILED; + PCI_SET_ERROR_RESPONSE(val); + goto out; + } else { + *val =3D readl(pcie->reg + H2X_DEV_RX_DESC_DATA); + } + } + break; + case PCIE_STATUS_OF_TX: + ret =3D PCIBIOS_SET_FAILED; + PCI_SET_ERROR_RESPONSE(val); + goto out; + default: + regmap_read(pcie->cfg, H2X_DEV_RX_DESC_DATA, &cfg_val); + *val =3D cfg_val; + break; + } + + writel(PCIE_UNLOCK_RX_BUFF | readl(pcie->reg + H2X_DEV_CTRL), + pcie->reg + H2X_DEV_CTRL); + + *val =3D TLP_GET_VALUE(*val, size, where); + + ret =3D PCIBIOS_SUCCESSFUL; +out: + writel(readl(pcie->reg + H2X_DEV_STS), pcie->reg + H2X_DEV_STS); + pcie->tx_tag =3D (pcie->tx_tag + 1) % 0x8; + return ret; +} + +static int aspeed_ast2600_rd_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + int slot =3D PCI_SLOT(devfn); + + if (slot !=3D 0 && slot !=3D 8) + return PCIBIOS_DEVICE_NOT_FOUND; + + return aspeed_ast2600_conf(bus, devfn, where, size, val, CRG0_READ_FMTTYP= E, false); +} + +static int aspeed_ast2600_child_rd_conf(struct pci_bus *bus, unsigned int = devfn, + int where, int size, u32 *val) +{ + return aspeed_ast2600_conf(bus, devfn, where, size, val, CRG1_READ_FMTTYP= E, false); +} + +static int aspeed_ast2600_wr_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + int slot =3D PCI_SLOT(devfn); + + if (slot !=3D 0 && slot !=3D 8) + return PCIBIOS_DEVICE_NOT_FOUND; + + return aspeed_ast2600_conf(bus, devfn, where, size, &val, CRG0_WRITE_FMTT= YPE, true); +} + +static int aspeed_ast2600_child_wr_conf(struct pci_bus *bus, unsigned int = devfn, + int where, int size, u32 val) +{ + return aspeed_ast2600_conf(bus, devfn, where, size, &val, CRG1_WRITE_FMTT= YPE, true); +} + +static bool aspeed_ast2700_get_link(struct aspeed_pcie_port *port) +{ + u32 reg; + + /* AST2700 has Gen2 and Gen4 RCs. + * Read register to distinguish between Gen2 or Gen4. + * Then read the corresonding register that is from Aspeed + * design to get whether it linked up or not. + */ + regmap_read(port->pciephy, PEHR_MISC_300, ®); + if (reg & RC_GEN2) { + regmap_read(port->pciephy, PEHR_MISC_344, ®); + return !!(reg & LINK_UP_GEN2); + } + + regmap_read(port->pciephy, PEHR_MISC_358, ®); + return !!(reg & LINK_UP_GEN4); +} + +static int aspeed_ast2700_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val, bool write) +{ + struct aspeed_pcie *pcie =3D bus->sysdata; + u32 cfg_val; + + cfg_val =3D CFGI_BYTE_EN(TLP_HEADER_BYTE_EN(size, where)) | (where & ~3); + if (write) + cfg_val |=3D CFGI_WRITE; + writel(cfg_val, pcie->reg + H2X_CFGI_TLP); + + writel(TLP_SET_VALUE(*val, size, where), pcie->reg + H2X_CFGI_WR_DATA); + writel(CFGI_TLP_FIRE, pcie->reg + H2X_CFGI_CTRL); + *val =3D readl(pcie->reg + H2X_CFGI_RET_DATA); + *val =3D TLP_GET_VALUE(*val, size, where); + + return PCIBIOS_SUCCESSFUL; +} + +static int aspeed_ast2700_child_config(struct pci_bus *bus, unsigned int d= evfn, + int where, int size, u32 *val, + bool write) +{ + struct aspeed_pcie *pcie =3D bus->sysdata; + u32 bdf_offset, status, cfg_val; + int ret; + + bdf_offset =3D aspeed_pcie_get_bdf_offset(bus, devfn, where); + + cfg_val =3D CRG_PAYLOAD_SIZE; + if (write) + cfg_val |=3D (bus->number =3D=3D 1) ? CRG0_WRITE_FMTTYPE : CRG1_WRITE_FM= TTYPE; + else + cfg_val |=3D (bus->number =3D=3D 1) ? CRG0_READ_FMTTYPE : CRG1_READ_FMTT= YPE; + writel(cfg_val, pcie->reg + H2X_CFGE_TLP_1ST); + + cfg_val =3D AST2700_TX_DESC1_VALUE | + FIELD_PREP(GENMASK(11, 8), pcie->tx_tag) | + TLP_HEADER_BYTE_EN(size, where); + writel(cfg_val, pcie->reg + H2X_CFGE_TLP_NEXT); + + writel(bdf_offset, pcie->reg + H2X_CFGE_TLP_NEXT); + if (write) + writel(TLP_SET_VALUE(*val, size, where), pcie->reg + H2X_CFGE_TLP_NEXT); + writel(CFGE_TX_IDLE | CFGE_RX_BUSY, pcie->reg + H2X_CFGE_INT_STS); + writel(CFGE_TLP_FIRE, pcie->reg + H2X_CFGE_CTRL); + + ret =3D readl_poll_timeout(pcie->reg + H2X_CFGE_INT_STS, status, + (status & CFGE_TX_IDLE), 0, 50); + if (ret) { + dev_err(pcie->dev, + "%04x:%02x:%02x.%d CR tx timeout sts: 0x%08x\n", + pcie->domain, bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), status); + ret =3D PCIBIOS_SET_FAILED; + PCI_SET_ERROR_RESPONSE(val); + goto out; + } + + ret =3D readl_poll_timeout(pcie->reg + H2X_CFGE_INT_STS, status, + (status & CFGE_RX_BUSY), 0, 50); + if (ret) { + dev_err(pcie->dev, + "%04x:%02x:%02x.%d CR rx timeoutsts: 0x%08x\n", + pcie->domain, bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), status); + ret =3D PCIBIOS_SET_FAILED; + PCI_SET_ERROR_RESPONSE(val); + goto out; + } + *val =3D readl(pcie->reg + H2X_CFGE_RET_DATA); + *val =3D TLP_GET_VALUE(*val, size, where); + + ret =3D PCIBIOS_SUCCESSFUL; +out: + writel(status, pcie->reg + H2X_CFGE_INT_STS); + pcie->tx_tag =3D (pcie->tx_tag + 1) % 0xF; + return ret; +} + +static int aspeed_ast2700_rd_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + if (devfn !=3D 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return aspeed_ast2700_config(bus, devfn, where, size, val, false); +} + +static int aspeed_ast2700_child_rd_conf(struct pci_bus *bus, unsigned int = devfn, + int where, int size, u32 *val) +{ + return aspeed_ast2700_child_config(bus, devfn, where, size, val, false); +} + +static int aspeed_ast2700_wr_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + if (devfn !=3D 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return aspeed_ast2700_config(bus, devfn, where, size, &val, true); +} + +static int aspeed_ast2700_child_wr_conf(struct pci_bus *bus, unsigned int = devfn, + int where, int size, u32 val) +{ + return aspeed_ast2700_child_config(bus, devfn, where, size, &val, true); +} + +static struct pci_ops aspeed_ast2600_pcie_ops =3D { + .read =3D aspeed_ast2600_rd_conf, + .write =3D aspeed_ast2600_wr_conf, +}; + +static struct pci_ops aspeed_ast2600_pcie_child_ops =3D { + .read =3D aspeed_ast2600_child_rd_conf, + .write =3D aspeed_ast2600_child_wr_conf, +}; + +static struct pci_ops aspeed_ast2700_pcie_ops =3D { + .read =3D aspeed_ast2700_rd_conf, + .write =3D aspeed_ast2700_wr_conf, +}; + +static struct pci_ops aspeed_ast2700_pcie_child_ops =3D { + .read =3D aspeed_ast2700_child_rd_conf, + .write =3D aspeed_ast2700_child_wr_conf, +}; + +#ifdef CONFIG_PCI_MSI +static void aspeed_msi_compose_msi_msg(struct irq_data *data, + struct msi_msg *msg) +{ + struct aspeed_pcie *pcie =3D irq_data_get_irq_chip_data(data); + + msg->address_hi =3D 0; + msg->address_lo =3D pcie->platform->msi_address; + msg->data =3D data->hwirq; +} + +static int aspeed_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip aspeed_msi_bottom_irq_chip =3D { + .name =3D "ASPEED MSI", + .irq_compose_msi_msg =3D aspeed_msi_compose_msi_msg, + .irq_set_affinity =3D aspeed_msi_set_affinity, +}; + +static int aspeed_irq_msi_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + struct aspeed_pcie *pcie =3D domain->host_data; + int bit; + int i; + + mutex_lock(&pcie->lock); + + bit =3D bitmap_find_free_region(pcie->msi_irq_in_use, MAX_MSI_HOST_IRQS, + get_count_order(nr_irqs)); + + mutex_unlock(&pcie->lock); + + if (bit < 0) + return -ENOSPC; + + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, bit + i, + &aspeed_msi_bottom_irq_chip, + domain->host_data, handle_simple_irq, NULL, + NULL); + } + + return 0; +} + +static void aspeed_irq_msi_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *data =3D irq_domain_get_irq_data(domain, virq); + struct aspeed_pcie *pcie =3D irq_data_get_irq_chip_data(data); + + mutex_lock(&pcie->lock); + + bitmap_release_region(pcie->msi_irq_in_use, data->hwirq, + get_count_order(nr_irqs)); + + mutex_unlock(&pcie->lock); +} + +static const struct irq_domain_ops aspeed_msi_domain_ops =3D { + .alloc =3D aspeed_irq_msi_domain_alloc, + .free =3D aspeed_irq_msi_domain_free, +}; + +static struct irq_chip aspeed_msi_irq_chip =3D { + .name =3D "PCIe MSI", + .irq_enable =3D pci_msi_unmask_irq, + .irq_disable =3D pci_msi_mask_irq, + .irq_mask =3D pci_msi_mask_irq, + .irq_unmask =3D pci_msi_unmask_irq, +}; + +static struct msi_domain_info aspeed_msi_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), + .chip =3D &aspeed_msi_irq_chip, +}; + +static int aspeed_pcie_msi_init(struct aspeed_pcie *pcie) +{ + int ret =3D 0; + + writel(~0, pcie->reg + pcie->platform->reg_msi_en); + writel(~0, pcie->reg + pcie->platform->reg_msi_en + 0x04); + writel(~0, pcie->reg + pcie->platform->reg_msi_sts); + writel(~0, pcie->reg + pcie->platform->reg_msi_sts + 0x04); + + pcie->dev_domain =3D + irq_domain_add_linear(NULL, MAX_MSI_HOST_IRQS, &aspeed_msi_domain_ops, p= cie); + if (!pcie->dev_domain) + return dev_err_probe(pcie->dev, -ENOMEM, "failed to create IRQ domain\n"= ); + + pcie->msi_domain =3D pci_msi_create_irq_domain(dev_fwnode(pcie->dev), &as= peed_msi_domain_info, + pcie->dev_domain); + if (!pcie->msi_domain) + return dev_err_probe(pcie->dev, -ENOMEM, "failed to create MSI domain\n"= ); + + return ret; +} + +static void aspeed_pcie_msi_free(struct aspeed_pcie *pcie) +{ + if (pcie->msi_domain) { + irq_domain_remove(pcie->msi_domain); + pcie->msi_domain =3D NULL; + } + + if (pcie->dev_domain) { + irq_domain_remove(pcie->dev_domain); + pcie->dev_domain =3D NULL; + } +} +#else +static int aspeed_pcie_msi_init(struct aspeed_pcie *pcie) +{ + return 0; +} + +static void aspeed_pcie_msi_free(struct aspeed_pcie *pcie) {} +#endif + +static void aspeed_pcie_irq_domain_free(struct aspeed_pcie *pcie) +{ + if (pcie->irq_domain) { + irq_domain_remove(pcie->irq_domain); + pcie->irq_domain =3D NULL; + } + aspeed_pcie_msi_free(pcie); +} + +static int aspeed_pcie_init_irq_domain(struct aspeed_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct device_node *node =3D dev->of_node; + struct device_node *pcie_intc_node; + int ret; + + pcie_intc_node =3D of_get_next_child(node, NULL); + if (!pcie_intc_node) + return dev_err_probe(dev, -ENODEV, "No PCIe Intc node found\n"); + + pcie->irq_domain =3D + irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, &aspeed_intx_domain_= ops, pcie); + of_node_put(pcie_intc_node); + if (!pcie->irq_domain) { + ret =3D dev_err_probe(dev, -ENOMEM, "failed to get an INTx IRQ domain\n"= ); + goto err; + } + + writel(0, pcie->reg + pcie->platform->reg_intx_en); + writel(~0, pcie->reg + pcie->platform->reg_intx_sts); + + ret =3D aspeed_pcie_msi_init(pcie); + if (ret) + goto err; + + return 0; +err: + aspeed_pcie_irq_domain_free(pcie); + return ret; +} + +static void aspeed_ast2600_port_init(struct aspeed_pcie_port *port) +{ + regmap_write(port->pciephy, PEHR_LOCK, PCIE_UNLOCK); + regmap_write(port->pciephy, PEHR_GLOBAL, AST2600_PORT_TYPE(0x3)); +} + +static void aspeed_ast2700_port_init(struct aspeed_pcie_port *port) +{ + u32 cfg_val; + + regmap_write(port->pciephy, PEHR_MISC_70, + POSTED_DATA_CREDITS(0xc0) | POSTED_HEADER_CREDITS(0xa)); + regmap_write(port->pciephy, PEHR_MISC_78, + COMPLETION_DATA_CREDITS(0x30) | COMPLETION_HEADER_CREDITS(0x8)); + regmap_write(port->pciephy, PEHR_MISC_58, LOCAL_SCALE_SUP); + + regmap_write(port->pciephy, PEHR_MISC_5C, CONFIG_RC_DEVICE); + regmap_read(port->pciephy, PEHR_MISC_60, &cfg_val); + cfg_val &=3D ~AST2700_PORT_TYPE_MASK; + cfg_val |=3D FIELD_PREP(AST2700_PORT_TYPE_MASK, PORT_TYPE_ROOT); + regmap_write(port->pciephy, PEHR_MISC_60, cfg_val); +} + +static int aspeed_pcie_port_init(struct aspeed_pcie_port *port) +{ + struct aspeed_pcie *pcie =3D port->pcie; + struct device *dev =3D pcie->dev; + int ret; + + ret =3D clk_prepare_enable(port->clk); + if (ret) + return dev_err_probe(dev, ret, "enabling clk pcie%d\n", port->slot); + + pcie->platform->port_init(port); + + reset_control_deassert(port->perst); + mdelay(PCIE_RESET_CONFIG_DEVICE_WAIT_MS); + + if (pcie->platform->get_link(port)) + dev_dbg(dev, "PCIe%d port %d link up\n", pcie->domain, port->slot); + else + dev_dbg(dev, "PCIe%d port %d link down\n", pcie->domain, port->slot); + + return 0; +} + +static int aspeed_pcie_init_ports(struct aspeed_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct aspeed_pcie_port *port, *tmp; + u8 num_enabled =3D 0; + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + u32 slot =3D port->slot; + int ret; + + ret =3D aspeed_pcie_port_init(port); + if (ret) { + dev_err(dev, "initializing port %d failed\n", slot); + list_del(&port->list); + } else { + num_enabled++; + } + } + + return (num_enabled > 0) ? 0 : -ENODEV; +} + +static void aspeed_host_reset(struct aspeed_pcie *pcie) +{ + reset_control_assert(pcie->h2xrst); + mdelay(PCIE_RESET_CONFIG_RC_WAIT_MS); + reset_control_deassert(pcie->h2xrst); +} + +static int aspeed_ast2600_setup(struct platform_device *pdev) +{ + struct aspeed_pcie *pcie =3D platform_get_drvdata(pdev); + struct device *dev =3D pcie->dev; + + pcie->ahbc =3D syscon_regmap_lookup_by_phandle(dev->of_node, "aspeed,ahbc= "); + if (IS_ERR(pcie->ahbc)) + return dev_err_probe(dev, PTR_ERR(pcie->ahbc), "failed to map ahbc base\= n"); + + aspeed_host_reset(pcie); + + regmap_write(pcie->ahbc, AHBC_KEY, AHBC_UNLOCK_KEY); + regmap_update_bits(pcie->ahbc, AHBC_ADDR_MAPPING, PCIE_RC_MEMORY_EN, PCIE= _RC_MEMORY_EN); + regmap_write(pcie->ahbc, AHBC_KEY, AHBC_UNLOCK); + + regmap_write(pcie->cfg, H2X_AHB_ADDR_CONFIG0, + AHB_REMAP_LO_ADDR(0x600) | AHB_MASK_LO_ADDR(0xE00)); + regmap_write(pcie->cfg, H2X_AHB_ADDR_CONFIG1, AHB_REMAP_HI_ADDR(0)); + regmap_write(pcie->cfg, H2X_AHB_ADDR_CONFIG2, AHB_MASK_HI_ADDR(~0)); + + regmap_write(pcie->cfg, H2X_CTRL, H2X_BRIDGE_EN); + + writel(PCIE_RX_DMA_EN | PCIE_RX_LINEAR | PCIE_RX_MSI_SEL | PCIE_RX_MSI_EN= | + PCIE_Wait_RX_TLP_CLR | PCIE_RC_RX_ENABLE | PCIE_RC_ENABLE, + pcie->reg + H2X_DEV_CTRL); + + writel(0x28, pcie->reg + H2X_DEV_TX_TAG); + + pcie->host->ops =3D &aspeed_ast2600_pcie_ops; + pcie->host->child_ops =3D &aspeed_ast2600_pcie_child_ops; + + return 0; +} + +static int aspeed_ast2700_bar_assign(struct aspeed_pcie *pcie) +{ + struct resource_entry *win, *tmp; + struct pci_host_bridge *bridge =3D pcie->host; + + resource_list_for_each_entry_safe(win, tmp, &bridge->windows) { + struct resource *res =3D win->res; + + if (resource_type(res) =3D=3D IORESOURCE_MEM && + !(res->flags & IORESOURCE_MEM_64)) { + writel(REMAP_BAR_BASE(res->start), pcie->reg + H2X_REMAP_DIRECT_ADDR); + return 0; + } + } + + return -ENODEV; +} + +static int aspeed_ast2700_setup(struct platform_device *pdev) +{ + struct aspeed_pcie *pcie =3D platform_get_drvdata(pdev); + int ret; + + regmap_update_bits(pcie->cfg, SCU_60, + RC_E2M_PATH_EN | RC_H2XS_PATH_EN | RC_H2XD_PATH_EN | RC_H2XX_PATH_EN= | + RC_UPSTREAM_MEM_EN, + RC_E2M_PATH_EN | RC_H2XS_PATH_EN | RC_H2XD_PATH_EN | RC_H2XX_PATH_EN= | + RC_UPSTREAM_MEM_EN); + regmap_write(pcie->cfg, SCU_64, + RC0_DECODE_DMA_BASE(0) | RC0_DECODE_DMA_LIMIT(0xFF) | RC1_DECODE_DM= A_BASE(0) | + RC1_DECODE_DMA_LIMIT(0xFF)); + regmap_write(pcie->cfg, SCU_70, DISABLE_EP_FUNC); + + aspeed_host_reset(pcie); + + writel(0, pcie->reg + H2X_CTRL); + writel(H2X_BRIDGE_EN | H2X_BRIDGE_DIRECT_EN, pcie->reg + H2X_CTRL); + + ret =3D aspeed_ast2700_bar_assign(pcie); + if (ret) + return dev_err_probe(pcie->dev, ret, "Failed to assign bar\n"); + + /* Prepare for 64-bit BAR pref */ + writel(REMAP_PREF_ADDR_63_32(0x3), pcie->reg + H2X_REMAP_PREF_ADDR); + + pcie->host->ops =3D &aspeed_ast2700_pcie_ops; + pcie->host->child_ops =3D &aspeed_ast2700_pcie_child_ops; + + return 0; +} + +static int aspeed_pcie_parse_port(struct aspeed_pcie *pcie, + struct device_node *node, + int slot) +{ + struct aspeed_pcie_port *port; + struct device *dev =3D pcie->dev; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->pciephy =3D syscon_regmap_lookup_by_phandle(node, "aspeed,pciephy"); + if (IS_ERR(port->pciephy)) + return dev_err_probe(dev, PTR_ERR(port->pciephy), + "Failed to map pcie%d pciephy base\n", slot); + + port->clk =3D devm_get_clk_from_child(dev, node, NULL); + if (IS_ERR(port->clk)) + return dev_err_probe(dev, PTR_ERR(port->clk), + "Failed to get pcie%d clock\n", slot); + + port->perst =3D of_reset_control_get_exclusive(node, "perst"); + if (IS_ERR(port->perst)) + return dev_err_probe(dev, PTR_ERR(port->perst), + "Failed to get pcie%d reset control\n", slot); + reset_control_assert(port->perst); + + port->slot =3D slot; + port->pcie =3D pcie; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int aspeed_pcie_parse_dt(struct aspeed_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct device_node *node =3D dev->of_node; + int ret; + + for_each_available_child_of_node_scoped(node, child) { + int slot; + const char *type; + + ret =3D of_property_read_string(child, "device_type", &type); + if (ret || strcmp(type, "pci")) + continue; + + ret =3D of_pci_get_devfn(child); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to parse devfn\n"); + + slot =3D PCI_SLOT(ret); + + ret =3D aspeed_pcie_parse_port(pcie, child, slot); + if (ret) + return ret; + } + + if (list_empty(&pcie->ports)) + return dev_err_probe(dev, -ENODEV, "No PCIe port found in DT\n"); + + return 0; +} + +static int aspeed_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *host; + struct aspeed_pcie *pcie; + struct aspeed_pcie_port *port; + struct device_node *node =3D dev->of_node; + const struct aspeed_pcie_rc_platform *md =3D of_device_get_match_data(dev= ); + int irq, ret; + + if (!md) + return -ENODEV; + + host =3D devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); + if (!host) + return -ENOMEM; + + pcie =3D pci_host_bridge_priv(host); + pcie->dev =3D dev; + pcie->tx_tag =3D 0; + platform_set_drvdata(pdev, pcie); + + pcie->platform =3D md; + pcie->host =3D host; + INIT_LIST_HEAD(&pcie->ports); + + pcie->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pcie->reg)) + return PTR_ERR(pcie->reg); + + of_property_read_u32(node, "linux,pci-domain", &pcie->domain); + + pcie->cfg =3D syscon_regmap_lookup_by_phandle(dev->of_node, "aspeed,pciec= fg"); + if (IS_ERR(pcie->cfg)) + return dev_err_probe(dev, PTR_ERR(pcie->cfg), "Failed to map pciecfg bas= e\n"); + + pcie->h2xrst =3D devm_reset_control_get_exclusive(dev, "h2x"); + if (IS_ERR(pcie->h2xrst)) + return dev_err_probe(dev, PTR_ERR(pcie->h2xrst), "Failed to get h2x rese= t\n"); + + ret =3D devm_mutex_init(dev, &pcie->lock); + if (ret) + return dev_err_probe(dev, ret, "Failed to init mutex\n"); + + ret =3D pcie->platform->setup(pdev); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup PCIe RC\n"); + + ret =3D aspeed_pcie_parse_dt(pcie); + if (ret) + return ret; + + ret =3D aspeed_pcie_init_ports(pcie); + if (ret) + goto err_remove_resets; + + host->sysdata =3D pcie; + + ret =3D aspeed_pcie_init_irq_domain(pcie); + if (ret) + goto err_irq_init; + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) { + ret =3D irq; + goto err_irq; + } + + ret =3D devm_request_irq(dev, irq, aspeed_pcie_intr_handler, IRQF_SHARED,= dev_name(dev), + pcie); + if (ret) + goto err_irq; + + ret =3D pci_host_probe(host); + if (ret) + goto err_irq; + + return 0; +err_irq: + aspeed_pcie_irq_domain_free(pcie); +err_irq_init: +err_remove_resets: + list_for_each_entry(port, &pcie->ports, list) + reset_control_put(port->perst); + dev_err_probe(dev, ret, "Failed to initial RC\n"); + return ret; +} + +const struct aspeed_pcie_rc_platform pcie_rc_ast2600 =3D { + .setup =3D aspeed_ast2600_setup, + .get_link =3D aspeed_ast2600_get_link, + .port_init =3D aspeed_ast2600_port_init, + .reg_intx_en =3D 0x04, + .reg_intx_sts =3D 0x08, + .reg_msi_en =3D 0x20, + .reg_msi_sts =3D 0x28, + .msi_address =3D 0x1e77005c, +}; + +const struct aspeed_pcie_rc_platform pcie_rc_ast2700 =3D { + .setup =3D aspeed_ast2700_setup, + .get_link =3D aspeed_ast2700_get_link, + .port_init =3D aspeed_ast2700_port_init, + .reg_intx_en =3D 0x40, + .reg_intx_sts =3D 0x48, + .reg_msi_en =3D 0x50, + .reg_msi_sts =3D 0x58, + .msi_address =3D 0x000000F0, +}; + +static const struct of_device_id aspeed_pcie_of_match[] =3D { + { .compatible =3D "aspeed,ast2600-pcie", .data =3D &pcie_rc_ast2600 }, + { .compatible =3D "aspeed,ast2700-pcie", .data =3D &pcie_rc_ast2700 }, + {} +}; + +static struct platform_driver aspeed_pcie_driver =3D { + .driver =3D { + .name =3D "aspeed-pcie", + .of_match_table =3D aspeed_pcie_of_match, + }, + .probe =3D aspeed_pcie_probe, +}; + +module_platform_driver(aspeed_pcie_driver); + +MODULE_AUTHOR("Jacky Chou "); +MODULE_DESCRIPTION("ASPEED PCIe Root Complex"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Tue Oct 7 03:50:33 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37A352D63F1; Tue, 15 Jul 2025 03:43:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 10/10] MAINTAINERS: Add ASPEED PCIe RC driver Date: Tue, 15 Jul 2025 11:43:20 +0800 Message-ID: <20250715034320.2553837-11-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add maintainer for ASPEED PCIe RC driver. Signed-off-by: Jacky Chou --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3ecb44458a7e..e1839dc240bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3696,6 +3696,16 @@ S: Maintained F: Documentation/devicetree/bindings/media/aspeed,video-engine.yaml F: drivers/media/platform/aspeed/ =20 +ASPEED PCIE CONTROLLER DRIVER +M: Jacky Chou +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml +F: Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml +F: Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml +F: drivers/pci/controller/pcie-aspeed.c + ASUS EC HARDWARE MONITOR DRIVER M: Eugene Shalygin L: linux-hwmon@vger.kernel.org --=20 2.43.0