From nobody Tue Oct 7 01:56:34 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65689231845; Tue, 15 Jul 2025 15:17:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592623; cv=none; b=K/Wm8hj7Zd7Vx/Hpsp00m/WmfjElaDh9E2I2OUXYwn6QM/GpP/ErG1S0fLYaX1vqz7U6GlovsMx4SOuvjN7vcf1NFYcGqaa5lEXjINiKBd8/FWRzU0il+Shd4ghjdGG1xn728bZuEf3UW9pD/ljJEqek461o363NoxWM8k7aV4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592623; c=relaxed/simple; bh=vMjwZKNmLGQQ+e93Bf0Pbs3zIvFyXNewGXBTz3pe6UI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VRTBjZp2vN/hSyIQs5yxBCp6nMTAVcxfiLg9SL4yF79n/fGuKiN8QRlaRPRpoDdV4Wt0qUJ47IXbDDjoW/C69thQ+IurcSNvLft7v/9XXG++E5qKTX+RRSQZUlMDtJ6gqnZjhvhc3jxR0g9zbEAFfunoDC44VfheXWwxuMnR594= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oNRBZnTN; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oNRBZnTN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752592619; bh=vMjwZKNmLGQQ+e93Bf0Pbs3zIvFyXNewGXBTz3pe6UI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oNRBZnTNwB6jZFvEjta75dQvm3DeH+p+ZUlI/d1pLjnYPIARI7hs1zzHJfwOZl1i/ TACqfiBg5iZMd7tkzcJJ19mgpOMFnaHUyX9Ie46vGo42UPIirvfGB3xamS+zMS+vjY 6BOJlU+y0Bu84g82YLKx//bfcyS6K2aFzb8HgRolxCd6M7qSTcokgEADlmZag9mwXV UQ/atLjGgSJcwqmS76nqQqOguIYRK3mJpIv6VtCcrj1H747mo+Xm1fDgY1Tuvp5eUF 7hkxQwXSW4E9GxKPFd+22TxLf6mp2e2uGbiKo3czCBLQNOFeJZqIPrTY7AWaOHqWgF oc4CpsQ9GThoA== Received: from [192.168.0.2] (unknown [IPv6:2804:14d:72b4:82f6:67c:16ff:fe57:b5a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dwlsalmeida) by bali.collaboradmins.com (Postfix) with ESMTPSA id D1A1A17E0D15; Tue, 15 Jul 2025 17:16:56 +0200 (CEST) From: Daniel Almeida Date: Tue, 15 Jul 2025 12:16:38 -0300 Subject: [PATCH v7 1/6] rust: irq: add irq module Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-topics-tyr-request_irq2-v7-1-d469c0f37c07@collabora.com> References: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> In-Reply-To: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 Add the IRQ module. Future patches will then introduce support for IRQ registrations and handlers. Reviewed-by: Alice Ryhl Signed-off-by: Daniel Almeida Tested-by: Dirk Behme Tested-by: Joel Fernandes --- rust/kernel/irq.rs | 11 +++++++++++ rust/kernel/lib.rs | 1 + 2 files changed, 12 insertions(+) diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs new file mode 100644 index 0000000000000000000000000000000000000000..fae7b15effc80c936d6bffbd5b4= 150000d6c2898 --- /dev/null +++ b/rust/kernel/irq.rs @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! IRQ abstractions. +//! +//! An IRQ is an interrupt request from a device. It is used to get the CP= U's +//! attention so it can service a hardware event in a timely manner. +//! +//! The current abstractions handle IRQ requests and handlers, i.e.: it al= lows +//! drivers to register a handler for a given IRQ line. +//! +//! C header: [`include/linux/device.h`](srctree/include/linux/interrupt.h) diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index 5bbf3627212f0a26d34be0d6c160a370abf1e996..cdc31a89064e2144f1937a1588c= 460aea5f0ddf8 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -82,6 +82,7 @@ pub mod init; pub mod io; pub mod ioctl; +pub mod irq; pub mod jump_label; #[cfg(CONFIG_KUNIT)] pub mod kunit; --=20 2.50.0 From nobody Tue Oct 7 01:56:34 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6633C244675; Tue, 15 Jul 2025 15:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592626; cv=none; b=gPLhV485iMFn80NgtYukEzpcGtQlrPXJJmeNwCa6d07FqrYTTv88PIRCiBaGJTV3hNtlP2IK+3i6LiV/6+s/uvxXj1wNjei6hVl/ZuG6/V3naK1Hw8YY5FDHItOFFcq83GA92V8SLkphMV0mM/oi37UqeJw8mFNI/YvmkPnAB+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592626; c=relaxed/simple; bh=bEgEWNhssQSJW2BrmbFAEaknmVdtS6hkCDnTTi167Bw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b25mBSbh5z4YRyqnyaMvHYHuxvEBrOufPskuBwgTscS7IA6vUVM0jkM9ECNHKm0cEvde+lGH2TQrODAKaV0uMEVcm22GAfTfC0xsfIBUUpsHRxhQ3xMb1zZTg1BZ0Mq6K4siQn+81F5mN39flckss/7NvBu9JOTn2C9DG5wkTNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=FrdFChsB; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="FrdFChsB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752592622; bh=bEgEWNhssQSJW2BrmbFAEaknmVdtS6hkCDnTTi167Bw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FrdFChsBWqizUsSnKEbnhqAhI+3iWVPWydeFcdvotgO/JtTERZVS2ab4vSPZFe6Sk jDvqRQLkn9ou2Tj+okgaEmV3JH37bZiteXBWS4vR8JmYat1BEFUI47DHAw3nZPbW7T 8JGu9joWj23xIT/GfzFv1q0yMPtL+fP9udvCIXFfoxzpSh6HlQL5Q43dm0rZ2jE4rn vMlNXiZ51y8qeVpXew/HQn51396bNJdtVrEboLK0/sLkUdig+dh7NpznJr8EFlsQS3 OPBp6P4/8/6aktu/jn3XG/mS0j4EthuMGAJzIzhvee83bqwxDV+j3RVby2xB/rKy/k WFXzpMObdPUXg== Received: from [192.168.0.2] (unknown [IPv6:2804:14d:72b4:82f6:67c:16ff:fe57:b5a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dwlsalmeida) by bali.collaboradmins.com (Postfix) with ESMTPSA id F255C17E0FFA; Tue, 15 Jul 2025 17:16:59 +0200 (CEST) From: Daniel Almeida Date: Tue, 15 Jul 2025 12:16:39 -0300 Subject: [PATCH v7 2/6] rust: irq: add flags module Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-topics-tyr-request_irq2-v7-2-d469c0f37c07@collabora.com> References: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> In-Reply-To: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 Manipulating IRQ flags (i.e.: IRQF_*) will soon be necessary, specially to register IRQ handlers through bindings::request_irq(). Add a kernel::irq::Flags for that purpose. Reviewed-by: Alice Ryhl Signed-off-by: Daniel Almeida Tested-by: Dirk Behme Tested-by: Joel Fernandes --- rust/kernel/irq.rs | 3 ++ rust/kernel/irq/flags.rs | 124 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 127 insertions(+) diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs index fae7b15effc80c936d6bffbd5b4150000d6c2898..9abd9a6dc36f3e3ecc1f92ad7b0= 040176b56a079 100644 --- a/rust/kernel/irq.rs +++ b/rust/kernel/irq.rs @@ -9,3 +9,6 @@ //! drivers to register a handler for a given IRQ line. //! //! C header: [`include/linux/device.h`](srctree/include/linux/interrupt.h) + +/// Flags to be used when registering IRQ handlers. +pub mod flags; diff --git a/rust/kernel/irq/flags.rs b/rust/kernel/irq/flags.rs new file mode 100644 index 0000000000000000000000000000000000000000..a4882851d21f3e841862875ad72= 86ea6a2dfd2dd --- /dev/null +++ b/rust/kernel/irq/flags.rs @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright 2025 Collabora ltd. + +use crate::bindings; +use crate::prelude::*; + +/// Flags to be used when registering IRQ handlers. +/// +/// Flags can be used to request specific behaviors when registering an IRQ +/// handler, and can be combined using the `|`, `&`, and `!` operators to +/// further control the system's behavior. +/// +/// A common use case is to register a shared interrupt, as sharing the li= ne +/// between devices is increasingly common in modern systems and is even +/// required for some buses. This requires setting [`Flags::SHARED`] when +/// requesting the interrupt. Other use cases include setting the trigger = type +/// through `Flags::TRIGGER_*`, which determines when the interrupt fires,= or +/// controlling whether the interrupt is masked after the handler runs by = using +/// [`Flags::ONESHOT`]. +/// +/// If an invalid combination of flags is provided, the system will refuse= to +/// register the handler, and lower layers will enforce certain flags when +/// necessary. This means, for example, that all the +/// [`crate::irq::Registration`] for a shared interrupt have to agree on +/// [`Flags::SHARED`] and on the same trigger type, if set. +#[derive(Clone, Copy, PartialEq, Eq)] +pub struct Flags(c_ulong); + +impl Flags { + /// Use the interrupt line as already configured. + pub const TRIGGER_NONE: Flags =3D Flags::new(bindings::IRQF_TRIGGER_NO= NE); + + /// The interrupt is triggered when the signal goes from low to high. + pub const TRIGGER_RISING: Flags =3D Flags::new(bindings::IRQF_TRIGGER_= RISING); + + /// The interrupt is triggered when the signal goes from high to low. + pub const TRIGGER_FALLING: Flags =3D Flags::new(bindings::IRQF_TRIGGER= _FALLING); + + /// The interrupt is triggered while the signal is held high. + pub const TRIGGER_HIGH: Flags =3D Flags::new(bindings::IRQF_TRIGGER_HI= GH); + + /// The interrupt is triggered while the signal is held low. + pub const TRIGGER_LOW: Flags =3D Flags::new(bindings::IRQF_TRIGGER_LOW= ); + + /// Allow sharing the IRQ among several devices. + pub const SHARED: Flags =3D Flags::new(bindings::IRQF_SHARED); + + /// Set by callers when they expect sharing mismatches to occur. + pub const PROBE_SHARED: Flags =3D Flags::new(bindings::IRQF_PROBE_SHAR= ED); + + /// Flag to mark this interrupt as timer interrupt. + pub const TIMER: Flags =3D Flags::new(bindings::IRQF_TIMER); + + /// Interrupt is per CPU. + pub const PERCPU: Flags =3D Flags::new(bindings::IRQF_PERCPU); + + /// Flag to exclude this interrupt from irq balancing. + pub const NOBALANCING: Flags =3D Flags::new(bindings::IRQF_NOBALANCING= ); + + /// Interrupt is used for polling (only the interrupt that is register= ed + /// first in a shared interrupt is considered for performance reasons). + pub const IRQPOLL: Flags =3D Flags::new(bindings::IRQF_IRQPOLL); + + /// Interrupt is not reenabled after the hardirq handler finished. Use= d by + /// threaded interrupts which need to keep the irq line disabled until= the + /// threaded handler has been run. + pub const ONESHOT: Flags =3D Flags::new(bindings::IRQF_ONESHOT); + + /// Do not disable this IRQ during suspend. Does not guarantee that th= is + /// interrupt will wake the system from a suspended state. + pub const NO_SUSPEND: Flags =3D Flags::new(bindings::IRQF_NO_SUSPEND); + + /// Force enable it on resume even if [`NO_SUSPEND`] is set. + pub const FORCE_RESUME: Flags =3D Flags::new(bindings::IRQF_FORCE_RESU= ME); + + /// Interrupt cannot be threaded. + pub const NO_THREAD: Flags =3D Flags::new(bindings::IRQF_NO_THREAD); + + /// Resume IRQ early during syscore instead of at device resume time. + pub const EARLY_RESUME: Flags =3D Flags::new(bindings::IRQF_EARLY_RESU= ME); + + /// If the IRQ is shared with a [`NO_SUSPEND`] user, execute this inte= rrupt + /// handler after suspending interrupts. For system wakeup devices use= rs + /// need to implement wakeup detection in their interrupt handlers. + pub const COND_SUSPEND: Flags =3D Flags::new(bindings::IRQF_COND_SUSPE= ND); + + /// Don't enable IRQ or NMI automatically when users request it. Users= will + /// enable it explicitly by `enable_irq` or `enable_nmi` later. + pub const NO_AUTOEN: Flags =3D Flags::new(bindings::IRQF_NO_AUTOEN); + + /// Exclude from runnaway detection for IPI and similar handlers, depe= nds on + /// `PERCPU`. + pub const NO_DEBUG: Flags =3D Flags::new(bindings::IRQF_NO_DEBUG); + + pub(crate) fn into_inner(self) -> c_ulong { + self.0 + } + + const fn new(value: u32) -> Self { + build_assert!(value as u64 <=3D c_ulong::MAX as u64); + Self(value as c_ulong) + } +} + +impl core::ops::BitOr for Flags { + type Output =3D Self; + fn bitor(self, rhs: Self) -> Self::Output { + Self(self.0 | rhs.0) + } +} + +impl core::ops::BitAnd for Flags { + type Output =3D Self; + fn bitand(self, rhs: Self) -> Self::Output { + Self(self.0 & rhs.0) + } +} + +impl core::ops::Not for Flags { + type Output =3D Self; + fn not(self) -> Self::Output { + Self(!self.0) + } +} --=20 2.50.0 From nobody Tue Oct 7 01:56:34 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71C042472B4; Tue, 15 Jul 2025 15:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592629; cv=none; b=FH5ic9qQcmzb0hw8PrIeTC1uOQzICBx7qVMiXtCIrrG3jADK/yWgDrxyuNtKt+bGdkUcx5ftiAOFR0lJ/+4CMgGynCUWUhhjZrk9YBrCzO+qFXAiTVNPks8QQ8jw+mw9REuy9a9jglaQO9jKqFKxWD+FRpPPkKj/Q10hpFswcJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592629; c=relaxed/simple; bh=6KspKblwLa3ygC9eGe1wdnRmMHIHLXGix2wD06V0wkE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MGQyNMyMqvA0Q+hdJ89I8pkPEGznqukBlbNdZjcOhL+fZ6U9lVnNxXo22PCyisWtbsqLEmtoC3IXIBfFIaMB7b/i/u7VfcTHL4OetwwkXPeibpZOcw+SY8hvFgrW3FcrBFalAtGK684lMzTAMO7sCBuVxsNcdGl4U9enqYX354I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=opwj+zaZ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="opwj+zaZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752592625; bh=6KspKblwLa3ygC9eGe1wdnRmMHIHLXGix2wD06V0wkE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=opwj+zaZBq3R+UqvTfwQFhRAI/okXAGBVlpkWISwCmRuGumG0qJqbxNwYeoTQ1kgu 8MOVFFr5E30y7dAC8GWwu038CuINvjuLMcWa+VBnRZn/aXwXdrotfbaowDOP10FdqV LOcjEC5tsKNKcszOG661X5iFMHGx9KHEMOXayBuh9Uape/OSz95kHSlRD/T0SWsQ4q XOs65/o8R3h9VxckqtsJ29T1QRHTVs+gn1VaIsn7rb3bS27TPwHynSaxq/XNNDDK/1 yT/t9Som5AptMFwCSmAYVWMk4tyCQZOZNnKKVqcCv5ja94hKCt+Jj52pzOWzLZ9nQ6 aYdeGJnBE+/Ig== Received: from [192.168.0.2] (unknown [IPv6:2804:14d:72b4:82f6:67c:16ff:fe57:b5a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dwlsalmeida) by bali.collaboradmins.com (Postfix) with ESMTPSA id 20E2117E097E; Tue, 15 Jul 2025 17:17:03 +0200 (CEST) From: Daniel Almeida Date: Tue, 15 Jul 2025 12:16:40 -0300 Subject: [PATCH v7 3/6] rust: irq: add support for non-threaded IRQs and handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-topics-tyr-request_irq2-v7-3-d469c0f37c07@collabora.com> References: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> In-Reply-To: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 This patch adds support for non-threaded IRQs and handlers through irq::Registration and the irq::Handler trait. Registering an irq is dependent upon having a IrqRequest that was previously allocated by a given device. This will be introduced in subsequent patches. Signed-off-by: Daniel Almeida Tested-by: Dirk Behme Tested-by: Joel Fernandes --- rust/bindings/bindings_helper.h | 1 + rust/helpers/helpers.c | 1 + rust/helpers/irq.c | 9 ++ rust/kernel/irq.rs | 5 + rust/kernel/irq/request.rs | 267 ++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 283 insertions(+) diff --git a/rust/bindings/bindings_helper.h b/rust/bindings/bindings_helpe= r.h index 7e8f2285064797d5bbac5583990ff823b76c6bdc..fc73b89ff9d539e536a5da9388e= 4926a91a6130e 100644 --- a/rust/bindings/bindings_helper.h +++ b/rust/bindings/bindings_helper.h @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include diff --git a/rust/helpers/helpers.c b/rust/helpers/helpers.c index 0b09bd0e3561c7bf80bf79faf1aebd7eeb851984..653c3f7b85c5f7192b1584c748a= 9d7e4af3796e9 100644 --- a/rust/helpers/helpers.c +++ b/rust/helpers/helpers.c @@ -22,6 +22,7 @@ #include "dma.c" #include "drm.c" #include "err.c" +#include "irq.c" #include "fs.c" #include "io.c" #include "jump_label.c" diff --git a/rust/helpers/irq.c b/rust/helpers/irq.c new file mode 100644 index 0000000000000000000000000000000000000000..1faca428e2c047a656dec317185= 5c1508d67e60b --- /dev/null +++ b/rust/helpers/irq.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +int rust_helper_request_irq(unsigned int irq, irq_handler_t handler, + unsigned long flags, const char *name, void *dev) +{ + return request_irq(irq, handler, flags, name, dev); +} diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs index 9abd9a6dc36f3e3ecc1f92ad7b0040176b56a079..01bd08884b72c2a3a9460897bce= 751c732a19794 100644 --- a/rust/kernel/irq.rs +++ b/rust/kernel/irq.rs @@ -12,3 +12,8 @@ =20 /// Flags to be used when registering IRQ handlers. pub mod flags; + +/// IRQ allocation and handling. +pub mod request; + +pub use request::{Handler, IrqRequest, IrqReturn, Registration}; diff --git a/rust/kernel/irq/request.rs b/rust/kernel/irq/request.rs new file mode 100644 index 0000000000000000000000000000000000000000..2f4637d8bc4c9fda23cbc830768= 7035957b0042a --- /dev/null +++ b/rust/kernel/irq/request.rs @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright 2025 Collabora ltd. + +//! This module provides types like [`Registration`] which allow users to +//! register handlers for a given IRQ line. + +use core::marker::PhantomPinned; + +use crate::alloc::Allocator; +use crate::device::Bound; +use crate::device::Device; +use crate::devres::Devres; +use crate::error::to_result; +use crate::irq::flags::Flags; +use crate::prelude::*; +use crate::str::CStr; +use crate::sync::Arc; + +/// The value that can be returned from an IrqHandler or a ThreadedIrqHand= ler. +#[repr(u32)] +pub enum IrqReturn { + /// The interrupt was not from this device or was not handled. + None =3D bindings::irqreturn_IRQ_NONE, + + /// The interrupt was handled by this device. + Handled =3D bindings::irqreturn_IRQ_HANDLED, +} + +/// Callbacks for an IRQ handler. +pub trait Handler: Sync { + /// The hard IRQ handler. + /// + /// This is executed in interrupt context, hence all corresponding + /// limitations do apply. + /// + /// All work that does not necessarily need to be executed from + /// interrupt context, should be deferred to a threaded handler. + /// See also [`ThreadedRegistration`]. + fn handle(&self) -> IrqReturn; +} + +impl Handler for Arc { + fn handle(&self) -> IrqReturn { + T::handle(self) + } +} + +impl Handler for Box { + fn handle(&self) -> IrqReturn { + T::handle(self) + } +} + +/// # Invariants +/// +/// - `self.irq` is the same as the one passed to `request_{threaded}_irq`. +/// - `cookie` was passed to `request_{threaded}_irq` as the cookie. It +/// is guaranteed to be unique by the type system, since each call to +/// `new` will return a different instance of `Registration`. +#[pin_data(PinnedDrop)] +struct RegistrationInner { + irq: u32, + cookie: *mut c_void, +} + +impl RegistrationInner { + fn synchronize(&self) { + // SAFETY: safe as per the invariants of `RegistrationInner` + unsafe { bindings::synchronize_irq(self.irq) }; + } +} + +#[pinned_drop] +impl PinnedDrop for RegistrationInner { + fn drop(self: Pin<&mut Self>) { + // SAFETY: + // + // Safe as per the invariants of `RegistrationInner` and: + // + // - The containing struct is `!Unpin` and was initialized using + // pin-init, so it occupied the same memory location for the entir= ety of + // its lifetime. + // + // Notice that this will block until all handlers finish executing, + // i.e.: at no point will &self be invalid while the handler is ru= nning. + unsafe { bindings::free_irq(self.irq, self.cookie) }; + } +} + +// SAFETY: We only use `inner` on drop, which called at most once with no +// concurrent access. +unsafe impl Sync for RegistrationInner {} + +// SAFETY: It is safe to send `RegistrationInner` across threads. +unsafe impl Send for RegistrationInner {} + +/// A request for an IRQ line for a given device. +/// +/// # Invariants +/// +/// - `=C3=ACrq` is the number of an interrupt source of `dev`. +/// - `irq` has not been registered yet. +pub struct IrqRequest<'a> { + dev: &'a Device, + irq: u32, +} + +impl<'a> IrqRequest<'a> { + /// Creates a new IRQ request for the given device and IRQ number. + /// + /// # Safety + /// + /// - `irq` should be a valid IRQ number for `dev`. + pub(crate) unsafe fn new(dev: &'a Device, irq: u32) -> Self { + IrqRequest { dev, irq } + } + + /// Returns the IRQ number of an [`IrqRequest`]. + pub fn irq(&self) -> u32 { + self.irq + } +} + +/// A registration of an IRQ handler for a given IRQ line. +/// +/// # Examples +/// +/// The following is an example of using `Registration`. It uses a +/// [`AtomicU32`](core::sync::AtomicU32) to provide the interior mutabilit= y. +/// +/// ``` +/// use core::sync::atomic::AtomicU32; +/// use core::sync::atomic::Ordering; +/// +/// use kernel::prelude::*; +/// use kernel::device::Bound; +/// use kernel::irq::flags; +/// use kernel::irq::Registration; +/// use kernel::irq::IrqRequest; +/// use kernel::irq::IrqReturn; +/// use kernel::sync::Arc; +/// use kernel::c_str; +/// use kernel::alloc::flags::GFP_KERNEL; +/// +/// // Declare a struct that will be passed in when the interrupt fires. T= he u32 +/// // merely serves as an example of some internal data. +/// struct Data(AtomicU32); +/// +/// // [`kernel::irq::request::Handler::handle`] takes `&self`. This examp= le +/// // illustrates how interior mutability can be used when sharing the da= ta +/// // between process context and IRQ context. +/// +/// type Handler =3D Data; +/// +/// impl kernel::irq::request::Handler for Handler { +/// // This is executing in IRQ context in some CPU. Other CPUs can st= ill +/// // try to access to data. +/// fn handle(&self) -> IrqReturn { +/// self.0.fetch_add(1, Ordering::Relaxed); +/// +/// IrqReturn::Handled +/// } +/// } +/// +/// // Registers an IRQ handler for the given IrqRequest. +/// // +/// // This is executing in process context and assumes that `request` was +/// // previously acquired from a device. +/// fn register_irq(handler: Handler, request: IrqRequest<'_>) -> Result>> { +/// let registration =3D Registration::new(request, flags::SHARED, c_s= tr!("my_device"), handler); +/// +/// let registration =3D Arc::pin_init(registration, GFP_KERNEL)?; +/// +/// // The data can be accessed from process context too. +/// registration.handler().0.fetch_add(1, Ordering::Relaxed); +/// +/// Ok(registration) +/// } +/// # Ok::<(), Error>(()) +/// ``` +/// +/// # Invariants +/// +/// * We own an irq handler using `&self.handler` as its private data. +/// +#[pin_data] +pub struct Registration { + #[pin] + inner: Devres, + + #[pin] + handler: T, + + /// Pinned because we need address stability so that we can pass a poi= nter + /// to the callback. + #[pin] + _pin: PhantomPinned, +} + +impl Registration { + /// Registers the IRQ handler with the system for the given IRQ number. + pub fn new<'a>( + request: IrqRequest<'a>, + flags: Flags, + name: &'static CStr, + handler: T, + ) -> impl PinInit + 'a { + try_pin_init!(&this in Self { + handler, + inner <- Devres::new( + request.dev, + try_pin_init!(RegistrationInner { + // SAFETY: `this` is a valid pointer to the `Registrat= ion` instance + cookie: unsafe { &raw mut (*this.as_ptr()).handler }.c= ast(), + irq: { + // SAFETY: + // - The callbacks are valid for use with request_= irq. + // - If this succeeds, the slot is guaranteed to b= e valid until the + // destructor of Self runs, which will deregiste= r the callbacks + // before the memory location becomes invalid. + to_result(unsafe { + bindings::request_irq( + request.irq, + Some(handle_irq_callback::), + flags.into_inner(), + name.as_char_ptr(), + (&raw mut (*this.as_ptr()).handler).cast(), + ) + })?; + request.irq + } + }) + ), + _pin: PhantomPinned, + }) + } + + /// Returns a reference to the handler that was registered with the sy= stem. + pub fn handler(&self) -> &T { + &self.handler + } + + /// Wait for pending IRQ handlers on other CPUs. + /// + /// This will attempt to access the inner [`Devres`] container. + pub fn try_synchronize(&self) -> Result { + let inner =3D self.inner.try_access().ok_or(ENODEV)?; + inner.synchronize(); + Ok(()) + } + + /// Wait for pending IRQ handlers on other CPUs. + pub fn synchronize(&self, dev: &Device) -> Result { + let inner =3D self.inner.access(dev)?; + inner.synchronize(); + Ok(()) + } +} + +/// # Safety +/// +/// This function should be only used as the callback in `request_irq`. +unsafe extern "C" fn handle_irq_callback(_irq: i32, ptr: *mut = c_void) -> c_uint { + // SAFETY: `ptr` is a pointer to T set in `Registration::new` + let handler =3D unsafe { &*(ptr as *const T) }; + T::handle(handler) as c_uint +} --=20 2.50.0 From nobody Tue Oct 7 01:56:34 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE12224E019; Tue, 15 Jul 2025 15:17:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592632; cv=none; b=G+PjovYtnDwx/ZWTuSASVOxZi7hhiixF/Z1s0KV+guaXMfj1K8EJ0HWJFmxhuKYvtPkecRXMJ515iZMiw1UlgND14tLniywicrs40oCgs0IZbcnTQypA6AUU2MUQvCoCE7VL0jXgoXCgz0XiMRwv0Jr2bU1HkIGmXGdOhYRZamg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592632; c=relaxed/simple; bh=GaqTGAvm/SZ/WWXgNLPIL8I1p20P80a2MfUJbHC9h3k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BNX5mY1rGPjstrr0kD7mZ9zUi3E2CRtpGYZ+OB+KAI2XQM4ZE8aiCfAExRSqO2VECaNNYXFpnwq9IiMevX8y6cV4EODRZmPdepcHKGa7iPuvlSl/uSauEHQsRw3AiBY1rBUJ3rmLKV0jUxDtOXcNrdLIFP5hoSz2384vJ7TcZEk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ZqyKb15J; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ZqyKb15J" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752592629; bh=GaqTGAvm/SZ/WWXgNLPIL8I1p20P80a2MfUJbHC9h3k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZqyKb15JfttsACE4yi6CDpPWljpdwgd4XnV/UnUFWiAqScpDByQHg0ZGvImkI0uUS jmcPYnzXqYg/y9Gn8ZEy0wQCB+X8K3PLNO8w2zM4qX57qzpgoMK0QJDZZUSc/Ej8YI nIXifLOnpUGOnp2yBeIa4hqXvXLkHKf8+sl0pbe4OzmLqbQh37uktloSh5EdeWOgY6 TB3m+4E6ZPHNZmsivu7x4WDEozf/I2tMmuGG8Hnt1fItvlDXKlWMJj0CtCr9FqYoXn NUKUFWgm0X8B1gypZd7TebG4AAtEizPCiw3TJbgv8cmXAckxzEQfNwJLOiyJs0cp9+ 4SSVvxpiIDV2g== Received: from [192.168.0.2] (unknown [IPv6:2804:14d:72b4:82f6:67c:16ff:fe57:b5a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dwlsalmeida) by bali.collaboradmins.com (Postfix) with ESMTPSA id 40DCF17E1293; Tue, 15 Jul 2025 17:17:06 +0200 (CEST) From: Daniel Almeida Date: Tue, 15 Jul 2025 12:16:41 -0300 Subject: [PATCH v7 4/6] rust: irq: add support for threaded IRQs and handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-topics-tyr-request_irq2-v7-4-d469c0f37c07@collabora.com> References: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> In-Reply-To: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 This patch adds support for threaded IRQs and handlers through irq::ThreadedRegistration and the irq::ThreadedHandler trait. Threaded interrupts are more permissive in the sense that further processing is possible in a kthread. This means that said execution takes place outside of interrupt context, which is rather restrictive in many ways. Registering a threaded irq is dependent upon having an IrqRequest that was previously allocated by a given device. This will be introduced in subsequent patches. Signed-off-by: Daniel Almeida Tested-by: Dirk Behme Tested-by: Joel Fernandes --- rust/kernel/irq.rs | 5 +- rust/kernel/irq/request.rs | 227 +++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 229 insertions(+), 3 deletions(-) diff --git a/rust/kernel/irq.rs b/rust/kernel/irq.rs index 01bd08884b72c2a3a9460897bce751c732a19794..aaa40001bafca617c588c799bb4= 1144921595cae 100644 --- a/rust/kernel/irq.rs +++ b/rust/kernel/irq.rs @@ -16,4 +16,7 @@ /// IRQ allocation and handling. pub mod request; =20 -pub use request::{Handler, IrqRequest, IrqReturn, Registration}; +pub use request::{ + Handler, IrqRequest, IrqReturn, Registration, ThreadedHandler, Threade= dIrqReturn, + ThreadedRegistration, +}; diff --git a/rust/kernel/irq/request.rs b/rust/kernel/irq/request.rs index 2f4637d8bc4c9fda23cbc8307687035957b0042a..aa1b957fa18f927df2f14b18076= 393e1be2cf1d6 100644 --- a/rust/kernel/irq/request.rs +++ b/rust/kernel/irq/request.rs @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright 2025 Collabora ltd. =20 -//! This module provides types like [`Registration`] which allow users to -//! register handlers for a given IRQ line. +//! This module provides types like [`Registration`] and +//! [`ThreadedRegistration`], which allow users to register handlers for a= given +//! IRQ line. =20 use core::marker::PhantomPinned; =20 @@ -265,3 +266,225 @@ pub fn synchronize(&self, dev: &Device) -> Res= ult { let handler =3D unsafe { &*(ptr as *const T) }; T::handle(handler) as c_uint } + +/// The value that can be returned from `ThreadedHandler::handle_irq`. +#[repr(u32)] +pub enum ThreadedIrqReturn { + /// The interrupt was not from this device or was not handled. + None =3D bindings::irqreturn_IRQ_NONE, + + /// The interrupt was handled by this device. + Handled =3D bindings::irqreturn_IRQ_HANDLED, + + /// The handler wants the handler thread to wake up. + WakeThread =3D bindings::irqreturn_IRQ_WAKE_THREAD, +} + +/// Callbacks for a threaded IRQ handler. +pub trait ThreadedHandler: Sync { + /// The hard IRQ handler. + /// + /// This is executed in interrupt context, hence all corresponding + /// limitations do apply. All work that does not necessarily need to be + /// executed from interrupt context, should be deferred to the threaded + /// handler, i.e. [`ThreadedHandler::handle_threaded`]. + fn handle(&self) -> ThreadedIrqReturn; + + /// The threaded IRQ handler. + /// + /// This is executed in process context. The kernel creates a dedicated + /// kthread for this purpose. + fn handle_threaded(&self) -> IrqReturn; +} + +impl ThreadedHandler for Arc { + fn handle(&self) -> ThreadedIrqReturn { + T::handle(self) + } + + fn handle_threaded(&self) -> IrqReturn { + T::handle_threaded(self) + } +} + +impl ThreadedHandler for Box { + fn handle(&self) -> ThreadedIrqReturn { + T::handle(self) + } + + fn handle_threaded(&self) -> IrqReturn { + T::handle_threaded(self) + } +} + +/// A registration of a threaded IRQ handler for a given IRQ line. +/// +/// Two callbacks are required: one to handle the IRQ, and one to handle a= ny +/// other work in a separate thread. +/// +/// The thread handler is only called if the IRQ handler returns `WakeThre= ad`. +/// +/// # Examples +/// +/// The following is an example of using `ThreadedRegistration`. It uses a +/// [`AtomicU32`](core::sync::AtomicU32) to provide the interior mutabilit= y. +/// +/// ``` +/// use core::sync::atomic::AtomicU32; +/// use core::sync::atomic::Ordering; +/// +/// use kernel::prelude::*; +/// use kernel::device::Bound; +/// use kernel::irq::flags; +/// use kernel::irq::ThreadedIrqReturn; +/// use kernel::irq::ThreadedRegistration; +/// use kernel::irq::IrqRequest; +/// use kernel::irq::IrqReturn; +/// use kernel::sync::Arc; +/// use kernel::c_str; +/// use kernel::alloc::flags::GFP_KERNEL; +/// +/// // Declare a struct that will be passed in when the interrupt fires. T= he u32 +/// // merely serves as an example of some internal data. +/// struct Data(AtomicU32); +/// +/// // [`kernel::irq::request::ThreadedHandler::handle`] takes `&self`. Th= is example +/// // illustrates how interior mutability can be used when sharing the da= ta +/// // between process context and IRQ context. +/// type Handler =3D Data; +/// +/// impl kernel::irq::request::ThreadedHandler for Handler { +/// // This is executing in IRQ context in some CPU. Other CPUs can st= ill +/// // try to access the data. +/// fn handle(&self) -> ThreadedIrqReturn { +/// self.0.fetch_add(1, Ordering::Relaxed); +/// // By returning `WakeThread`, we indicate to the system that t= he +/// // thread function should be called. Otherwise, return +/// // ThreadedIrqReturn::Handled. +/// ThreadedIrqReturn::WakeThread +/// } +/// +/// // This will run (in a separate kthread) if and only if `handle` +/// // returns `WakeThread`. +/// fn handle_threaded(&self) -> IrqReturn { +/// self.0.fetch_add(1, Ordering::Relaxed); +/// IrqReturn::Handled +/// } +/// } +/// +/// // Registers a threaded IRQ handler for the given IrqRequest. +/// // +/// // This is executing in process context and assumes that `request` was +/// // previously acquired from a device. +/// fn register_threaded_irq(handler: Handler, request: IrqRequest<'_>) ->= Result>> { +/// let registration =3D ThreadedRegistration::new(request, flags::SHA= RED, c_str!("my_device"), handler); +/// +/// let registration =3D Arc::pin_init(registration, GFP_KERNEL)?; +/// +/// // The data can be accessed from process context too. +/// registration.handler().0.fetch_add(1, Ordering::Relaxed); +/// +/// Ok(registration) +/// } +/// # Ok::<(), Error>(()) +/// ``` +/// +/// # Invariants +/// +/// * We own an irq handler using `&T` as its private data. +/// +#[pin_data] +pub struct ThreadedRegistration { + #[pin] + inner: Devres, + + #[pin] + handler: T, + + /// Pinned because we need address stability so that we can pass a poi= nter + /// to the callback. + #[pin] + _pin: PhantomPinned, +} + +impl ThreadedRegistration { + /// Registers the IRQ handler with the system for the given IRQ number. + pub fn new<'a>( + request: IrqRequest<'a>, + flags: Flags, + name: &'static CStr, + handler: T, + ) -> impl PinInit + 'a { + try_pin_init!(&this in Self { + handler, + inner <- Devres::new( + request.dev, + try_pin_init!(RegistrationInner { + // SAFETY: `this` is a valid pointer to the `ThreadedR= egistration` instance. + cookie: unsafe { &raw mut (*this.as_ptr()).handler }.c= ast(), + irq: { + // SAFETY: + // - The callbacks are valid for use with request_= threaded_irq. + // - If this succeeds, the slot is guaranteed to b= e valid until the + // destructor of Self runs, which will deregister = the callbacks + // before the memory location becomes invalid. + to_result(unsafe { + bindings::request_threaded_irq( + request.irq, + Some(handle_threaded_irq_callback::), + Some(thread_fn_callback::), + flags.into_inner() as usize, + name.as_char_ptr(), + (&raw mut (*this.as_ptr()).handler).cast(), + ) + })?; + request.irq + } + }) + ), + _pin: PhantomPinned, + }) + } + + /// Returns a reference to the handler that was registered with the sy= stem. + pub fn handler(&self) -> &T { + &self.handler + } + + /// Wait for pending IRQ handlers on other CPUs. + /// + /// This will attempt to access the inner [`Devres`] container. + pub fn try_synchronize(&self) -> Result { + let inner =3D self.inner.try_access().ok_or(ENODEV)?; + inner.synchronize(); + Ok(()) + } + + /// Wait for pending IRQ handlers on other CPUs. + pub fn synchronize(&self, dev: &Device) -> Result { + let inner =3D self.inner.access(dev)?; + inner.synchronize(); + Ok(()) + } +} + +/// # Safety +/// +/// This function should be only used as the callback in `request_threaded= _irq`. +unsafe extern "C" fn handle_threaded_irq_callback( + _irq: i32, + ptr: *mut c_void, +) -> c_uint { + // SAFETY: `ptr` is a pointer to T set in `ThreadedRegistration::new` + let handler =3D unsafe { &*(ptr as *const T) }; + T::handle(handler) as c_uint +} + +/// # Safety +/// +/// This function should be only used as the callback in `request_threaded= _irq`. +unsafe extern "C" fn thread_fn_callback(_irq: i32, ptr= : *mut c_void) -> c_uint { + // SAFETY: `ptr` is a pointer to T set in `ThreadedRegistration::new` + let handler =3D unsafe { &*(ptr as *const T) }; + T::handle_threaded(handler) as c_uint +} --=20 2.50.0 From nobody Tue Oct 7 01:56:34 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D664921B9E2; Tue, 15 Jul 2025 15:17:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592635; cv=none; b=nYzHqDDAzS4UcBaoO6ylakBkiEqo6DYrWeVui1Uz1q0DPqU3gkCf6FraeFqeq3XLeVn5MXnlXPcv7rL6diYkEDbipzL0Abgd6ymseOmkb+q8vFqaRbI5c+7S5w8sqfpmAAQhxzm8XQaaxV9v8tzcrlM28v2UHjQJRx7Y7dcQVgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592635; c=relaxed/simple; bh=hDBDz41qpLHB3oj7BUa1RgzJiVkl4PhvA5k8G6iWXYQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O6lqV4tB7n/6ewQWV1ra8Bf3UK07pkubUZ+XNj+v0IICNhMwSA6U+Jl4zsh5bqqwacJFC7mt/LiY1fx7xcuo8va7sbjoA7n046mSIeS7RfBpFHTj3IGMxEOs4XXS+j7HpzLuLzI0+YpLDkZGXZs5C0HS9iiJoWMgYmI1KVByxQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=iSy5VCDY; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="iSy5VCDY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752592632; bh=hDBDz41qpLHB3oj7BUa1RgzJiVkl4PhvA5k8G6iWXYQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=iSy5VCDYtR6JhPh0S18NACM1GdFqtkoIxhNo5fbN9tRJLTnXZvERKziXwboBAEw20 vbKJsHJWab8vRhMB35Q/BOZ/zwu4NxnKLJA9hJ4RT9Rv5PF4MfsYjRUAbRMzhqS/Ab 1oIHYKtfuPCKRjj6Ntm1OUgav8lR47EiHvMhvB+7S5ujnYu6vVRoW340X46BhqfpfL /rPDWYTa3u2SU/nXUmzNYsVUZgEqlBaKuUzdcsiBdt0qrB+dvnVc+s6U/qmH1Ad6We EXaeJGBwBWgm/Hv6z30ku84fYiENv0jsogl3aXO72fOKnMDkz2pB0a66Bb0QYrH9L9 53mXvJYdxgEtw== Received: from [192.168.0.2] (unknown [IPv6:2804:14d:72b4:82f6:67c:16ff:fe57:b5a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dwlsalmeida) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6296A17E1324; Tue, 15 Jul 2025 17:17:09 +0200 (CEST) From: Daniel Almeida Date: Tue, 15 Jul 2025 12:16:42 -0300 Subject: [PATCH v7 5/6] rust: platform: add irq accessors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-topics-tyr-request_irq2-v7-5-d469c0f37c07@collabora.com> References: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> In-Reply-To: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 These accessors can be used to retrieve a irq::Registration and irq::ThreadedRegistration from a platform device by index or name. Alternatively, drivers can retrieve an IrqRequest from a bound platform device for later use. These accessors ensure that only valid IRQ lines can ever be registered. Reviewed-by: Alice Ryhl Signed-off-by: Daniel Almeida Tested-by: Dirk Behme Tested-by: Joel Fernandes --- rust/kernel/platform.rs | 146 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 145 insertions(+), 1 deletion(-) diff --git a/rust/kernel/platform.rs b/rust/kernel/platform.rs index ced43367d900bcb87c0ce1af3981f5e5af129840..ba334bfdaf1db4cb60a33ef2757= 39958bc4c77d5 100644 --- a/rust/kernel/platform.rs +++ b/rust/kernel/platform.rs @@ -5,8 +5,11 @@ //! C header: [`include/linux/platform_device.h`](srctree/include/linux/pl= atform_device.h) =20 use crate::{ - acpi, bindings, container_of, device, driver, + acpi, bindings, container_of, + device::{self, Bound}, + driver, error::{from_result, to_result, Result}, + irq::{self, IrqRequest}, of, prelude::*, types::Opaque, @@ -226,6 +229,147 @@ fn as_raw(&self) -> *mut bindings::platform_device { } } =20 +macro_rules! define_irq_accessor_by_index { + ($(#[$meta:meta])* $fn_name:ident, $request_fn:ident, $reg_type:ident,= $handler_trait:ident) =3D> { + $(#[$meta])* + pub fn $fn_name( + &self, + flags: irq::flags::Flags, + index: u32, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.$request_fn(index)?; + + Ok(irq::$reg_type::::new( + request, + flags, + name, + handler, + )) + } + }; +} + +macro_rules! define_irq_accessor_by_name { + ($(#[$meta:meta])* $fn_name:ident, $request_fn:ident, $reg_type:ident,= $handler_trait:ident) =3D> { + $(#[$meta])* + pub fn $fn_name( + &self, + flags: irq::flags::Flags, + irq_name: &CStr, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.$request_fn(irq_name)?; + + Ok(irq::$reg_type::::new( + request, + flags, + name, + handler, + )) + } + }; +} + +impl Device { + /// Returns an [`IrqRequest`] for the IRQ at the given index, if any. + pub fn irq_by_index(&self, index: u32) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { bindings::platform_get_irq(self.as_raw(), ind= ex) }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns an [`IrqRequest`] for the IRQ at the given index, but does= not + /// print an error if the IRQ cannot be obtained. + pub fn optional_irq_by_index(&self, index: u32) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { bindings::platform_get_irq_optional(self.as_r= aw(), index) }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns an [`IrqRequest`] for the IRQ with the given name, if any. + pub fn irq_by_name(&self, name: &CStr) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { bindings::platform_get_irq_byname(self.as_raw= (), name.as_char_ptr()) }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns an [`IrqRequest`] for the IRQ with the given name, but doe= s not + /// print an error if the IRQ cannot be obtained. + pub fn optional_irq_by_name(&self, name: &CStr) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct plat= form_device`. + let irq =3D unsafe { + bindings::platform_get_irq_byname_optional(self.as_raw(), name= .as_char_ptr()) + }; + + if irq < 0 { + return Err(Error::from_errno(irq)); + } + + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + define_irq_accessor_by_index!( + /// Returns a [`irq::Registration`] for the IRQ at the given index. + request_irq_by_index, irq_by_index, Registration, Handler + ); + define_irq_accessor_by_name!( + /// Returns a [`irq::Registration`] for the IRQ with the given nam= e. + request_irq_by_name, irq_by_name, Registration, Handler + ); + define_irq_accessor_by_index!( + /// Does the same as [`Self::request_irq_by_index`], except that i= t does + /// not print an error message if the IRQ cannot be obtained. + request_optional_irq_by_index, optional_irq_by_index, Registration= , Handler + ); + define_irq_accessor_by_name!( + /// Does the same as [`Self::request_irq_by_name`], except that it= does + /// not print an error message if the IRQ cannot be obtained. + request_optional_irq_by_name, optional_irq_by_name, Registration, = Handler + ); + + define_irq_accessor_by_index!( + /// Returns a [`irq::ThreadedRegistration`] for the IRQ at the giv= en index. + request_threaded_irq_by_index, irq_by_index, ThreadedRegistration,= ThreadedHandler + ); + define_irq_accessor_by_name!( + /// Returns a [`irq::ThreadedRegistration`] for the IRQ with the g= iven name. + request_threaded_irq_by_name, irq_by_name, ThreadedRegistration, T= hreadedHandler + ); + define_irq_accessor_by_index!( + /// Does the same as [`Self::request_threaded_irq_by_index`], exce= pt + /// that it does not print an error message if the IRQ cannot be + /// obtained. + request_optional_threaded_irq_by_index, optional_irq_by_index, Thr= eadedRegistration, ThreadedHandler + ); + define_irq_accessor_by_name!( + /// Does the same as [`Self::request_threaded_irq_by_name`], excep= t that + /// it does not print an error message if the IRQ cannot be obtain= ed. + request_optional_threaded_irq_by_name, optional_irq_by_name, Threa= dedRegistration, ThreadedHandler + ); +} + // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend= on `Device`'s generic // argument. kernel::impl_device_context_deref!(unsafe { Device }); --=20 2.50.0 From nobody Tue Oct 7 01:56:34 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA15326B767; Tue, 15 Jul 2025 15:17:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592638; cv=none; b=sfx0czMfl+/sUWx3Mbn+2pTBIOjnAwLf0LeL1VcS773Zy89g8m/uDBNhYkDtjVhAcHjJGYqQbibmRgwV8AYecwKI2t4IfaY9RrQkFI41w1NVhlEMQhqxlKYHwraBFu9hq6hxVDjDwvAJZfAsJNh4syBMXj01A6golbae2lxYyjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752592638; c=relaxed/simple; bh=Y5QpKSmWd6Wsb5VPbgQX80SRQm5mOODfgl3DJQHXIic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RCUmpt3FNcFGoNP36F1etG1shmBTv1LSqn9Y9J7oEVE/CnW6eqbjpCsv+nQU1rvILk/Ih0vzE+bymnHQZ+PGnPwpuYoS8qbJTpkAZ8j8fTHkL/+VZVX/YVjd9OemS1BKmDmEd/Ywa0CX0jr9JVsDFmpgI1yFMzdxLou//X0IWxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=po6MU4K9; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="po6MU4K9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752592635; bh=Y5QpKSmWd6Wsb5VPbgQX80SRQm5mOODfgl3DJQHXIic=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=po6MU4K9B+NVMA87SwrN4nZJsx2E4MX3JzOC0k76j6/qAgOiV8tBDV6HRo50ztGR7 LyvYJyQW7T49UIwswgVWTVjGW73mWBX4PeekQdVRYcIpIVqXxk3ZCyt0W9TtRsBJhV E89IqH/VvbwiDm1QGx0JlM9GGtq+rGwFh+VajA+oVFMAO1T15OsUa6BAjuMam2Qo7Q 1d32v6PYYfbr7RfYOWUE3HHcTTIW1bHPK2Xo7SxNiT/f7hf2Y8zUeR2FNtCnqJjNvS EIgzRHqtYVawGlxjjoxuTlAeIh1nSZZgcQyzoNOtfpl7yogqfdgEmZzawujEFtvK2B ojIj5MRT9NasQ== Received: from [192.168.0.2] (unknown [IPv6:2804:14d:72b4:82f6:67c:16ff:fe57:b5a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dwlsalmeida) by bali.collaboradmins.com (Postfix) with ESMTPSA id 84B6517E1325; Tue, 15 Jul 2025 17:17:12 +0200 (CEST) From: Daniel Almeida Date: Tue, 15 Jul 2025 12:16:43 -0300 Subject: [PATCH v7 6/6] rust: pci: add irq accessors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-topics-tyr-request_irq2-v7-6-d469c0f37c07@collabora.com> References: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> In-Reply-To: <20250715-topics-tyr-request_irq2-v7-0-d469c0f37c07@collabora.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Greg Kroah-Hartman , "Rafael J. Wysocki" , Thomas Gleixner , Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Benno Lossin Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org, Daniel Almeida X-Mailer: b4 0.14.2 These accessors can be used to retrieve a irq::Registration or a irq::ThreadedRegistration from a pci device. Alternatively, drivers can retrieve an IrqRequest from a bound PCI device for later use. These accessors ensure that only valid IRQ lines can ever be registered. Reviewed-by: Alice Ryhl Signed-off-by: Daniel Almeida Tested-by: Dirk Behme Tested-by: Joel Fernandes --- rust/helpers/pci.c | 8 ++++++++ rust/kernel/pci.rs | 45 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c index ef9cb38c81a6a5375f72c3676cd9730aad17757b..5bf56004478c6945dc3e1a394fc= d787c656d8b2a 100644 --- a/rust/helpers/pci.c +++ b/rust/helpers/pci.c @@ -11,3 +11,11 @@ bool rust_helper_dev_is_pci(const struct device *dev) { return dev_is_pci(dev); } + +#ifndef CONFIG_PCI_MSI +int rust_helper_pci_irq_vector(struct pci_dev *pdev, unsigned int nvec) +{ + return pci_irq_vector(pdev, nvec); +} + +#endif diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 8b884e324dcfcef2a2e69b009fe1e3071efe7066..1ae390245fc62a078ce9dfd6f67= b27368a5aeba2 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,8 +10,8 @@ devres::Devres, driver, error::{from_result, to_result, Result}, - io::Io, - io::IoRaw, + io::{Io, IoRaw}, + irq::{self, IrqRequest}, str::CStr, types::{ARef, Opaque}, ThisModule, @@ -427,6 +427,47 @@ pub fn iomap_region<'a>( ) -> impl PinInit, Error> + 'a { self.iomap_region_sized::<0>(bar, name) } + + /// Returns an [`IrqRequest`] for the IRQ vector at the given index, i= f any. + pub fn irq_vector(&self, index: u32) -> Result> { + // SAFETY: `self.as_raw` returns a valid pointer to a `struct pci_= dev`. + let irq =3D unsafe { crate::bindings::pci_irq_vector(self.as_raw()= , index) }; + if irq < 0 { + return Err(crate::error::Error::from_errno(irq)); + } + // SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self= `. + Ok(unsafe { IrqRequest::new(self.as_ref(), irq as u32) }) + } + + /// Returns a [`kernel::irq::Registration`] for the IRQ vector at the = given + /// index. + pub fn request_irq( + &self, + index: u32, + flags: irq::flags::Flags, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.irq_vector(index)?; + + Ok(irq::Registration::::new(request, flags, name, handler)) + } + + /// Returns a [`kernel::irq::ThreadedRegistration`] for the IRQ vector= at + /// the given index. + pub fn request_threaded_irq( + &self, + index: u32, + flags: irq::flags::Flags, + name: &'static CStr, + handler: T, + ) -> Result, Error> + '_> { + let request =3D self.irq_vector(index)?; + + Ok(irq::ThreadedRegistration::::new( + request, flags, name, handler, + )) + } } =20 impl Device { --=20 2.50.0