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[212.95.5.88]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-611c976fcfcsm6873715a12.66.2025.07.15.00.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jul 2025 00:19:24 -0700 (PDT) From: Luca Weiss Date: Tue, 15 Jul 2025 09:19:07 +0200 Subject: [PATCH v3 07/11] clk: qcom: Add Display Clock controller (DISPCC) driver for Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-sm7635-clocks-v3-7-18f9faac4984@fairphone.com> References: <20250715-sm7635-clocks-v3-0-18f9faac4984@fairphone.com> In-Reply-To: <20250715-sm7635-clocks-v3-0-18f9faac4984@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752563952; l=30647; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=Mo5T0kFjE5qgZcdBw3OSMj9T8MxmQ676LukIgNilpd8=; b=YRdy7aE4T4vnpJEyJC6Wn5L003ZqIVnUoOuSP8sO8Iu5pclUPl66d7X5NbL4O2H6jTA/I2uhK TV+GzZ7OLX5Ccob6351Gi+udMCk+nsuCE8vAxNPgiMxqzrRC40p2vPy X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add support for the display clock controller found on Milos (e.g. SM7635) based devices. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-milos.c | 974 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 985 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d2fdabbede4e702ef9e5f8bf09c169117cc84b29..1b42152ca1b98fac8bb7331a552= bc714346c868b 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1054,6 +1054,16 @@ config SM_DISPCC_6375 Say Y if you want to support display devices and functionality such as splash screen. =20 +config SM_DISPCC_MILOS + tristate "Milos Display Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on SM_GCC_MILOS + help + Support for the display clock controller on Qualcomm Technologies, Inc + Milos devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config SM_DISPCC_8450 tristate "SM8450 Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 933f9d153a6eccfd9987440bedd3a3dbf90b9792..978f39b1a3167d3fe5cc6699e67= 699f2dbe45905 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -138,6 +138,7 @@ obj-$(CONFIG_SM_DISPCC_8250) +=3D dispcc-sm8250.o obj-$(CONFIG_SM_DISPCC_8450) +=3D dispcc-sm8450.o obj-$(CONFIG_SM_DISPCC_8550) +=3D dispcc-sm8550.o obj-$(CONFIG_SM_DISPCC_8750) +=3D dispcc-sm8750.o +obj-$(CONFIG_SM_DISPCC_MILOS) +=3D dispcc-milos.o obj-$(CONFIG_SM_GCC_4450) +=3D gcc-sm4450.o obj-$(CONFIG_SM_GCC_6115) +=3D gcc-sm6115.o obj-$(CONFIG_SM_GCC_6125) +=3D gcc-sm6125.o diff --git a/drivers/clk/qcom/dispcc-milos.c b/drivers/clk/qcom/dispcc-milo= s.c new file mode 100644 index 0000000000000000000000000000000000000000..602d3a498d339b24af8e2a013df= 4053852d32b2b --- /dev/null +++ b/drivers/clk/qcom/dispcc-milos.c @@ -0,0 +1,974 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "reset.h" +#include "gdsc.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_AHB_CLK, + DT_GCC_DISP_GPLL0_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DP0_PHY_PLL_LINK_CLK, + DT_DP0_PHY_PLL_VCO_DIV_CLK, +}; + +#define DISP_CC_MISC_CMD 0xF000 + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_EVEN, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP0_PHY_PLL_LINK_CLK, + P_DP0_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_GCC_DISP_GPLL0_CLK, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 257.142858 MHz Configuration */ +static const struct alpha_pll_config disp_cc_pll0_config =3D { + .l =3D 0xd, + .alpha =3D 0x6492, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll disp_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &disp_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GCC_DISP_GPLL0_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, + { P_DISP_CC_PLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll0.clkr.hw }, + { .index =3D DT_GCC_DISP_GPLL0_CLK }, + { .hw =3D &disp_cc_pll0.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_7[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_7_ao[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), + F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8130, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x8098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src =3D { + .cmd_rcgr =3D 0x8118, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_aux_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { + .cmd_rcgr =3D 0x80cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x80e8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8100, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12800000, P_BI_TCXO, 1.5, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x80b4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .freq_tbl =3D ftbl_disp_cc_mdss_esc0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(342000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(535000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(630000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x8068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_6, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x8050, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x8080, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xe054, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_7, + .freq_tbl =3D ftbl_disp_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_sleep_clk_src", + .parent_data =3D disp_cc_parent_data_7_ao, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xe034, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_xo_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x80b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src =3D { + .reg =3D 0x80e4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_accu_clk =3D { + .halt_reg =3D 0xe050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xe050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_accu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb1_clk =3D { + .halt_reg =3D 0xa020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x8024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x8028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_aux_clk =3D { + .halt_reg =3D 0x8048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_crypto_clk =3D { + .halt_reg =3D 0x803c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_link_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk =3D { + .halt_reg =3D 0x8038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk =3D { + .halt_reg =3D 0x8040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk =3D { + .halt_reg =3D 0x8044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk =3D { + .halt_reg =3D 0x8034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_dptx0_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x802c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x802c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp1_clk =3D { + .halt_reg =3D 0xa004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut1_clk =3D { + .halt_reg =3D 0xa010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x8014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0xc004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xc004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk =3D { + .halt_reg =3D 0xc00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xc00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rscc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk =3D { + .halt_reg =3D 0xc008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xc008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_rscc_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync1_clk =3D { + .halt_reg =3D 0xa01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x8020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x9000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, +}; + +static struct gdsc disp_cc_mdss_core_int2_gdsc =3D { + .gdscr =3D 0xb000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "disp_cc_mdss_core_int2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *disp_cc_milos_clocks[] =3D { + [DISP_CC_MDSS_ACCU_CLK] =3D &disp_cc_mdss_accu_clk.clkr, + [DISP_CC_MDSS_AHB1_CLK] =3D &disp_cc_mdss_ahb1_clk.clkr, + [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &disp_cc_mdss_dptx0_aux_clk.clkr, + [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx0_aux_clk_src.clkr, + [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &disp_cc_mdss_dptx0_crypto_clk.clkr, + [DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &disp_cc_mdss_dptx0_link_clk.clkr, + [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx0_link_clk_src.cl= kr, + [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx0_link_div_cl= k_src.clkr, + [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx0_link_intf_clk.= clkr, + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &disp_cc_mdss_dptx0_pixel0_clk.clkr, + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx0_pixel0_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &disp_cc_mdss_dptx0_pixel1_clk.clkr, + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx0_pixel1_clk_sr= c.clkr, + [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D + &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP1_CLK] =3D &disp_cc_mdss_mdp1_clk.clkr, + [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT1_CLK] =3D &disp_cc_mdss_mdp_lut1_clk.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] =3D &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC1_CLK] =3D &disp_cc_mdss_vsync1_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK_SRC] =3D &disp_cc_sleep_clk_src.clkr, + [DISP_CC_XO_CLK_SRC] =3D &disp_cc_xo_clk_src.clkr, +}; + +static const struct qcom_reset_map disp_cc_milos_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, + [DISP_CC_MDSS_CORE_INT2_BCR] =3D { 0xa000 }, + [DISP_CC_MDSS_RSCC_BCR] =3D { 0xc000 }, +}; + +static struct gdsc *disp_cc_milos_gdscs[] =3D { + [DISP_CC_MDSS_CORE_GDSC] =3D &disp_cc_mdss_core_gdsc, + [DISP_CC_MDSS_CORE_INT2_GDSC] =3D &disp_cc_mdss_core_int2_gdsc, +}; + +static struct clk_alpha_pll *disp_cc_milos_plls[] =3D { + &disp_cc_pll0, +}; + +static u32 disp_cc_milos_critical_cbcrs[] =3D { + 0xe06c, /* DISP_CC_SLEEP_CLK */ + 0xe04c, /* DISP_CC_XO_CLK */ +}; + +static const struct regmap_config disp_cc_milos_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x11008, + .fast_io =3D true, +}; + +static void disp_cc_milos_clk_regs_configure(struct device *dev, struct re= gmap *regmap) +{ + /* Enable clock gating for MDP clocks */ + regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); +} + + +static struct qcom_cc_driver_data disp_cc_milos_driver_data =3D { + .alpha_plls =3D disp_cc_milos_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_milos_plls), + .clk_cbcrs =3D disp_cc_milos_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_milos_critical_cbcrs), + .clk_regs_configure =3D disp_cc_milos_clk_regs_configure, +}; + +static struct qcom_cc_desc disp_cc_milos_desc =3D { + .config =3D &disp_cc_milos_regmap_config, + .clks =3D disp_cc_milos_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_milos_clocks), + .resets =3D disp_cc_milos_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_milos_resets), + .gdscs =3D disp_cc_milos_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_milos_gdscs), + .use_rpm =3D true, + .driver_data =3D &disp_cc_milos_driver_data, +}; + +static const struct of_device_id disp_cc_milos_match_table[] =3D { + { .compatible =3D "qcom,milos-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_milos_match_table); + +static int disp_cc_milos_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &disp_cc_milos_desc); +} + +static struct platform_driver disp_cc_milos_driver =3D { + .probe =3D disp_cc_milos_probe, + .driver =3D { + .name =3D "disp_cc-milos", + .of_match_table =3D disp_cc_milos_match_table, + }, +}; + +module_platform_driver(disp_cc_milos_driver); + +MODULE_DESCRIPTION("QTI DISP_CC Milos Driver"); +MODULE_LICENSE("GPL"); --=20 2.50.1