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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni CC: , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752577357; l=4815; i=quic_luoj@quicinc.com; s=20250209; h=from:subject:message-id; bh=/sWPCINMaB60z+bkwQT0KPa0xCV+8eHOxXwRIeUpWyM=; b=2/asqrrW99u8254YRit7CLwqMSB6ahyZCPp5QKRYAy+SMiOTU7V1JQEK0ypqdezZF26JLKFX4 sn9bjiQ9vEZD7DSK2Syzftp/P/KWrZ43/GI/xx4RvM3tjLjPcMyTFCN X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=pzwy8bU5tJZ5UKGTv28n+QOuktaWuriznGmriA9Qkfc= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: q4AUgMI1g-7NGhPOVanCM--I47mw8AGN X-Authority-Analysis: v=2.4 cv=D4xHKuRj c=1 sm=1 tr=0 ts=68763553 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=xSRD5RxY1kXmWiYytnYA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: q4AUgMI1g-7NGhPOVanCM--I47mw8AGN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE1MDEwMCBTYWx0ZWRfXws5NkR7ZBMG2 f66rINwb0uQhbt36JMsNt87Tvpc2V2nRWU9idh98VVmD4ZTOoZI9p+fLYJ96E12Y19LTi3Dvwfn Y7EfUFo9HJipmRTGr/gycWMGsVRjjS4IOs3sz+fGNSB2/UIQZ7PYyVmAwGP16pIOqB2R8b8PTuk kpOLUoh13Gq25vQVLEhLqyDSwX8kh14BtFxbSsVcaLifzaf9MXzBTRhNzL8P2BU3RpFt6fohTbL tETdY/5CXw7MfM3YypgmgN0tdfNTwjNCoOhdAjZojiDkVzrZNeqTi5NzZGVJt76tIsCYHjkvPrH iM8eTEm0jOukMHwlRmDYZ/KJVNpUcDMbCfQLL577c025MTtKxxDovuyHgzM/RLH0fmQu55DYqo/ Oehs4v5Y2hth94lYYYTlBsKllA6zzj1a9Sxj48tGpiC7X3UMgcEGTzP2KkBATOkDqU62/d/o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-15_01,2025-07-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 suspectscore=0 bulkscore=0 mlxscore=0 priorityscore=1501 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507150100 Add PHY counter functionality to the shared library. The implementation is identical for the current QCA807X and QCA808X PHYs. The PHY counter can be configured to perform CRC checking for both received and transmitted packets. Additionally, the packet counter can be set to automatically clear after it is read. The PHY counter includes 32-bit packet counters for both RX (received) and TX (transmitted) packets, as well as 16-bit counters for recording CRC error packets for both RX and TX. Signed-off-by: Luo Jie Reviewed-by: Andrew Lunn --- drivers/net/phy/qcom/qcom-phy-lib.c | 75 +++++++++++++++++++++++++++++++++= ++++ drivers/net/phy/qcom/qcom.h | 23 ++++++++++++ 2 files changed, 98 insertions(+) diff --git a/drivers/net/phy/qcom/qcom-phy-lib.c b/drivers/net/phy/qcom/qco= m-phy-lib.c index af7d0d8e81be..965c2bb99a9b 100644 --- a/drivers/net/phy/qcom/qcom-phy-lib.c +++ b/drivers/net/phy/qcom/qcom-phy-lib.c @@ -699,3 +699,78 @@ int qca808x_led_reg_blink_set(struct phy_device *phyde= v, u16 reg, return 0; } EXPORT_SYMBOL_GPL(qca808x_led_reg_blink_set); + +/* Enable CRC checking for both received and transmitted frames to ensure + * accurate counter recording. The hardware supports a 32-bit counter, + * configure the counter to clear after it is read to facilitate the + * implementation of a 64-bit software counter + */ +int qcom_phy_counter_config(struct phy_device *phydev) +{ + return phy_set_bits_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_CTRL, + QCA808X_MMD7_CNT_CTRL_CRC_CHECK_EN | + QCA808X_MMD7_CNT_CTRL_READ_CLEAR_EN); +} +EXPORT_SYMBOL_GPL(qcom_phy_counter_config); + +int qcom_phy_update_stats(struct phy_device *phydev, + struct qcom_phy_hw_stats *hw_stats) +{ + int ret; + u32 cnt; + + /* PHY 32-bit counter for RX packets. */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_15_0); + if (ret < 0) + return ret; + + cnt =3D ret; + + ret =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_31_16); + if (ret < 0) + return ret; + + cnt |=3D ret << 16; + hw_stats->rx_pkts +=3D cnt; + + /* PHY 16-bit counter for RX CRC error packets. */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_ERR_PKT); + if (ret < 0) + return ret; + + hw_stats->rx_err_pkts +=3D ret; + + /* PHY 32-bit counter for TX packets. */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_PKT_15_0); + if (ret < 0) + return ret; + + cnt =3D ret; + + ret =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_PKT_31_16); + if (ret < 0) + return ret; + + cnt |=3D ret << 16; + hw_stats->tx_pkts +=3D cnt; + + /* PHY 16-bit counter for TX CRC error packets. */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_ERR_PKT); + if (ret < 0) + return ret; + + hw_stats->tx_err_pkts +=3D ret; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_phy_update_stats); + +void qcom_phy_get_stats(struct ethtool_phy_stats *stats, + struct qcom_phy_hw_stats hw_stats) +{ + stats->tx_packets =3D hw_stats.tx_pkts; + stats->tx_errors =3D hw_stats.tx_err_pkts; + stats->rx_packets =3D hw_stats.rx_pkts; + stats->rx_errors =3D hw_stats.rx_err_pkts; +} +EXPORT_SYMBOL_GPL(qcom_phy_get_stats); diff --git a/drivers/net/phy/qcom/qcom.h b/drivers/net/phy/qcom/qcom.h index 7f7151c8baca..5071e7149a11 100644 --- a/drivers/net/phy/qcom/qcom.h +++ b/drivers/net/phy/qcom/qcom.h @@ -195,6 +195,17 @@ #define AT803X_MIN_DOWNSHIFT 2 #define AT803X_MAX_DOWNSHIFT 9 =20 +#define QCA808X_MMD7_CNT_CTRL 0x8029 +#define QCA808X_MMD7_CNT_CTRL_READ_CLEAR_EN BIT(1) +#define QCA808X_MMD7_CNT_CTRL_CRC_CHECK_EN BIT(0) + +#define QCA808X_MMD7_CNT_RX_PKT_31_16 0x802a +#define QCA808X_MMD7_CNT_RX_PKT_15_0 0x802b +#define QCA808X_MMD7_CNT_RX_ERR_PKT 0x802c +#define QCA808X_MMD7_CNT_TX_PKT_31_16 0x802d +#define QCA808X_MMD7_CNT_TX_PKT_15_0 0x802e +#define QCA808X_MMD7_CNT_TX_ERR_PKT 0x802f + enum stat_access_type { PHY, MMD @@ -212,6 +223,13 @@ struct at803x_ss_mask { u8 speed_shift; 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Additionally, add PHY counter operations and integrate shared functions. Signed-off-by: Luo Jie --- drivers/net/phy/qcom/qca808x.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/net/phy/qcom/qca808x.c b/drivers/net/phy/qcom/qca808x.c index 6de16c0eaa08..8eb51b1a006c 100644 --- a/drivers/net/phy/qcom/qca808x.c +++ b/drivers/net/phy/qcom/qca808x.c @@ -93,6 +93,7 @@ MODULE_LICENSE("GPL"); =20 struct qca808x_priv { int led_polarity_mode; + struct qcom_phy_hw_stats hw_stats; }; =20 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) @@ -243,6 +244,10 @@ static int qca808x_config_init(struct phy_device *phyd= ev) =20 qca808x_fill_possible_interfaces(phydev); =20 + ret =3D qcom_phy_counter_config(phydev); + if (ret) + return ret; + /* Configure adc threshold as 100mv for the link 10M */ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, QCA808X_ADC_THRESHOLD_MASK, @@ -622,6 +627,22 @@ static int qca808x_led_polarity_set(struct phy_device = *phydev, int index, active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); } =20 +static int qca808x_update_stats(struct phy_device *phydev) +{ + struct qca808x_priv *priv =3D phydev->priv; + + return qcom_phy_update_stats(phydev, &priv->hw_stats); +} + +static void qca808x_get_phy_stats(struct phy_device *phydev, + struct ethtool_eth_phy_stats *eth_stats, + struct ethtool_phy_stats *stats) +{ + struct qca808x_priv *priv =3D phydev->priv; + + qcom_phy_get_stats(stats, priv->hw_stats); +} + static struct phy_driver qca808x_driver[] =3D { { /* Qualcomm QCA8081 */ @@ -651,6 +672,8 @@ static struct phy_driver qca808x_driver[] =3D { .led_hw_control_set =3D qca808x_led_hw_control_set, .led_hw_control_get =3D qca808x_led_hw_control_get, .led_polarity_set =3D qca808x_led_polarity_set, + .update_stats =3D qca808x_update_stats, + .get_phy_stats =3D qca808x_get_phy_stats, }, }; =20 module_phy_driver(qca808x_driver); --=20 2.34.1 From nobody Tue Oct 7 01:59:27 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0FC12DA748; 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Tue, 15 Jul 2025 11:02:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56FB2m9B004036 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 15 Jul 2025 11:02:48 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 04:02:45 -0700 From: Luo Jie Date: Tue, 15 Jul 2025 19:02:28 +0800 Subject: [PATCH net-next v3 3/3] net: phy: qcom: qca807x: Support PHY counter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250715-qcom_phy_counter-v3-3-8b0e460a527b@quicinc.com> References: <20250715-qcom_phy_counter-v3-0-8b0e460a527b@quicinc.com> In-Reply-To: <20250715-qcom_phy_counter-v3-0-8b0e460a527b@quicinc.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. 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Additionally, add support for PHY counter operations. Signed-off-by: Luo Jie --- drivers/net/phy/qcom/qca807x.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/phy/qcom/qca807x.c b/drivers/net/phy/qcom/qca807x.c index 6d10ef7e9a8a..291f052ea53c 100644 --- a/drivers/net/phy/qcom/qca807x.c +++ b/drivers/net/phy/qcom/qca807x.c @@ -124,6 +124,7 @@ struct qca807x_priv { bool dac_full_amplitude; bool dac_full_bias_current; bool dac_disable_bias_current_tweak; + struct qcom_phy_hw_stats hw_stats; }; =20 static int qca807x_cable_test_start(struct phy_device *phydev) @@ -768,6 +769,10 @@ static int qca807x_config_init(struct phy_device *phyd= ev) return ret; } =20 + ret =3D qcom_phy_counter_config(phydev); + if (ret) + return ret; + control_dac =3D phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH); control_dac &=3D ~QCA807X_CONTROL_DAC_MASK; @@ -782,6 +787,22 @@ static int qca807x_config_init(struct phy_device *phyd= ev) control_dac); } =20 +static int qca807x_update_stats(struct phy_device *phydev) +{ + struct qca807x_priv *priv =3D phydev->priv; + + return qcom_phy_update_stats(phydev, &priv->hw_stats); +} + +static void qca807x_get_phy_stats(struct phy_device *phydev, + struct ethtool_eth_phy_stats *eth_stats, + struct ethtool_phy_stats *stats) +{ + struct qca807x_priv *priv =3D phydev->priv; + + qcom_phy_get_stats(stats, priv->hw_stats); +} + static struct phy_driver qca807x_drivers[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_QCA8072), @@ -800,6 +821,8 @@ static struct phy_driver qca807x_drivers[] =3D { .suspend =3D genphy_suspend, .cable_test_start =3D qca807x_cable_test_start, .cable_test_get_status =3D qca808x_cable_test_get_status, + .update_stats =3D qca807x_update_stats, + .get_phy_stats =3D qca807x_get_phy_stats, }, { PHY_ID_MATCH_EXACT(PHY_ID_QCA8075), @@ -823,6 +846,8 @@ static struct phy_driver qca807x_drivers[] =3D { .led_hw_is_supported =3D qca807x_led_hw_is_supported, .led_hw_control_set =3D qca807x_led_hw_control_set, .led_hw_control_get =3D qca807x_led_hw_control_get, + .update_stats =3D qca807x_update_stats, + .get_phy_stats =3D qca807x_get_phy_stats, }, }; module_phy_driver(qca807x_drivers); --=20 2.34.1