From nobody Tue Oct 7 01:58:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD68220C00C; Tue, 15 Jul 2025 12:51:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752583903; cv=none; b=VrC7UenGy8WNNkbCbGCx+NVE13NqJw/i7larLG8B4W66poso1oQQaUPrkIatkB1R9tVGwtb6fZn6VD1DHywF7LK2G4S46FG0qepKI4D/+jXY5uvcZMtkXcYJYcdHdDEFSULkoHMXUtZ9q5QP+kNVtTeGUCRgxOUkcHxJm1nDkqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752583903; c=relaxed/simple; bh=2TkqcdkiWyrnm1Y72+wWgizVw6FEwqJ4t2W4Sl/s5HQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pM6MRzuBWAorE1OnDgt7pmsAcT9WTIQ7oG23dSGXEOafJH/skoKuasZwjJXV49fwdtcPyBPfSbBDTLsu56lIOsRPcfrcjump5wT/CWtydMQwf6pbamh83O4AqgDaPbEtRl9y5ZTX6U4wqbNTjba/EKLHv6/E1YV3dAtN5mC7ZR0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TIoCqEGv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TIoCqEGv" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6896AC4CEF6; Tue, 15 Jul 2025 12:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752583903; bh=2TkqcdkiWyrnm1Y72+wWgizVw6FEwqJ4t2W4Sl/s5HQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TIoCqEGv0LZj54U2MgqyqflIK2m5GfGdmC7j8er6E+p5yUgyDSDCcKM7DPSzpC/oo qxGdmI7mCU5HB1VOGKnjFlCnV+8M2iM+MDvBRqwDyLrXtnPqV8FKkYRU77Ekp6J4ae mRnDhu+4ulNMMNQoxPTGKXTbQ0Zd9C3UMwBcn8Nkt8VqsaM0N8lJL/oGecE4LiTMGO yNqeaBU7fNb2VKFtcpfqmgduCxZuDC+PHfYlzNawfeMl0s5VqyrJ7bJTB7rtjDX+52 WJ2NmjcCCstD65Fpn8nU7etJJaois9QF4el9rPhqCqxfKKpS/wtaXeIOx13TP6vv3I hHih3xvWGJ2CQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56FBEC83F21; Tue, 15 Jul 2025 12:51:43 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 15 Jul 2025 20:51:38 +0800 Subject: [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-add_video_clk-v1-1-40e7f633f361@amlogic.com> References: <20250715-add_video_clk-v1-0-40e7f633f361@amlogic.com> In-Reply-To: <20250715-add_video_clk-v1-0-40e7f633f361@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752583900; l=1212; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=LztxELd9EtqmjCHRSvnKXiDEtIhmTixy/0hdsbLfFOA=; b=H9D6zYFXC/H+ChDtNW3x0uSFhuScIdrRXaA1ArwghGEqWePsiq/3BLToknEoNOGIzsLvNoED7 Ek24Wg8K0TNDNgnd9VqLJPVZuJUu7vagTAQu5PiiMFhgy7HYBtzljT5 X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add indices for video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu Acked-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,s4-peripherals-clkc.h index 861a331963ac..a1cd22b25102 100644 --- a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h @@ -232,5 +232,19 @@ #define CLKID_HDCP22_SKPCLK_SEL 222 #define CLKID_HDCP22_SKPCLK_DIV 223 #define CLKID_HDCP22_SKPCLK 224 +#define CLKID_CTS_ENCL_SEL 225 +#define CLKID_CTS_ENCL 226 +#define CLKID_LCD_AN_SEL 227 +#define CLKID_LCD_AN_PH2 228 +#define CLKID_LCD_AN_PH3 229 +#define CLKID_CDAC_SEL 230 +#define CLKID_CDAC_DIV 231 +#define CLKID_CDAC 232 +#define CLKID_DEMOD_CORE_SEL 233 +#define CLKID_DEMOD_CORE_DIV 234 +#define CLKID_DEMOD_CORE 235 +#define CLKID_ADC_EXTCLK_IN_SEL 236 +#define CLKID_ADC_EXTCLK_IN_DIV 237 +#define CLKID_ADC_EXTCLK_IN 238 =20 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Tue Oct 7 01:58:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5E672264A9; Tue, 15 Jul 2025 12:51:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752583903; cv=none; b=ZcAY7/yYOpOXRb2MfuY8qYStsaDAdF30ZB03njK7v863r1HZYXIeWFx2fKDWyZWfn+6MgRgNUc6SzrzmRo7DoaZds5xpkODta5u7vpdybGOC3LCXKLxRu+K83pT0XAYg1/+9XeGkJRjbSNVDJxJQLOqlDmyCnkkE9WeA+Dv/HyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752583903; c=relaxed/simple; bh=85dpZxDXnCCzOPyZ7BS5N9GgXCmsv2H8dUvkNv/cJN0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tUpcKnwVPGZhVde93ZV3svXLlzMoKix1bOx1DYrbgQvZoCqnJWsZypmWebST96aA5kI7+/lnQmwddXk/lsJGhgvbD/wUXQRFEd59NZPz4nYOIHzyCdrV5Xh5Ng3SoOd0EjoHYc970XpR6pvAHXjxqYzy3oYMwoBNXTrmiybzZBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pe5MYIjP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pe5MYIjP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 760A5C4CEF1; Tue, 15 Jul 2025 12:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752583903; bh=85dpZxDXnCCzOPyZ7BS5N9GgXCmsv2H8dUvkNv/cJN0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pe5MYIjPKmTHjoFFQpWcLcj+S+aKet22gikbF2F7h+s0vRasKsX5F321Wth68tjnY TlNWeJ90IW11QdLL2vJ/4js5WXJ8qxAhzTsiVUV0pNTEisT6DJm/L9p+4SLYJmcpyS 4+FtOXk6yz+uh3L1s0SIl3rf891P5ZXdIg7ZCtKIGHbQybPVx4MQYmOr0e6V+fQ/VJ QxydYep9eHnr8PDSNtCX34nDfL1Zo5tLlH4Bb8HXbIf4p5CEB1W/y+JxqNIoCE7UhN 2xruvgMElJeIzOP1SjJbGIMnfZq8ixuesGXkqm/Og8KqrBvTJZeIM19t8yKEp2iV2N LuPMy4LZBG0og== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 666B9C83F27; Tue, 15 Jul 2025 12:51:43 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 15 Jul 2025 20:51:39 +0800 Subject: [PATCH 2/2] clk: amlogic: add video-related clocks for S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250715-add_video_clk-v1-2-40e7f633f361@amlogic.com> References: <20250715-add_video_clk-v1-0-40e7f633f361@amlogic.com> In-Reply-To: <20250715-add_video_clk-v1-0-40e7f633f361@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752583900; l=8635; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=Krtad04/LG3f+yownUO/6hPuVzIprI6Y8mPsJSZ7oMw=; b=jMVksC6mymjR/byiSiIbxFAfx7pwBYMaXcaQETql3fxq9FmaUM3nN9ryk8syF2Odt2oCBZWxJ RjEY4HOiEX0BWIlX5Euy1Nr9fgwZqRu9fMde0pvZjR6DRkHeT2LdkmL X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 256 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 256 insertions(+) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index c9400cf54c84..f43526d506b1 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -44,6 +44,7 @@ #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 #define CLKCTRL_VAPBCLK_CTRL 0x0fc #define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_CDAC_CLK_CTRL 0x108 #define CLKCTRL_VDEC_CLK_CTRL 0x140 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 @@ -1117,6 +1118,22 @@ static struct clk_regmap s4_cts_encp_sel =3D { }, }; =20 +static struct clk_regmap s4_cts_encl_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D mux_table_cts_sel, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cts_encl_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D s4_cts_parent_hws, + .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VIID_CLK_DIV, @@ -1196,6 +1213,22 @@ static struct clk_regmap s4_cts_encp =3D { }, }; =20 +static struct clk_regmap s4_cts_encl =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_encl", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cts_encl_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VID_CLK_CTRL2, @@ -1228,6 +1261,56 @@ static struct clk_regmap s4_hdmi_tx =3D { }, }; =20 +static struct clk_regmap s4_lcd_an_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_VIID_CLK_DIV, + .mask =3D 0x1, + .shift =3D 11, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "lcd_an_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_vclk_div6.hw, + &s4_vclk_div12.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_lcd_an_ph2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "lcd_an_ph2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_lcd_an_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_lcd_an_ph3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "lcd_an_ph3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_lcd_an_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + /* HDMI Clocks */ static const struct clk_parent_data s4_hdmi_parent_data[] =3D { { .fw_name =3D "xtal", }, @@ -3174,6 +3257,165 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +/* CVBS DAC */ +static struct clk_regmap s4_cdac_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fclk_div5" }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap s4_cdac_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .shift =3D 0, + .width =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_cdac =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "fclk_div4" } + }, + .num_parents =3D 3, + }, +}; + +static struct clk_regmap s4_demod_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 8 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* CVBS ADC */ +static struct clk_regmap s4_adc_extclk_in_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div4" }, + { .fw_name =3D "fclk_div3" }, + { .fw_name =3D "fclk_div5" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "gp0_pll" }, + { .fw_name =3D "hifi_pll" } + }, + .num_parents =3D 8, + }, +}; + +static struct clk_regmap s4_adc_extclk_in_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_adc_extclk_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 24 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) =20 @@ -3453,6 +3695,20 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_mux.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk_gate.hw, + [CLKID_CTS_ENCL_SEL] =3D &s4_cts_encl_sel.hw, + [CLKID_CTS_ENCL] =3D &s4_cts_encl.hw, + [CLKID_LCD_AN_SEL] =3D &s4_lcd_an_sel.hw, + [CLKID_LCD_AN_PH2] =3D &s4_lcd_an_ph2.hw, + [CLKID_LCD_AN_PH3] =3D &s4_lcd_an_ph3.hw, + [CLKID_CDAC_SEL] =3D &s4_cdac_sel.hw, + [CLKID_CDAC_DIV] =3D &s4_cdac_div.hw, + [CLKID_CDAC] =3D &s4_cdac.hw, + [CLKID_DEMOD_CORE_SEL] =3D &s4_demod_core_sel.hw, + [CLKID_DEMOD_CORE_DIV] =3D &s4_demod_core_div.hw, + [CLKID_DEMOD_CORE] =3D &s4_demod_core.hw, + [CLKID_ADC_EXTCLK_IN_SEL] =3D &s4_adc_extclk_in_sel.hw, + [CLKID_ADC_EXTCLK_IN_DIV] =3D &s4_adc_extclk_in_div.hw, + [CLKID_ADC_EXTCLK_IN] =3D &s4_adc_extclk_in.hw, }; =20 static const struct regmap_config clkc_regmap_config =3D { --=20 2.42.0