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Signed-off-by: Sirius Wang Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..5052b6b2dcce 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -382,6 +382,10 @@ properties: - enum: - mediatek,mt8188-evb - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8189-evb + - const: mediatek,mt8189 - description: Google Hayato items: - const: google,hayato-rev1 --=20 2.45.2 From nobody Tue Oct 7 05:24:03 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 657AD2550AD; Mon, 14 Jul 2025 14:06:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752501998; cv=none; b=u0hX4i8mFT5Y7glwjLoWMKFfavlaVtz3PKalvy/zpTDElEkkE+lanBhF3eKlL7gZudpqNyaixaL5nHEKdAAoSWbWK1GWiSq0q5Hdg2KA7IORofAVQ8uJj7Qo19lpkzSOPQFfnslESWySjiFvfjvsxAtu/+JpMSW1Qd5ubvnq0mQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752501998; c=relaxed/simple; bh=7Ju6plKMJMc0zJ4PWMDTZGyvZyNEEJ9TALEk+Pw7ChY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=doiprhZF0jiMQlOQOSRKvxZ2GKqTxpbZb4SIzxk64YzYx9AR/Wp/7l3WQh5uhw+sDPjQSLPafeYqhEXYR6ybPImTnWxlT8e0jrrGV3JGyz8IVSXF0Q7d+x9HAEcoZuAYqyvAU843iLa5tihf9UgKbO/lBmooSrb2tkD0OApSWLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=sUJx3qpk; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sUJx3qpk" X-UUID: bd078ed060bb11f0b1510d84776b8c0b-20250714 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qTk3CaUjrlXYE6puZpLxm2dSmQaEjt3CJufwyvSfla8=; b=sUJx3qpkz9ecB9halxJTf0+gV/VB20WYq2j4frRBTZJ/cTsLJRrgh0RSG/YH5uFhU82GhOKmrXXGXmXIzJYTY/ZqYQ93COBg21keZJ5hx/35ste4HF/DGobv7e2aRTt7Y8If3Ubqos9FfRVH5XTCWXUSTUnU/2E57BesDRpdvvE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:d8aea03d-7ebe-4581-bb1a-aa06123dc3ef,IP:0,UR L:0,TC:0,Content:46,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:46 X-CID-META: VersionHash:9eb4ff7,CLOUDID:8d2c30d8-b768-4ffb-8a44-cd8427608ba6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:3|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: bd078ed060bb11f0b1510d84776b8c0b-20250714 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 884187858; Mon, 14 Jul 2025 22:06:29 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 14 Jul 2025 22:06:27 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 14 Jul 2025 22:06:27 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang , Conor Dooley Subject: [PATCH v4 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 Date: Mon, 14 Jul 2025 22:06:04 +0800 Message-ID: <20250714140608.2065966-3-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250714140608.2065966-1-sirius.wang@mediatek.com> References: <20250714140608.2065966-1-sirius.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string for serial on MT8189 SoC. Signed-off-by: Sirius Wang Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/= Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 5bd8a8853ae0..3f0f4aea0a4c 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -47,6 +47,7 @@ properties: - mediatek,mt8183-uart - mediatek,mt8186-uart - mediatek,mt8188-uart + - mediatek,mt8189-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8365-uart --=20 2.45.2 From nobody Tue Oct 7 05:24:03 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B932550AD; Mon, 14 Jul 2025 14:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add mt8189 dts evaluation board and Mafefile Signed-off-by: Sirius Wang --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 + arch/arm64/boot/dts/mediatek/mt8189.dtsi | 419 ++++++++++++++++++++ 3 files changed, 440 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index a4df4c21399e..52c5b799308e 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku4.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku6.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku7.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8189-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8189-evb.dts new file mode 100644 index 000000000000..e5d9ce1b8e61 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sirius Wang + */ +/dts-v1/; +#include "mt8189.dtsi" + +/ { + model =3D "MediaTek MT8189 evaluation board"; + compatible =3D "mediatek,mt8189-evb", "mediatek,mt8189"; + + chosen: chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts= /mediatek/mt8189.dtsi new file mode 100644 index 000000000000..a484a40a036c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#include +#include + +/ { + compatible =3D "mediatek,mt8189"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + }; + + clk32k: oscillator-clk32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32000>; + clock-output-names =3D "clk32k"; + }; + + clk13m: oscillator-clk13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <1>; + clock-div =3D <2>; + clock-output-names =3D "clk13m"; + }; + + clk26m: oscillator-clk26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk104m: oscillator-clk104m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <4>; + clock-div =3D <1>; + clock-output-names =3D "clk104m"; + }; + + ulposc: oscillator-ulposc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <520000000>; + clock-output-names =3D "ulposc"; + }; + + ulposc3: oscillator-ulposc3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "ulposc3"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <742>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <742>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <742>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <742>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <742>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <742>; + cpu-idle-states =3D <&cpu_off_l>, <&cpu_s2idle>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x600>; + enable-method =3D "psci"; + clock-frequency =3D <3000000000>; + capacity-dmips-mhz =3D <958>; + cpu-idle-states =3D <&cpu_off_b>, <&cpu_s2idle>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x700>; + enable-method =3D "psci"; + clock-frequency =3D <3000000000>; + capacity-dmips-mhz =3D <958>; + cpu-idle-states =3D <&cpu_off_b>, <&cpu_s2idle>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + core4 { + cpu =3D <&cpu4>; + }; + core5 { + cpu =3D <&cpu5>; + }; + core6 { + cpu =3D <&cpu6>; + }; + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <25>; + exit-latency-us =3D <57>; + min-residency-us =3D <5700>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <35>; + exit-latency-us =3D <82>; + min-residency-us =3D <1890>; + }; + + cpu_cluster_off_l: cpu-cluster-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010001>; + local-timer-stop; + entry-latency-us =3D <57>; + exit-latency-us =3D <134>; + min-residency-us =3D <5700>; + }; + + cpu_cluster_off_b: cpu-cluster-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010001>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <144>; + min-residency-us =3D <2460>; + }; + + cpu_mcusys_off_l: cpu-mcusys-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x02010007>; + local-timer-stop; + entry-latency-us =3D <863>; + exit-latency-us =3D <1237>; + min-residency-us =3D <5700>; + }; + + cpu_mcusys_off_b: cpu-mcusys-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x02010007>; + local-timer-stop; + entry-latency-us =3D <648>; + exit-latency-us =3D <1172>; + min-residency-us =3D <4570>; + }; + + cpu_system_vcore: cpu-system-vcore { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x020100ff>; + local-timer-stop; + entry-latency-us =3D <2400>; + exit-latency-us =3D <4800>; + min-residency-us =3D <35200>; + }; + + cpu_s2idle: cpu-s2idle { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x020180ff>; + local-timer-stop; + entry-latency-us =3D <10000>; + exit-latency-us =3D <10000>; + min-residency-us =3D <4294967295>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + }; + }; + + memory: memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0xc0000000>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer: timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + performance: performance-controller@11bc10 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells =3D <1>; + }; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu6 &cpu7>; + }; + }; + }; + + uart0: serial@11001000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + }; +}; --=20 2.45.2