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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e949f2sm787867166b.34.2025.07.14.01.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 01:17:44 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 1/3] drivers: cpufreq: add Tegra114 support Date: Mon, 14 Jul 2025 11:17:11 +0300 Message-ID: <20250714081713.8409-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250714081713.8409-1-clamor95@gmail.com> References: <20250714081713.8409-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra114 is fully compatible with existing Tegra124 cpufreq driver. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Thierry Reding --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra124-cpufreq.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index a010da0f6337..015dd393eaba 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -143,6 +143,7 @@ static const struct of_device_id blocklist[] __initcons= t =3D { =20 { .compatible =3D "nvidia,tegra20", }, { .compatible =3D "nvidia,tegra30", }, + { .compatible =3D "nvidia,tegra114", }, { .compatible =3D "nvidia,tegra124", }, { .compatible =3D "nvidia,tegra210", }, { .compatible =3D "nvidia,tegra234", }, diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-= cpufreq.c index 514146d98bca..6ff2ccc08e5e 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -189,8 +189,9 @@ static int __init tegra_cpufreq_init(void) int ret; struct platform_device *pdev; =20 - if (!(of_machine_is_compatible("nvidia,tegra124") || - of_machine_is_compatible("nvidia,tegra210"))) + if (!(of_machine_is_compatible("nvidia,tegra114") || + of_machine_is_compatible("nvidia,tegra124") || + of_machine_is_compatible("nvidia,tegra210"))) return -ENODEV; =20 /* --=20 2.48.1 From nobody Tue Oct 7 05:42:08 2025 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6B9323D285; Mon, 14 Jul 2025 08:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752481070; cv=none; b=fzQw/n3QS78EfFirURcM0Ir/6lynHMGSktEvoFhAv4zwHUEYhMYzabxaBc2NZyqYTDYdoDydU83KdXSP29/q1tFhTOan68R2hG9tD5K785D5p0hv6qR5y26CQnmoc3fxCV5rTI/czad0VSBQZnGkn/12KpDnlErMiT0r3vk8zeg= ARC-Message-Signature: i=1; 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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e949f2sm787867166b.34.2025.07.14.01.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 01:17:46 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 2/3] clk: tegra: add DFLL support for Tegra114 Date: Mon, 14 Jul 2025 11:17:12 +0300 Message-ID: <20250714081713.8409-3-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250714081713.8409-1-clamor95@gmail.com> References: <20250714081713.8409-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the Tegra124 driver to include DFLL configuration settings required for Tegra114 compatibility. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 - include/dt-bindings/reset/tegra114-car.h | 13 +++ 5 files changed, 144 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/reset/tegra114-car.h diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig index 90df619dc087..62147a069606 100644 --- a/drivers/clk/tegra/Kconfig +++ b/drivers/clk/tegra/Kconfig @@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP depends on TEGRA_BPMP =20 config TEGRA_CLK_DFLL - depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC + depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC select PM_OPP def_bool y =20 diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra= 114.c index 73303458e886..126c0a55a6d0 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "clk.h" #include "clk-id.h" @@ -1272,7 +1273,7 @@ EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); * * Assert the reset line of the DFLL's DVCO. No return value. */ -void tegra114_clock_assert_dfll_dvco_reset(void) +static void tegra114_clock_assert_dfll_dvco_reset(void) { u32 v; =20 @@ -1281,7 +1282,6 @@ void tegra114_clock_assert_dfll_dvco_reset(void) writel_relaxed(v, clk_base + RST_DFLL_DVCO); tegra114_car_barrier(); } -EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); =20 /** * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset @@ -1289,7 +1289,7 @@ EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to * operate. No return value. */ -void tegra114_clock_deassert_dfll_dvco_reset(void) +static void tegra114_clock_deassert_dfll_dvco_reset(void) { u32 v; =20 @@ -1298,7 +1298,26 @@ void tegra114_clock_deassert_dfll_dvco_reset(void) writel_relaxed(v, clk_base + RST_DFLL_DVCO); tegra114_car_barrier(); } -EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); + +static int tegra114_reset_assert(unsigned long id) +{ + if (id =3D=3D TEGRA114_RST_DFLL_DVCO) + tegra114_clock_assert_dfll_dvco_reset(); + else + return -EINVAL; + + return 0; +} + +static int tegra114_reset_deassert(unsigned long id) +{ + if (id =3D=3D TEGRA114_RST_DFLL_DVCO) + tegra114_clock_deassert_dfll_dvco_reset(); + else + return -EINVAL; + + return 0; +} =20 static void __init tegra114_clock_init(struct device_node *np) { @@ -1344,6 +1363,9 @@ static void __init tegra114_clock_init(struct device_= node *np) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, &pll_x_params); =20 + tegra_init_special_resets(1, tegra114_reset_assert, + tegra114_reset_deassert); + tegra_add_of_provider(np, of_clk_src_onecell_get); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); =20 diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra= /clk-tegra124-dfll-fcpu.c index 0251618b82c8..7a43380ce519 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -28,6 +28,99 @@ struct dfll_fcpu_data { unsigned int cpu_cvb_tables_size; }; =20 +/* Maximum CPU frequency, indexed by CPU speedo id */ +static const unsigned long tegra114_cpu_max_freq_table[] =3D { + [0] =3D 2040000000UL, + [1] =3D 1810500000UL, + [2] =3D 1912500000UL, + [3] =3D 1810500000UL, +}; + +#define T114_CPU_CVB_TABLE \ + .min_millivolts =3D 1000, \ + .max_millivolts =3D 1320, \ + .speedo_scale =3D 100, \ + .voltage_scale =3D 1000, \ + .entries =3D { \ + { 306000000UL, { 2190643, -141851, 3576 } }, \ + { 408000000UL, { 2250968, -144331, 3576 } }, \ + { 510000000UL, { 2313333, -146811, 3576 } }, \ + { 612000000UL, { 2377738, -149291, 3576 } }, \ + { 714000000UL, { 2444183, -151771, 3576 } }, \ + { 816000000UL, { 2512669, -154251, 3576 } }, \ + { 918000000UL, { 2583194, -156731, 3576 } }, \ + { 1020000000UL, { 2655759, -159211, 3576 } }, \ + { 1122000000UL, { 2730365, -161691, 3576 } }, \ + { 1224000000UL, { 2807010, -164171, 3576 } }, \ + { 1326000000UL, { 2885696, -166651, 3576 } }, \ + { 1428000000UL, { 2966422, -169131, 3576 } }, \ + { 1530000000UL, { 3049183, -171601, 3576 } }, \ + { 1606500000UL, { 3112179, -173451, 3576 } }, \ + { 1708500000UL, { 3198504, -175931, 3576 } }, \ + { 1810500000UL, { 3304747, -179126, 3576 } }, \ + { 1912500000UL, { 3395401, -181606, 3576 } }, \ + { 0UL, { 0, 0, 0 } }, \ + }, \ + .cpu_dfll_data =3D { \ + .tune0_low =3D 0x00b0039d, \ + .tune0_high =3D 0x00b0009d, \ + .tune1 =3D 0x0000001f, \ + .tune_high_min_millivolts =3D 1050, \ + } + +static const struct cvb_table tegra114_cpu_cvb_tables[] =3D { + { + .speedo_id =3D 0, + .process_id =3D -1, + .min_millivolts =3D 1000, + .max_millivolts =3D 1250, + .speedo_scale =3D 100, + .voltage_scale =3D 100, + .entries =3D { + { 306000000UL, { 107330, -1569, 0 } }, + { 408000000UL, { 111250, -1666, 0 } }, + { 510000000UL, { 110000, -1460, 0 } }, + { 612000000UL, { 117290, -1745, 0 } }, + { 714000000UL, { 122700, -1910, 0 } }, + { 816000000UL, { 125620, -1945, 0 } }, + { 918000000UL, { 130560, -2076, 0 } }, + { 1020000000UL, { 137280, -2303, 0 } }, + { 1122000000UL, { 146440, -2660, 0 } }, + { 1224000000UL, { 152190, -2825, 0 } }, + { 1326000000UL, { 157520, -2953, 0 } }, + { 1428000000UL, { 166100, -3261, 0 } }, + { 1530000000UL, { 176410, -3647, 0 } }, + { 1632000000UL, { 189620, -4186, 0 } }, + { 1734000000UL, { 203190, -4725, 0 } }, + { 1836000000UL, { 222670, -5573, 0 } }, + { 1938000000UL, { 256210, -7165, 0 } }, + { 2040000000UL, { 250050, -6544, 0 } }, + { 0UL, { 0, 0, 0 } }, + }, + .cpu_dfll_data =3D { + .tune0_low =3D 0x00b0019d, + .tune0_high =3D 0x00b0019d, + .tune1 =3D 0x0000001f, + .tune_high_min_millivolts =3D 1000, + } + }, + { + .speedo_id =3D 1, + .process_id =3D -1, + T114_CPU_CVB_TABLE + }, + { + .speedo_id =3D 2, + .process_id =3D -1, + T114_CPU_CVB_TABLE + }, + { + .speedo_id =3D 3, + .process_id =3D -1, + T114_CPU_CVB_TABLE + }, +}; + /* Maximum CPU frequency, indexed by CPU speedo id */ static const unsigned long tegra124_cpu_max_freq_table[] =3D { [0] =3D 2014500000UL, @@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { }, }; =20 +static const struct dfll_fcpu_data tegra114_dfll_fcpu_data =3D { + .cpu_max_freq_table =3D tegra114_cpu_max_freq_table, + .cpu_max_freq_table_size =3D ARRAY_SIZE(tegra114_cpu_max_freq_table), + .cpu_cvb_tables =3D tegra114_cpu_cvb_tables, + .cpu_cvb_tables_size =3D ARRAY_SIZE(tegra114_cpu_cvb_tables) +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data =3D { .cpu_max_freq_table =3D tegra124_cpu_max_freq_table, .cpu_max_freq_table_size =3D ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -509,6 +609,10 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_= data =3D { }; =20 static const struct of_device_id tegra124_dfll_fcpu_of_match[] =3D { + { + .compatible =3D "nvidia,tegra114-dfll", + .data =3D &tegra114_dfll_fcpu_data, + }, { .compatible =3D "nvidia,tegra124-dfll", .data =3D &tegra124_dfll_fcpu_data, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 5d80d8b79b8e..58e860b18e5e 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -898,8 +898,6 @@ static inline bool tegra124_clk_emc_driver_available(st= ruct clk_hw *emc_hw) void tegra114_clock_tune_cpu_trimmers_high(void); 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([188.163.112.60]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e949f2sm787867166b.34.2025.07.14.01.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 01:17:47 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 3/3] ARM: tegra: Add DFLL clock support on Tegra114 Date: Mon, 14 Jul 2025 11:17:13 +0300 Message-ID: <20250714081713.8409-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250714081713.8409-1-clamor95@gmail.com> References: <20250714081713.8409-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DFLL clock node to common Tegra114 device tree along with clocks property to cpu node. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 4caf2073c556..3ee51d7f3935 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 / { @@ -693,6 +694,30 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells =3D <1>; }; =20 + dfll: clock@70110000 { + compatible =3D "nvidia,tegra114-dfll"; + reg =3D <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names =3D "soc", "ref", "i2c"; + resets =3D <&tegra_car TEGRA114_RST_DFLL_DVCO>; + reset-names =3D "dvco"; + #clock-cells =3D <0>; + clock-output-names =3D "dfllCPU_out"; + nvidia,sample-rate =3D <11500>; + nvidia,droop-ctrl =3D <0x00000f00>; + nvidia,force-mode =3D <1>; + nvidia,cf =3D <10>; + nvidia,ci =3D <0>; + nvidia,cg =3D <2>; + status =3D "disabled"; + }; + mmc@78000000 { compatible =3D "nvidia,tegra114-sdhci"; reg =3D <0x78000000 0x200>; @@ -824,6 +849,15 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0>; + + clocks =3D <&tegra_car TEGRA114_CLK_CCLK_G>, + <&tegra_car TEGRA114_CLK_CCLK_LP>, + <&tegra_car TEGRA114_CLK_PLL_X>, + <&tegra_car TEGRA114_CLK_PLL_P>, + <&dfll>; + clock-names =3D "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency =3D <300000>; }; =20 cpu1: cpu@1 { --=20 2.48.1