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charset="utf-8" The gcc_aux_clk is not required by the PCIe PHY on qcs8300 and is not specified in the device tree node. Hence, move the qcs8300 phy compatibility entry into the list of PHYs that require six clocks. Fixes: e46e59b77a9e ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Documen= t the QCS8300 QMP PCIe PHY Gen4 x2") Fixes: Fixes: fd2d4e4c1986 ("dt-bindings: phy: qcom,qmp: Add sa8775p QMP PC= Ie PHY") Signed-off-by: Ziyue Zhang Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 2c6c9296e4c0..1d4815056bc2 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -176,6 +176,7 @@ allOf: contains: enum: - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy @@ -196,7 +197,6 @@ allOf: compatible: contains: enum: - - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy then: --=20 2.34.1 From nobody Tue Oct 7 05:44:11 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4DDF23AB81; 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charset="utf-8" Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 172 +++++++++++++++++++++++++- 1 file changed, 171 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 7ada029c32c1..7b7009567999 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -619,7 +619,7 @@ gcc: clock-controller@100000 { #power-domain-cells =3D <1>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, + <&pcie0_phy>, <0>, <0>, <0>, @@ -1966,6 +1966,176 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + pcie0: pci@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie3_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + }; + }; + }; + + pcie0_phy: phy@1c04000 { + compatible =3D "qcom,qcs8300-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x01c04000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 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charset="utf-8" Add configurations in devicetree for PCIe0, board related gpios, PMIC regulators, etc for qcs8300-ride board. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 8c166ead912c..e8e382db2b99 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -308,6 +308,23 @@ &iris { status =3D "okay"; }; =20 +&pcie0 { + perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l6a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -348,6 +365,29 @@ ethernet0_mdio: ethernet0-mdio-pins { bias-pull-up; }; }; + + pcie0_default_state: pcie0-default-state { + wake-pins { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; }; =20 &uart7 { --=20 2.34.1 From nobody Tue Oct 7 05:44:11 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4E4423AB94; Mon, 14 Jul 2025 08:15:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480950; cv=none; b=p2mIp8uG/kI/MtP8V9OrZBdd+Ck/Y2lveN6xkNJzbmBLoSsFK0FQvnNuiqrod296uc/reMpQc+wpjdpGc3WFHywiCRhwuqvUUfG6E1+jmN8VuI/ptxNN43qi3bTOEbaTnP/qclVHDlMsBHEKS4FmTYYCxotUO2DFrcM6QE5PzBs= ARC-Message-Signature: i=1; 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charset="utf-8" Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s. Acked-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 124 +++++++++++++++++++++++++- 1 file changed, 123 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 7b7009567999..0dc536494ac7 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -620,7 +620,7 @@ gcc: clock-controller@100000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <0>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -2136,6 +2136,128 @@ pcie0_phy: phy@1c04000 { status =3D "disabled"; }; =20 + pcie1: pci@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + num-lanes =3D <4>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_1_GDSC>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg =3D <0x0 0x01c14000 0x0 0x4000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 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Mon, 14 Jul 2025 08:15:36 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 56E8FYPx026711; Mon, 14 Jul 2025 08:15:34 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 47ugsm629x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Jul 2025 08:15:34 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 56E8FY28026699; Mon, 14 Jul 2025 08:15:34 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (cse-cd01-lnx.qualcomm.com [10.64.75.209]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 56E8FY9Z026697 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Jul 2025 08:15:34 +0000 Received: by cse-cd01-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 1AFDA20F96; Mon, 14 Jul 2025 16:15:31 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Konrad Dybcio Subject: [PATCH v8 5/5] arm64: dts: qcom: qcs8300-ride: enable pcie1 interface Date: Mon, 14 Jul 2025 16:15:29 +0800 Message-Id: <20250714081529.3847385-6-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com> References: <20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=EbLIQOmC c=1 sm=1 tr=0 ts=6874bca9 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=0LYZJ8Fh9g_wO_RM1qMA:9 X-Proofpoint-GUID: cwjD0diNzdKReQSggratB4sPuMmzpLKN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDA0OCBTYWx0ZWRfX9/eF5C1DB0rp 7ACwk9dMc1CRrexfUz90YDb3RjXSwwoUo66BXFPmhHgYTCWHiB0H88laBuypaEoJyPEFOKjJy14 Ac1ofnkBPLRfBfxhTh+Z7U7e6ptfAmC9O65lf3BnfEoTVMaKQtWk2Wbh6kiUKG/juKHfgn1NJe9 cK6ZPcactWdGIxj4fApzi52yRdwFtOrH+foGrp+NmR4LCeJ/NaB1W2Oc3xsp0Jex9G1KWsHHFaD 2r+jtd0adfgjQhvookzL4gamjjpK+GvtS2ke/k8A9jIFoEWNftDcqT50PmELTBoqlMQb3y1BuvL O9onF/yuKuwWi0lo/raWSKEnaeH3rvGjMbE4oc2lBsZhFSh9pnMww1KR3/MpFzn+wrJSi0nHIDH j+F9R7NAB2dGkDkjSOb9FZ8w06QTsrCc2zMcMYt+mhF+xkkC+NJeW796EFSsrO7OLs1a7Ty6 X-Proofpoint-ORIG-GUID: cwjD0diNzdKReQSggratB4sPuMmzpLKN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 suspectscore=0 impostorscore=0 adultscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140048 Content-Type: text/plain; charset="utf-8" Add configurations in devicetree for PCIe1, board related gpios, PMIC regulators, etc for qcs8300-ride platform. Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index e8e382db2b99..bec2905c5d8f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -325,6 +325,23 @@ &pcie0_phy { status =3D "okay"; }; =20 +&pcie1 { + perst-gpios =3D <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 21 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l6a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -388,6 +405,29 @@ perst-pins { bias-pull-down; }; }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio22"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; }; =20 &uart7 { --=20 2.34.1