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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:21 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Date: Mon, 14 Jul 2025 14:31:00 +0800 Message-Id: <20250714063109.591-2-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfX+2N8qWlhrXoe tWxx9qAYSyC3Is0LF9bEmeXqQoB8kMk23ggHJuex8DCsGuUExhEA/ws7aoGCtWmJU90eWI6O5n4 IVy02MmuXSH6YPEMTA/h6s5Myx2kD9A34n+KcS9nMF9Rdf1WcFmXdwqHc6kd+Dh7RIAip+tfD1X NQuCyZhhV+1K5LJDLFSyS8DzaUXV8Vl2AHhF1aI9ELu//3mbuYcIXOFgrL2/qkzzNbVvZEmfbb7 oRXxp6tW68tGCsViSgy1hfYdNBbcT2tPeRwMqhMPvX+snoqWd86xcK9JWN3cDUFLjCQlB+4KHux E8aWpmgwnfOHzZGlCNLzbVJurHnRgZ38WJA69cnjDdktLCY93zTwvbUqkFYqEkx79KOM/Ve/93N WaDJW3mQ2jsacVgx6qengfQ/c9Rl6x0RSUfz2kkEeREZqiG68PcgwbXu6e1Wx6EME7tFUlIO X-Proofpoint-GUID: t2uKd4qgogmFhgj_por-6mtXxy_O8cj_ X-Authority-Analysis: v=2.4 cv=RPSzH5i+ c=1 sm=1 tr=0 ts=6874a43b cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=UMME_An3wchvczm7DuYA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: t2uKd4qgogmFhgj_por-6mtXxy_O8cj_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Remove ctcu_get_active_port from CTCU module and add it to the core framework. The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 19 +-------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 1accd7cbd54b..5297a5ff7921 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -580,6 +580,30 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_port_helper: get the in-port number of the helper device + * that is connected to the csdev. + * + * @csdev: csdev of the device that is connected to helper. + * @helper: csdev of the helper device. + * + * Return: port number upson success or -EINVAL for fail. + */ +int coresight_get_port_helper(struct coresight_device *csdev, + struct coresight_device *helper) +{ + struct coresight_platform_data *pdata =3D helper->pdata; + int i; + + for (i =3D 0; i < pdata->nr_inconns; ++i) { + if (pdata->in_conns[i]->src_dev =3D=3D csdev) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_port_helper); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index c6bafc96db96..28ea4a216345 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -118,23 +118,6 @@ static int __ctcu_set_etr_traceid(struct coresight_dev= ice *csdev, u8 traceid, in return 0; } =20 -/* - * Searching the sink device from helper's view in case there are multiple= helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) -{ - struct coresight_platform_data *pdata =3D helper->pdata; - int i; - - for (i =3D 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev =3D=3D sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct cor= esight_path *path, bool enable) { @@ -147,7 +130,7 @@ static int ctcu_set_etr_traceid(struct coresight_device= *csdev, struct coresight return -EINVAL; } =20 - port_num =3D ctcu_get_active_port(sink, csdev); + port_num =3D coresight_get_port_helper(sink, csdev); if (port_num < 0) return -EINVAL; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 33e22b1ba043..07a5f03de81d 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -156,6 +156,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_port_helper(struct coresight_device *csdev, + struct coresight_device *helper); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:26 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 02/10] coresight: core: add a new API to retrieve the helper device Date: Mon, 14 Jul 2025 14:31:01 +0800 Message-Id: <20250714063109.591-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfXwXUsETsQyY+Y ygl3bZaYPqYk22m5Z+7NRsk7XA955NviySO8+vn8PmYB7V184SOq5U2chGUavBwB9jwNLcHJPSy 0dbT66lL7cMJWaDHstfX46+Dd8biizhcJIYyI4xspaKu4P2jdmECBumvPA4e9CZz5vLhgcjjR2B OH0f/F4aIpYFa6e9nRGmwxR2lUFjN6+1FDEC2DySPowS2fdwM2T457ju4fbY8+r87vaZjI+P0L8 ZUFcosb6KdvJLyHAcVqZyS4UMYCpLz+UGfz8/JkqD5NB9VM9er4Wahbr3V/7EH44yNtDHEwrgln B/hVNkr7u6wq63fhVGpqYQl8woAB3ib9tgF82OIHoetofBH0vErck+IwgF2dFapFCWbFUJgDGLW FzLgDJuceq607OO1BlSYV4hEvDSNv2FUeTrFtb7k9j5bGyWRRdj18uGZQb976MAmVnO4HDP7 X-Proofpoint-ORIG-GUID: mvqwxWX2QiZiKZwg3boAW1V5eDxCKMhm X-Proofpoint-GUID: mvqwxWX2QiZiKZwg3boAW1V5eDxCKMhm X-Authority-Analysis: v=2.4 cv=f59IBPyM c=1 sm=1 tr=0 ts=6874a440 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=Bv2r1u00ER1ubdDhqu4A:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Retrieving the helper device of the specific coresight device based on its helper_subtype because a single coresight device may has multiple types of the helper devices. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 30 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 5297a5ff7921..76e10c36a8a1 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -580,6 +580,36 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_helper: find the helper device of the assigned csdev. + * + * @csdev: The csdev the helper device is conntected to. + * @type: helper_subtype of the expected helper device. + * + * Retrieve the helper device for the specific csdev based on its + * helper_subtype. + * + * Return: the helper's csdev upon success or NULL for fail. + */ +struct coresight_device *coresight_get_helper(struct coresight_device *csd= ev, + int type) +{ + int i; + struct coresight_device *helper; + + for (i =3D 0; i < csdev->pdata->nr_outconns; ++i) { + helper =3D csdev->pdata->out_conns[i]->dest_dev; + if (!helper || !coresight_is_helper(helper)) + continue; + + if (helper->subtype.helper_subtype =3D=3D type) + return helper; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(coresight_get_helper); + /** * coresight_get_port_helper: get the in-port number of the helper device * that is connected to the csdev. diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 07a5f03de81d..5b912eb60401 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -158,6 +158,8 @@ void coresight_path_assign_trace_id(struct coresight_pa= th *path, enum cs_mode mode); int coresight_get_port_helper(struct coresight_device *csdev, struct coresight_device *helper); +struct coresight_device *coresight_get_helper(struct coresight_device *csd= ev, + int type); =20 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) int etm_readl_cp14(u32 off, unsigned int *val); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:31 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 RESEND 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Date: Mon, 14 Jul 2025 14:31:02 +0800 Message-Id: <20250714063109.591-4-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=e7gGSbp/ c=1 sm=1 tr=0 ts=6874a445 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gSyxy6DGYGa4b6s9XCEA:9 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: sADxKO-VtzeVFcHrxdozNXiw0zWCSDFD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfX4+2gybPImGj/ B2YTrmDX/tuvnhESIJlZTlewAzRNdD5lbYSjGiauoPRDKQjwVfBG6oEBNf+sQiUqLA6qu2a1y+R Ffkd157As7ZkW9ah7SzVjdc1WeNvowypandmSlSDuTY2v8ynPwfHCT1vf19HiiAv7UdaAC61j+/ gToe2/nkYUljJIPVP5thyvoUrbrD2njTRN0m3C5CHUsQ0F1bxZHLYqHLidd6/oibR0kz2KxB971 MNwhKvutsXcTp/hEn2Zhfamafu2XvN0qIhnWNJ/uoHBJiwCzaviW0CEmo8tlTA2Sngs8XuL5sqZ Qwy0M5NodSS8sHR9+MuUnlGNCv8CNOiYwe68kP5r4o8zgK7K45coNhg8QKwyqjZZAyScwSy1l9W Tz6SOv7XBv3kY6TVmc9Iiy41vg9E5R6EMIa67uXYqwYJxdlHRB7SBZ7XGzzzCN4YkfCpr74y X-Proofpoint-ORIG-GUID: sADxKO-VtzeVFcHrxdozNXiw0zWCSDFD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Byte cntr interrupt for etr0 + - description: Byte cntr interrupt for etr1 + + interrupt-names: + items: + - const: etr0 + - const: etr1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -56,6 +66,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -63,6 +75,11 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:36 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Date: Mon, 14 Jul 2025 14:31:03 +0800 Message-Id: <20250714063109.591-5-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfXyCUnAy8biAIB a0aCPhMp6KuvXPWEdtdo9ACwLMNiX5Q4itbKKZ7eA+qyLoU1ZtkxQyoUxsmRf0lsjvsxaWnZEbq 2VYQ8psjzEcsWvS+L5d8c8xIA5Srg9EPjvpaYvXESMoVh/HnwSttB9dk3d5gf8ZCiH/e5nmNuAg WCocMuCUa06hNnWTquXU06rqyY0jJwNWJZIcojU0olUjKL1mAUrSO96tXK/564M6rk+Eg2GZo/e j4E6njfY1OegmYRAg41URIY5czv0/xmFpu8VoYzsaLEZ6nJCyYqjr4vZur15cruPEMCjV8/JwZr sfQ1tbiKrIQb0az98300g/TgMgNNLVXNpm4A0noT5n0OrsyXV3Nf7LsCTEW7eklqwJP0oQeOUMD 32S3FuiEzZtTFDB+b1Zmb/ec6RsrcxMeE5m4UP7i9TxBdLoGYPn3p9efN4LK0Eea8cizEYzv X-Proofpoint-ORIG-GUID: r4t4YxN2zCwox_Lf_RgDD_E_caWHRJZo X-Proofpoint-GUID: r4t4YxN2zCwox_Lf_RgDD_E_caWHRJZo X-Authority-Analysis: v=2.4 cv=f59IBPyM c=1 sm=1 tr=0 ts=6874a44b cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=QXWqZSVT-t1lZVDuzqIA:9 a=324X-CrmTo6CU4MGRt3R:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the ETR buffer. Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-ctcu | 5 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 102 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 94 +++++++++++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 49 ++++++++- 5 files changed, 246 insertions(+), 6 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-c= tcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..e21f5bcb8097 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,5 @@ +What: /sys/bus/coresight/devices//irq_val +Date: June 2025 +KernelVersion: 6.16 +Contact: Tingwei Zhang (QUIC) ; Jinlong = Mao (QUIC) ; Jie Gan +Description: (RW) Configure the IRQ value for byte-cntr register. diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 4e7cc3c5bf99..3568d9768567 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -54,5 +54,5 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..d3b6eb7a89fb --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + byte_cntr_data->irq_num++; + + return IRQ_HANDLED; +} + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink) + return; + + port_num =3D coresight_get_port_helper(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D true; + byte_cntr_data->reading_buf =3D false; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink || coresight_get_mode(sink) =3D=3D CS_MODE_SYSFS) + return; + + port_num =3D coresight_get_port_helper(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int byte_cntr_irq, ret, i; + + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + byte_cntr_irq =3D of_irq_get_byname(nd, byte_cntr_data->irq_name); + if (byte_cntr_irq < 0) { + dev_err(dev, "Failed to get IRQ from DT for %s\n", + byte_cntr_data->irq_name); + continue; + } + + ret =3D devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for %s\n", + byte_cntr_data->irq_name); + continue; + } + + byte_cntr_data->byte_cntr_irq =3D byte_cntr_irq; + disable_irq(byte_cntr_data->byte_cntr_irq); + init_waitqueue_head(&byte_cntr_data->wq); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 28ea4a216345..721836d42523 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include "coresight-ctcu.h" #include "coresight-priv.h" @@ -45,17 +46,23 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); =20 #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .irq_name =3D "etr0", + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .irq_name =3D "etr1", + .port_num =3D 1, }, }; =20 @@ -64,6 +71,76 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +static void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u= 32 offset) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_val_show(struct device *dev, struct device_attribute *a= ttr, + char *buf) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + int i, len =3D 0; + + for (i =3D 0; i < ETR_MAX_NUM; i++) { + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "%u ", + drvdata->byte_cntr_data[i].thresh_val); + } + + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +/* Program a valid value into IRQCTRL register will enable byte-cntr inter= rupt */ +static ssize_t irq_val_store(struct device *dev, struct device_attribute *= attr, + const char *buf, size_t size) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u32 thresh_vals[ETR_MAX_NUM] =3D { 0 }; + u32 irq_ctrl_offset; + int num, i; + + num =3D sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); + if (num <=3D 0 || num > ETR_MAX_NUM) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + for (i =3D 0; i < num; i++) { + /* A small threshold will result in a large number of interruptions */ + if (thresh_vals[i] && thresh_vals[i] < SZ_4K) + return -EINVAL; + + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { + drvdata->byte_cntr_data[i].thresh_val =3D thresh_vals[i]; + irq_ctrl_offset =3D drvdata->byte_cntr_data[i].irq_ctrl_offset; + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(drvdata, thresh_vals[i] / 8, irq_ctrl_offset); + } + } + + return size; +} +static DEVICE_ATTR_RW(irq_val); + +static struct attribute *ctcu_attrs[] =3D { + &dev_attr_irq_val.attr, + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -143,6 +220,8 @@ static int ctcu_enable(struct coresight_device *csdev, = enum cs_mode mode, void * { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 @@ -150,6 +229,8 @@ static int ctcu_disable(struct coresight_device *csdev,= void *data) { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -200,7 +281,11 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_name =3D etr_cfg->irq_name; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -212,6 +297,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata =3D pdata; desc.dev =3D dev; + desc.groups =3D ctcu_attr_grps; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); =20 diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..71266371591b 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,19 +5,27 @@ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 =20 +#define BYTE_CNTR_TIMEOUT (5 * HZ) + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; + const char *irq_name; }; =20 struct ctcu_config { @@ -25,15 +33,54 @@ struct ctcu_config { int num_etr_config; }; =20 +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @reading: indicates that its byte-cntr reading. + * @reading_buf: indicates that byte-cntr is reading buffer. + * @thresh_val: threshold to trigger a interruption. + * @total_size: total size of transferred data. + * @byte_cntr_irq: IRQ number. + * @irq_cnt: IRQ count. + * @irq_num: number of the byte_cntr IRQ for one session. + * @wq: workqueue of reading ETR data. + * @read_work: work of reading ETR data. + * @spin_lock: spinlock of byte cntr data. + * the byte cntr is stopped. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @irq_name: IRQ name in DT. + */ +struct ctcu_byte_cntr { + bool enable; + bool reading; + bool reading_buf; + u32 thresh_val; + u64 total_size; + int byte_cntr_irq; + atomic_t irq_cnt; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:41 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Date: Mon, 14 Jul 2025 14:31:04 +0800 Message-Id: <20250714063109.591-6-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfX4NSgq1K3GvYx 8jfRzaQgLpvzjBedBUSRFUWsjb3ADnKfBhIDzFXEGciVLOoDT93f390W3RiXQk9ak1elg96c2i5 yZh180AkMOTmaFieT0czUUFEk0cor4zI11M/HLoX0/txJjoFtHhAgHTqOBQt3Kef+6qPzliplzv er6DlLBIE99BVZiWewqlpJueJhJPhBhaqmPaV2RQr0hG/xwQWFRKYFyZaZPx9YvGThu4sDqlJeG mH/xaIArruSIKD/Fs86o9Byx34TVf61Plz6utMHVOdRPECbMqbTeUczQOPJf41B2v5zYlwF7hPU Y3VezzuJzhIyxk4PuMaxy4PV4lRPXWt1XW2FBlyGdmI19U/fkzz4esa3D7pGLWHPFEfPUbzHgtw WiM8QQkPuLnHn+p0BMhF9B/m3etBkLO30VE6ioB52hFdZ9gQKWg7RVx11aX8QR6eg6XrC76T X-Proofpoint-GUID: B2gedCh3n3Bsy2Qli0MuI7GZcK_4-OdX X-Authority-Analysis: v=2.4 cv=SZT3duRu c=1 sm=1 tr=0 ts=6874a44f cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ORm1qb0EFYpRwVLUulEA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: B2gedCh3n3Bsy2Qli0MuI7GZcK_4-OdX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Add a list to store allocated etr_buf. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tmc.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index be964656be93..4d249af93097 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -830,6 +830,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 6541a27a018e..f6b05639aeca 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,21 @@ struct tmc_resrv_buf { s64 len; }; =20 +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @reading: Indicates whether the buffer is reading. + * @pos: Position of the buffer. + * @node: Node in etr_buf_list. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + bool reading; + loff_t pos; + struct list_head node; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @pclk: APB clock if present, otherwise NULL @@ -242,6 +257,8 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. + * @reading_node: Available buffer for byte-cntr reading. */ struct tmc_drvdata { struct clk *pclk; @@ -271,6 +288,8 @@ struct tmc_drvdata { struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf crash_mdata; + struct list_head etr_buf_list; + struct etr_buf_node *reading_node; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:46 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 06/10] coresight: tmc: add create/delete functions for etr_buf_node Date: Mon, 14 Jul 2025 14:31:05 +0800 Message-Id: <20250714063109.591-7-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=e7gGSbp/ c=1 sm=1 tr=0 ts=6874a455 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=k3jFKW3szlTOC2bxmxAA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: GI2Pce_Zay2WZXAuApOxutH0rS1yZ9_C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfX2iN+yUcoTpaE 2FG92mkp1tLXUtgXdL0ltO6kfUpQUtJ5ARuCvOP2160BenU3O5HTCywewIQ5oZG+UAY0xojF3vx qEQ98sJ4UncfKanP98x1aVTQlckh31gH7VLeXJFjknf2sunGqTIBWztTQ03iyhHZbqjUORO6xRm 1yLrQILg7C1JHe0fNvUbJmvzopB2qpIUHoff09URuRZyr/QXw3G95/rz37hpyNKdSQbDkl5i9jy 0Fwajq5xFUPy4Vom7/e1WYPjKg4e1GDeemKgAePn0IRZF59wltpLVEWRdgBfau9hJllOX2ki22F k5KBjpI5yYrWB+siC495857ODEME+cdOENMn95rD7beg6G9rsE/3c8Usr8sltM0s22DW0Die/UX JmKE0lrm5XOuHXf8sLOrczzkkkYOH/CJs5/jhGhUhJmf0so8dKoLgc7fkq6dOuF1lx2Zky30 X-Proofpoint-ORIG-GUID: GI2Pce_Zay2WZXAuApOxutH0rS1yZ9_C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Create and insert or remove the etr_buf_node to/from the etr_buf_list. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..4609df80ae38 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1909,6 +1909,55 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +static void tmc_delete_etr_buf_node(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D drvdata->sysfs_buf) { + list_del(&nd->node); + kfree(nd); + } else { + /* Free allocated buffers which are not utilized by ETR */ + list_del(&nd->node); + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf =3D NULL; + kfree(nd); + } + } +} + +static int tmc_create_etr_buf_node(struct tmc_drvdata *drvdata, struct etr= _buf *alloc_buf) +{ + struct etr_buf_node *sysfs_buf_node; + struct etr_buf *sysfs_buf; + + if (!alloc_buf) { + sysfs_buf =3D tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0= ), NULL); + if (IS_ERR(sysfs_buf)) + return PTR_ERR(sysfs_buf); + } else { + sysfs_buf =3D alloc_buf; + } + + sysfs_buf_node =3D kzalloc(sizeof(struct etr_buf_node), GFP_KERNEL); + if (IS_ERR(sysfs_buf_node)) { + if (!alloc_buf) + tmc_free_etr_buf(sysfs_buf); + return PTR_ERR(sysfs_buf_node); + } + + sysfs_buf_node->sysfs_buf =3D sysfs_buf; + sysfs_buf_node->reading =3D false; + if (!alloc_buf) + sysfs_buf_node->is_free =3D true; + else + sysfs_buf_node->is_free =3D false; + list_add(&sysfs_buf_node->node, &drvdata->etr_buf_list); + + return 0; +} + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; --=20 2.34.1 From nobody Tue Oct 7 05:44:11 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E11122A4F8 for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:51 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Date: Mon, 14 Jul 2025 14:31:06 +0800 Message-Id: <20250714063109.591-8-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=e7gGSbp/ c=1 sm=1 tr=0 ts=6874a45a cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=xC7plfDI9GgKYcT3xssA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: EbZR5vd7cZEwjww8IB-m03z85rErJZQE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfX8z3oLrpfvnbc /Wg5g+r68ERHreecawrOzl/ZR6CurUO8cxctBNPrRKgAWLRtBeZ9uBaicUEHD8Vkii8R0pZXW9E b0e8/wDJVxm82N4efL+DwZXakT4NOkR7egByZci3TNeo5DKPFO69MQXAf17oQOjQYFL4nPqnfKu AEDrSJERGVLW9Q/spcpvsttYupxtwl4W/eLnFmBDJqxa8YBjS/lKSec9YCBt/ZEtF1M+oW6hwZt nx18NuxaSonYJVzW+9TeMfu8EdzxRscNwugu12A1jxt/qNNQus1M5UjSfV7CQbqRJ5QaXC6l5yE RjMW30JlokNiLr8o1cuxW6ntoInSygj6gFbRVki8DSjNR8CXVNWCsnawex21+BzZUUGKdtsEypb vXeMCK/FpVnV1HU6UqRVVwoLKmBUX7/jI1TcCpx/VpdYGAN6v00WkmbHLLGCZ1chjnPbKfTy X-Proofpoint-ORIG-GUID: EbZR5vd7cZEwjww8IB-m03z85rErJZQE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=799 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Prepare for byte-cntr reading. An additional sysfs_buf is required to receive trace data, as byte-cntr always reads from the deactivated and filled sysfs_buf. The unprepare function releases the additional deactivated sysfs_buf allocated during the prepare phase. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 38 ++++++++- .../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 7 ++ 3 files changed, 120 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 4d249af93097..354faeeddbb2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -230,7 +230,11 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *d= rvdata) =20 static int tmc_read_prepare(struct tmc_drvdata *drvdata) { - int ret =3D 0; + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port, ret =3D 0; =20 switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -238,7 +242,18 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) ret =3D tmc_read_prepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_prepare_byte_cntr(drvdata, byte_cntr_data); + else + ret =3D tmc_read_prepare_etr(drvdata); break; default: ret =3D -EINVAL; @@ -252,7 +267,11 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) =20 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { - int ret =3D 0; + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port, ret =3D 0; =20 switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -260,7 +279,18 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvd= ata) ret =3D tmc_read_unprepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_unprepare_byte_cntr(drvdata, byte_cntr_data); + else + ret =3D tmc_read_unprepare_etr(drvdata); break; default: ret =3D -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 4609df80ae38..2b73bd8074bb 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -2032,6 +2032,85 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvda= ta) return 0; } =20 +int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + unsigned long flags; + int ret =3D 0; + + /* config types are set a boot time and never change */ + if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_SYSFS) + return -EINVAL; + + /* + * The threshold value must not exceed the buffer size. + * A margin should be maintained between the two values to account + * for the time gap between the interrupt and buffer switching. + */ + if (byte_cntr_data->thresh_val + SZ_16K >=3D drvdata->size) { + dev_err(&drvdata->csdev->dev, "The threshold value is too large\n"); + return -EINVAL; + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (byte_cntr_data->reading) { + ret =3D -EBUSY; + goto out_unlock; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + /* Insert current sysfs_buf into the list */ + ret =3D tmc_create_etr_buf_node(drvdata, drvdata->sysfs_buf); + if (!ret) { + /* + * Add one more sysfs_buf for byte-cntr function, byte-cntr always reads + * the data from the buffer which has been synced. Switch the buffer when + * the used buffer is nearly full. The used buffer will be synced and ma= de + * available for reading before switch. + */ + ret =3D tmc_create_etr_buf_node(drvdata, NULL); + if (ret) { + dev_err(&drvdata->csdev->dev, "Failed to create etr_buf_node\n"); + tmc_delete_etr_buf_node(drvdata); + byte_cntr_data->reading =3D false; + goto out; + } + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + atomic_set(&byte_cntr_data->irq_cnt, 0); + enable_irq(byte_cntr_data->byte_cntr_irq); + enable_irq_wake(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->total_size =3D 0; + byte_cntr_data->irq_num =3D 0; + +out_unlock: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + +out: + return ret; +} + +int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct device *dev =3D &drvdata->csdev->dev; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + disable_irq_wake(byte_cntr_data->byte_cntr_irq); + disable_irq(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->reading =3D false; + tmc_delete_etr_buf_node(drvdata); + dev_dbg(dev, "send data total size:%llu bytes, irq_cnt:%d\n", + byte_cntr_data->total_size, byte_cntr_data->irq_num); + + return 0; +} + static const char *const buf_modes_str[] =3D { [ETR_MODE_FLAT] =3D "flat", [ETR_MODE_ETR_SG] =3D "tmc-sg", diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index f6b05639aeca..1dbba0bc50a3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -14,6 +14,8 @@ #include #include =20 +#include "coresight-ctcu.h" + #define TMC_RSZ 0x004 #define TMC_STS 0x00c #define TMC_RRD 0x010 @@ -357,6 +359,11 @@ extern const struct coresight_ops tmc_etr_cs_ops; ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp); =20 +/* Byte-cntr functions */ +int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data); +int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:31:56 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function for byte-cntr Date: Mon, 14 Jul 2025 14:31:07 +0800 Message-Id: <20250714063109.591-9-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfXwyX6MiFgcBdH SOXOYH9g6kgt2+EiGeZ9lJ3WNs4eCACq+B/CgFIGoSHC/MeO4j1ZgkWe0xew/aZIHPouMjJ2d1s Bk736wbzoocF+Ycfua8KwzyDr3/BtGBd2RHhQAIQeYNP8Nx6gVWc6Xi0GNCm1h1+G0UO88KUmlm h3TXj7yFkUczISnah3AtGi5EIumoxYjJTZQGQBAO9nwPx7EfiIJ2NquSv9L98qI7TC7n4vWcPzS 3kQAjaJKX6wiXtRXvywVMENTw9hOGIgY5Q4Y7j/rL/6KgMd4lb0sbMsVb8b+U1x7+SFwv/g4nGY z6GOdUGEKaxBfMlh4Q7A/Px6ixHuTWoWiVKjEipwZjnc7GaSmqcDsGfOpwgbl3T6SFtcOLxnLxX BSwuVa30BQSsuC4byy07vxCg3Uwza0Ibm5W6OcFyP9IEgNSUflDC9KilOFns6l1aJ+pT1spz X-Proofpoint-ORIG-GUID: 9cxcrnnIW301uWfLzFBdF_aKCXfrvMpE X-Proofpoint-GUID: 9cxcrnnIW301uWfLzFBdF_aKCXfrvMpE X-Authority-Analysis: v=2.4 cv=f59IBPyM c=1 sm=1 tr=0 ts=6874a45e cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=wDWrKlMOwBuH9W2KgGoA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. Disable the ETR device if it cannot find an available buffer to switch. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 2b73bd8074bb..3e3e1b5e78ca 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1287,6 +1287,58 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(stru= ct coresight_device *csdev) return ret ? ERR_PTR(ret) : drvdata->sysfs_buf; } =20 +static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node, *picked_node; + struct etr_buf *curr_buf =3D drvdata->sysfs_buf; + bool found_free_buf =3D false; + + if (WARN_ON(!drvdata || !byte_cntr_data)) + return found_free_buf; + + /* Stop the ETR before we start the switching process */ + if (coresight_get_mode(drvdata->csdev) =3D=3D CS_MODE_SYSFS) + __tmc_etr_disable_hw(drvdata); + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf =3D=3D curr_buf) { + nd->is_free =3D true; + curr_node =3D nd; + } + + if (!found_free_buf && nd->is_free && nd->sysfs_buf !=3D curr_buf) { + if (nd->reading) + continue; + + picked_node =3D nd; + found_free_buf =3D true; + } + } + + if (found_free_buf) { + curr_node->reading =3D true; + curr_node->pos =3D 0; + drvdata->reading_node =3D curr_node; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:32:01 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 RESEND 09/10] coresight: tmc: add read function for byte-cntr Date: Mon, 14 Jul 2025 14:31:08 +0800 Message-Id: <20250714063109.591-10-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=e7gGSbp/ c=1 sm=1 tr=0 ts=6874a464 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=56IJ4eEW6NAC_NOVRZQA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: jXBsWRkNyvrLFQ-aP6rgbSSvbZ8v8u-7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfX44lA68k+oDax WNKlejE5vJImj2LXdr3TSbrOF6CXxZ4vNirN9cXcS0L4BYSA7DQ1QM/g9CPZo8fBvpcvLnlEqpt s9Vd8bZRlXN6EWX8e1zFi2fTrB9VRONN/ZqdypurxgkciDlE3PwvIvfRV4bOsoufvtCbKDXisMU 1wcm/ZE3N6C0cQGNuuUZen8wIX3M7Tj8ldM6lTrXAm3CMGJdx8dyGuQ/snBcL1Qm7gYBBXxZuuB I2kAyxiU7b6CgzFObiFzj3Y1HDAAoUbzvuGVE2TLXZitkteVQk8qOwtkHCpOE1YCJ6a5Q1QOove FaipSE3rnSQUwRz/06+3kIFm0Z85ZAn6fenj392EiQbnZT5htGP69POsmrSr2UT6duy4NSBPm1q ZKBwlHY8HEXtwBR4gkv6acGinSe2viAfozes7ozKypWSuZv7w8PwcrUGrlXJMT66G2t1obWo X-Proofpoint-ORIG-GUID: jXBsWRkNyvrLFQ-aP6rgbSSvbZ8v8u-7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" The byte-cntr read function always reads trace data from the deactivated and filled buffer which is already synced. The read function will fail when the ETR cannot find a available buffer to receive trace data. The read function terminates when the path is disabled or interrupted by a signal. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 31 ++++++- .../hwtracing/coresight/coresight-tmc-etr.c | 90 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 3 + 3 files changed, 120 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 354faeeddbb2..3ab25adc4e4d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -318,14 +318,18 @@ static int tmc_open(struct inode *inode, struct file = *file) return 0; } =20 -static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, - char **bufpp) +static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data, + loff_t pos, size_t len, char **bufpp) { switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: case TMC_CONFIG_TYPE_ETF: return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); case TMC_CONFIG_TYPE_ETR: + if (byte_cntr_data && byte_cntr_data->thresh_val) + return tmc_byte_cntr_get_data(drvdata, byte_cntr_data, len, bufpp); + return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); } =20 @@ -339,7 +343,21 @@ static ssize_t tmc_read(struct file *file, char __user= *data, size_t len, ssize_t actual; struct tmc_drvdata *drvdata =3D container_of(file->private_data, struct tmc_drvdata, miscdev); - actual =3D tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port; + + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + actual =3D tmc_get_sysfs_trace(drvdata, byte_cntr_data, *ppos, len, &bufp= ); if (actual <=3D 0) return 0; =20 @@ -349,7 +367,12 @@ static ssize_t tmc_read(struct file *file, char __user= *data, size_t len, return -EFAULT; } =20 - *ppos +=3D actual; + if (byte_cntr_data && byte_cntr_data->thresh_val) { + byte_cntr_data->total_size +=3D actual; + drvdata->reading_node->pos +=3D actual; + } else + *ppos +=3D actual; + dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); =20 return actual; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 3e3e1b5e78ca..174411e76047 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1163,6 +1163,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *= drvdata, ssize_t actual =3D len; struct etr_buf *etr_buf =3D drvdata->sysfs_buf; =20 + /* Reading the buffer from the buf_node if it exists*/ + if (drvdata->reading_node) + etr_buf =3D drvdata->reading_node->sysfs_buf; + if (pos + actual > etr_buf->len) actual =3D etr_buf->len - pos; if (actual <=3D 0) @@ -1339,6 +1343,92 @@ static bool tmc_byte_cntr_switch_buffer(struct tmc_d= rvdata *drvdata, return found_free_buf; } =20 +/* + * tmc_byte_cntr_get_data() - reads data from the deactivated and filled b= uffer. + * The byte-cntr reading work reads data from the deactivated and filled b= uffer. + * The read operation waits for a buffer to become available, either fille= d or + * upon timeout, and then reads trace data from the synced buffer. + */ +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data, + size_t len, char **bufpp) +{ + size_t thresh_val =3D byte_cntr_data->thresh_val; + atomic_t *irq_cnt =3D &byte_cntr_data->irq_cnt; + struct etr_buf *sysfs_buf =3D drvdata->sysfs_buf; + struct device *dev =3D &drvdata->csdev->dev; + struct etr_buf_node *nd, *next; + ssize_t size =3D sysfs_buf->size; + ssize_t actual; + loff_t pos; + int ret; + +wait_buffer: + if (!byte_cntr_data->reading_buf) { + ret =3D wait_event_interruptible_timeout(byte_cntr_data->wq, + ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for byte-cntr\n"); + return -EINVAL; + } + + byte_cntr_data->reading_buf =3D true; + } else { + if (!drvdata->reading_node) { + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D sysfs_buf) { + nd->pos =3D 0; + drvdata->reading_node =3D nd; + break; + } + } + } + + pos =3D drvdata->reading_node->pos; + actual =3D tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); + if (actual > 0) + return actual; + + drvdata->reading_node =3D NULL; + + /* Exit byte-cntr reading */ + return -EINVAL; + } + } + + /* Check the status of current etr_buf*/ + if ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) + /* + * Unlikely to find a free buffer to switch, so just disable + * the ETR for a while. + */ + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) + dev_info(dev, "No available buffer to store data, disable ETR\n"); + + pos =3D drvdata->reading_node->pos; + actual =3D tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); + if (actual =3D=3D 0) { + /* Reading work for marked buffer has finished, reset flags */ + drvdata->reading_node->reading =3D false; + byte_cntr_data->reading_buf =3D false; + drvdata->reading_node =3D NULL; + + /* Nothing in the buffer, wait for next buffer to be filled */ + goto wait_buffer; + } + + return actual; +} + static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) { int ret =3D 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 1dbba0bc50a3..4136ec5ecaf7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -364,6 +364,9 @@ int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvd= ata, struct ctcu_byte_cntr *byte_cntr_data); int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, struct ctcu_byte_cntr *byte_cntr_data); +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data, + size_t len, char **bufpp); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4334005sm86138255ad.158.2025.07.13.23.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 23:32:06 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: [PATCH v3 RESEND 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Date: Mon, 14 Jul 2025 14:31:09 +0800 Message-Id: <20250714063109.591-11-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com> References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: fqqbSo70O1eHUy5GDED52VFWbpR6uLbb X-Proofpoint-ORIG-GUID: fqqbSo70O1eHUy5GDED52VFWbpR6uLbb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDAzNyBTYWx0ZWRfXw36oaD80lcDF WJpRs64hGPqQ3x04knzDbbzn9BSvdCCval6cnaTvKC15HA7fewkdAMijV+Jt2VbvMGKghrtBHyJ I0rm9rK6vmXWs4qPLYS5Oc8pMIpv1eockWx6Oa5tVriH0yiEuyVOHdISJCHa5uJ3ppi9hgobJqj L676WeDwLOeKrFHPx1wgjtZMONDCcEl3PwU9OPZMYkeOqqOCtyWXAaAN8/N2wO5jZdkgPoRjYhF EoJNgIptEq39jVjLBdMJ5cA2qgaNc4R6KZlkE+QW71flB56ygbGig1CslGyF8XpXsf/zQhSwoxg gCjdEl7nxAOaK5BpyPzTRMGukR59JMc4yNsjfip5+sp8sGQ3KELAe3XxxDvsdjA24rmMXaO29YV 4JswOD00gGzwv92bmyIHfjd5rkPF5w7Nv75ELyhmFtKFpDJeD5SA89aMgvAaZAkk/Vg4oimA X-Authority-Analysis: v=2.4 cv=Xc2JzJ55 c=1 sm=1 tr=0 ts=6874a469 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=gBkj9RZkAcI1HbXH1KoA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_01,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 priorityscore=1501 adultscore=0 mlxlogscore=827 phishscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140037 Content-Type: text/plain; charset="utf-8" Add interrupts to enable byte-cntr function for TMC ETR devices. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index fed34717460f..44da72cebcf4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2762,6 +2762,11 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1