From nobody Tue Oct 7 05:42:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BDC9223324; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; cv=none; b=owXfBeXm2UQL5kpAGKzUtOPW+otQJsrOO21CTYLIfUdf0dyS3awIjWq2M5UOPMb8xbdWZ59f+G/+YzdOMSbAHxrYv18slB77HGYopbjT/V2WAZWh8zoEWVo2OWWyglbqJhYKOaa/BvwvlRUJKq6QT8YmozhCyZnYa2514JLpUUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; c=relaxed/simple; bh=XpzvAHUxAzYVFgTQa2ypdhi4koHcoO778v2ak/zqA4E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ndsWBtUjLB5MLpjvv46lqmDp1BICgqS2928WAt8rUtVvz/Ov2fr2i3tL7pBa6Zf0BND6KcxCcifPzmR0ymHxse/wAu54lzLk5cE8WLOt/fhNMt2ow7vG6WWkCHidZkh0RyPfB9axMRgshvIGiM+a5xFrebyqK2kU+hAJwXabCJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HDrDuibB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HDrDuibB" Received: by smtp.kernel.org (Postfix) with ESMTPS id E15EDC4CEF5; Mon, 14 Jul 2025 08:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752480028; bh=XpzvAHUxAzYVFgTQa2ypdhi4koHcoO778v2ak/zqA4E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HDrDuibBTCydpiKJ0NbveuCOlz7D3WxJr3Rf8dLFGuFGFjp0wpaLejaB8MuItUD+1 BL2dih69sQ6thOdZodL3eqIvpYNdPD396Pdhi5xkWqsuTcRN6lzycgmgC5oi8+4jif BN77iEwF2KWHaOVGfgkndxiPW3c3yc7Z3UyaEv7MHbMQdaOdRwWUB9Bbe3MyUEBEPB CfoQaBRoa3BxpUVICYUgQzyOt6HW2nAzvm1rersBHsjZ8JS2t9eQZaExlXZcfaMgQ+ 4+yL/dJACiSGqixmATbMO6Ufr50HRhEZzHxnt2Ndt+mZSt1Xz3I5Z9V8HqlGvXwzyZ m+jMqI87e1UmA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D094CC83F1B; Mon, 14 Jul 2025 08:00:27 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 14 Jul 2025 15:59:17 +0800 Subject: [PATCH net-next 1/3] net: stmmac: xgmac: Disable RX FIFO Overflow interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-xgmac-minor-fixes-v1-1-c34092a88a72@altera.com> References: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> In-Reply-To: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752480026; l=1448; i=rohan.g.thomas@altera.com; s=20250415; h=from:subject:message-id; bh=oFA2+kb2AvW4R/3k8yiyiYdyPGfCRckJUe8sIarPelM=; b=EpWkcMwrFCOnahq0Sl2yqqNCuHkZ5+aiumNQUuGm3nIiRP/zrTLO8zBmThd3neqcinM6oKkYO eznyo+EFxqaBHNVY5L+WIa8S1nkwy9pKMLTjSZ2QiRppcCei+eDBdO+ X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=TLFM1xzY5sPOABaIaXHDNxCAiDwRegVWoy1tP842z5E= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250415 with auth_id=460 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Enabling RX FIFO Overflow interrupts is counterproductive and causes an interrupt storm when RX FIFO overflows. Disabling this interrupt has no side effect and eliminates interrupt storms when the RX FIFO overflows. Commit 8a7cb245cf28 ("net: stmmac: Do not enable RX FIFO overflow interrupts") disables RX FIFO overflow interrupts for DWMAC4 IP and removes the corresponding handling of this interrupt. This patch is doing the same thing for XGMAC IP. Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 5dcc95bc0ad28b756accf9670c5fa00aa94fcfe3..7201a38842651a865493fce0cef= e757d6ae9bafa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -203,10 +203,6 @@ static void dwxgmac2_dma_rx_mode(struct stmmac_priv *p= riv, void __iomem *ioaddr, } =20 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); - - /* Enable MTL RX overflow */ - value =3D readl(ioaddr + XGMAC_MTL_QINTEN(channel)); - writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); } =20 static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *i= oaddr, --=20 2.25.1 From nobody Tue Oct 7 05:42:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65DBA238C2A; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; cv=none; b=Rd1qZshMyGyBZJp+6GdOCi9+P68bvsNCRVkitH1vfuDsEspxHcx1WUD1XZ1DDf0aSymuL/E41sTivvQsZL8oITCEbWUjS6bdo+u1imZudnaCA+ByK3ZJqz0jvLECpTtdkc5VVxQCyhjqFsgiEurlvgd4ut9FEZgwX413nCvedJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; c=relaxed/simple; bh=Yq9Ky8VsS9kS5h5dcxlefIW7mRIPAU0Vre1zK1k0Ea4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qB5HE1E/HnE5p96b4UYSrJQ/Pcu84KBcsqRfuAZml3RDqHX8e1xtiI3xTlqi5JIaJgTa6ngferDIcZ2yplwf0Qxd2p8B6l13o0g73DYCiRTkiSlI53yNRCycbvBckg4wMaSkhwXoHThEqQbpSjOBcYN0Pspq2CQI9Wfw1EL/WNY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qGCb2CXk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qGCb2CXk" Received: by smtp.kernel.org (Postfix) with ESMTPS id F04E2C4CEF6; Mon, 14 Jul 2025 08:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752480028; bh=Yq9Ky8VsS9kS5h5dcxlefIW7mRIPAU0Vre1zK1k0Ea4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qGCb2CXkje7zXwMgiKGRFwYLDG3zmn/ZpoZeYWwh1HUsfwd6S8Vw3Ej8UiaZYfLDG VF8xEAEKbOvJWsPjyVvnFvKuttOqIKEkgH7le3gn4yrjcLDtwyObny2NGDp+zmmP9T d7eVQOSaTXGAvAt0EenJ5ANVc/raFw3lpl15R+rDGnLPmBqvs1XU48i4K1pwCoZHkg yZ0sd2iK3r1Qqv3zXbGw6/mlitOU3i+eBknBvY86FDqRHuOcdAG37Zs+GSmKsOuPE3 7nzZfLwgl1QS+nyzPZJ+yH1UyZ+6P9B1gqKe96VsG5QKoVODEJqnthacAmLkDKT8Xx 0+BBn5tlxhcnQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2BFBC83F17; Mon, 14 Jul 2025 08:00:27 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 14 Jul 2025 15:59:18 +0800 Subject: [PATCH net-next 2/3] net: stmmac: xgmac: Correct supported speed modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-xgmac-minor-fixes-v1-2-c34092a88a72@altera.com> References: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> In-Reply-To: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752480026; l=3261; i=rohan.g.thomas@altera.com; s=20250415; h=from:subject:message-id; bh=VG2Dfp/g/YHOIG/+Mje0Iha3SvShc7S+fE/4uX6Rxa8=; b=29subWKkHTxTo19LkKQVvEstduVel5NjOed85DdVpVPrwfoUX/brn1WLcLhYZQ6vSGC/oJi4Z gyR00E9wtRHB/2xExpa7WovLQbH+oFfvQeuK18Mpca1mKfEL9fNfuOx X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=TLFM1xzY5sPOABaIaXHDNxCAiDwRegVWoy1tP842z5E= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250415 with auth_id=460 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Correct supported speed modes as per the XGMAC databook. Commit 9cb54af214a7 ("net: stmmac: Fix IP-cores specific MAC capabilities") removes support for 10M, 100M and 1000HD. 1000HD is not supported by XGMAC IP, but it does support 10M and 100M FD mode, and it also supports 10M and 100M HD mode if the HDSEL bit is set in the MAC_HW_FEATURE0 reg. This commit adds support for 10M and 100M speed modes for XGMAC IP. Fixes: 9cb54af214a7 ("net: stmmac: Fix IP-cores specific MAC capabilities") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 14 ++++++++++++-- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 6cadf8de4fdfdb18af1a112b883b3d33a53da638..3cef8ba5a7f6c1b02881b8a4ac1= eadb18ecfece4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -49,6 +49,15 @@ static void dwxgmac2_core_init(struct mac_device_info *h= w, writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN); } =20 +static void dwxgmac2_update_caps(struct stmmac_priv *priv) +{ + /* If HDSEL bit is set in MAC_HW_Feature0 register then XGMAC supports + * half duplex mode but only for 10Mbps and 100Mbps speed modes. + */ + if (priv->dma_cap.half_duplex) + priv->hw->link.caps |=3D (MAC_10HD | MAC_100HD); +} + static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable) { u32 tx =3D readl(ioaddr + XGMAC_TX_CONFIG); @@ -1424,6 +1433,7 @@ static void dwxgmac2_set_arp_offload(struct mac_devic= e_info *hw, bool en, =20 const struct stmmac_ops dwxgmac210_ops =3D { .core_init =3D dwxgmac2_core_init, + .update_caps =3D dwxgmac2_update_caps, .set_mac =3D dwxgmac2_set_mac, .rx_ipc =3D dwxgmac2_rx_ipc, .rx_queue_enable =3D dwxgmac2_rx_queue_enable, @@ -1532,8 +1542,8 @@ int dwxgmac2_setup(struct stmmac_priv *priv) mac->mcast_bits_log2 =3D ilog2(mac->multicast_filter_bins); =20 mac->link.caps =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | - MAC_1000FD | MAC_2500FD | MAC_5000FD | - MAC_10000FD; + MAC_10FD | MAC_100FD | MAC_1000FD | + MAC_2500FD | MAC_5000FD | MAC_10000FD; mac->link.duplex =3D 0; mac->link.speed10 =3D XGMAC_CONFIG_SS_10_MII; mac->link.speed100 =3D XGMAC_CONFIG_SS_100_MII; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 7201a38842651a865493fce0cefe757d6ae9bafa..76a98d28f9de693ef6cb4c115e3= 8f69c9a965b54 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -405,6 +405,7 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, dma_cap->sma_mdio =3D (hw_cap & XGMAC_HWFEAT_SMASEL) >> 5; dma_cap->vlhash =3D (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4; dma_cap->half_duplex =3D (hw_cap & XGMAC_HWFEAT_HDSEL) >> 3; + dma_cap->mbps_10_100 =3D (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; dma_cap->mbps_1000 =3D (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; =20 /* MAC HW feature 1 */ --=20 2.25.1 From nobody Tue Oct 7 05:42:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C9CF23B60C; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; cv=none; b=YwH23nsxRXKtQMwYjm3+M2JvDn77wqrHBsUALt/UJxJjQAFE2aLTMNT3L+KpOghuBHdwOOiR7qi68uh5uu0UIofa6FMjqwWEyQ3UOz8zyzfZ3KaFGMnDDoRB44m4FW3avdjiwpl1hZrOKXnhmWDSEf0YtEBBPJ5VqzWwrzJiwt4= ARC-Message-Signature: i=1; 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b=SsWHKG2VfLrNDRnFq2SpYGq13L3B63E9GyIaK15LFX6KJLVMsDV1xnICzky9sPJuE 6tsHQeXiiLND5vInv5rjbMsZARXfkjgP6J3x0PzWAPf+fvqHmD0/wXzkeZ9JNUvqS1 uRpSyZgmfWauEAoqi1SEKAQKr0VeruXka+hiJWAlbsJnAr/frPfiSub7J3xgtaU73L ehhU8vaklbAyCkFUIm568cyTBI/l1sl1+3+B1UFGG48h3uEKgSsNDgJdrp69bFObst 93BPpqvugss7j9QgdKBRKk2dVjoE/wgV7l6bxdilwVGwNSyHQ+TwnjBkjHQtpVrU/p DVFlCSsSPMT/Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 004EFC83F25; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 14 Jul 2025 15:59:19 +0800 Subject: [PATCH net-next 3/3] net: stmmac: Set CIC bit only for TX queues with COE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-xgmac-minor-fixes-v1-3-c34092a88a72@altera.com> References: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> In-Reply-To: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752480026; l=2519; i=rohan.g.thomas@altera.com; s=20250415; h=from:subject:message-id; bh=LvG0a5gBZ5g9VJhz1xFTiPD3FiH+GWS8NxcWQcWl6tc=; b=fVE9HlJaErdbIModd8D71uXp7Ny7wlJiiE+7BHU4coROJ/HaDD30Ly3V5zU8VBfqhYvYFE9wP g7WemhMLVucCOrtR+ZTEuvc3FgAK2dfr1Dr9e90L76eE7gmhl75xTAw X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=TLFM1xzY5sPOABaIaXHDNxCAiDwRegVWoy1tP842z5E= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250415 with auth_id=460 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Currently, in the AF_XDP transmit paths, the CIC bit of TX Desc3 is set for all packets. Setting this bit for packets transmitting through queues that don't support checksum offloading causes the TX DMA to get stuck after transmitting some packets. This patch ensures the CIC bit of TX Desc3 is set only if the TX queue supports checksum offloading. Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index f350a6662880a230a32ad6785c475cce4e950322..d9f7435a44fac695899e0b4ffd0= dc7851c4e759f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2584,6 +2584,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *pr= iv, u32 queue, u32 budget) struct netdev_queue *nq =3D netdev_get_tx_queue(priv->dev, queue); struct stmmac_tx_queue *tx_q =3D &priv->dma_conf.tx_queue[queue]; struct stmmac_txq_stats *txq_stats =3D &priv->xstats.txq_stats[queue]; + bool csum =3D !priv->plat->tx_queues_cfg[queue].coe_unsupported; struct xsk_buff_pool *pool =3D tx_q->xsk_pool; unsigned int entry =3D tx_q->cur_tx; struct dma_desc *tx_desc =3D NULL; @@ -2671,7 +2672,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *pr= iv, u32 queue, u32 budget) } =20 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdp_desc.len); =20 stmmac_enable_dma_transmission(priv, priv->ioaddr, queue); @@ -4983,6 +4984,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *p= riv, int queue, { struct stmmac_txq_stats *txq_stats =3D &priv->xstats.txq_stats[queue]; struct stmmac_tx_queue *tx_q =3D &priv->dma_conf.tx_queue[queue]; + bool csum =3D !priv->plat->tx_queues_cfg[queue].coe_unsupported; unsigned int entry =3D tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; @@ -5034,7 +5036,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *p= riv, int queue, stmmac_set_desc_addr(priv, tx_desc, dma_addr); =20 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdpf->len); =20 tx_q->tx_count_frames++; --=20 2.25.1